KR100615202B1 - Thin film transistor, method of the TFT, and flat panel display device with the TFT - Google Patents

Abstract

According to an aspect of the present invention, there is provided a thin film transistor including a gate electrode formed on an upper surface of a substrate, a semiconductor active layer formed on an upper portion of the gate electrode, and a source and drain electrode formed on an upper surface of the semiconductor active layer. One side facing the source and drain electrodes is provided with an etched portion having a predetermined depth, and a region corresponding to the etched portion of the semiconductor active layer generally has a MILC crystal, and other regions generally have a MIC crystal. Provided are a thin film transistor, a method of manufacturing the same, and a flat panel display device having the same, particularly an organic electroluminescent display device.

Description

Thin film transistor, method of manufacturing thin film transistor, and flat panel display device having the same {Thin film transistor, method of the TFT, and flat panel display device with the TFT}

1A to 1E are a process diagram of manufacturing a thin film transistor having an upper gate structure according to the prior art,

2a to 2e is a manufacturing process diagram of a thin film transistor and an organic electroluminescent display device having a lower gate structure according to an embodiment of the present invention,

3 is a schematic diagram of a manufacturing process of a thin film transistor having a bottom gate structure according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a thin-film transistor (TFT) of a bottom gate structure in which a semiconductor active layer is crystallized using a metal induction crystallization method and a method of manufacturing the same. And a flat panel display device, in particular an organic electroluminescent display, comprising the thin film transistor.

In flat panel display devices such as liquid crystal display devices and organic electroluminescent display devices, various thin film transistors (TFTs) such as thin film transistors for driving such devices are provided.

The thin film transistor has a gate electrode, a source and a drain electrode, and a semiconductor layer activated by driving of the gate electrode, and the thin film transistor has a top gate or normal staggered thin film transistor according to the stacking order of these layers. And a thin film transistor having a bottom gate structure (bottom gate or inverted staggered). The semiconductor layer constituting the thin film transistor is generally composed of a silicon layer. According to the prior art, the semiconductor active layer is composed of amorphous silicon (a-Si), but the amorphous silicon is, for example, 1 cm 2 / Vs or less. While it has a low electron mobility of, poly-silicon has an electron mobility of about 100 cm 2 / Vs, and satisfies the technology trend of decreasing size and gradually decreasing aperture ratio. In view of this, in recent years, a technique for crystallizing amorphous silicon into polycrystalline silicon has been developed.

The polycrystalline silicon as described above may be manufactured by various methods, which may be classified into two methods, a method of directly depositing polycrystalline silicon and a method of depositing amorphous silicon and then crystallizing it.

Direct deposition of polycrystalline silicon includes chemical vapor deposition (CVD), photo CVD, hydrogen radical (HR) CVD, electron cyclotron resonance (ECR) CVD, plasma enhanced (CVD) CVD, and low pressure (CVD) CVD. Etc.

Meanwhile, the method of crystallizing amorphous silicon after deposition includes solid phase crystallization (SPC), excimer laser annealing, sequential lateral solidification (SLS), and metal induced crystallization (metal). Induced Crystallization (MIC), and Metal Induced Lateral Crystallization (MILC).

However, since the solid phase crystallization method must be maintained at a high temperature of 600 ° C. or more for a long time, its practicality is remarkably inferior.

The excimer laser method has an advantage of achieving low temperature crystallization, but causes a problem of inferior uniformity by widening the laser beam using an optical system.

Continuous lateral solidification is a method of forming a polycrystalline silicon in a local region while crystallizing the amorphous silicon by scanning the laser through a chevron-shaped mask to the amorphous silicon, which is a technical difficulty in precisely controlling the scanning of the laser light. As a result, there is a limit to obtaining a polycrystalline silicon thin film with uniform characteristics.

On the other hand, the metal induction crystallization method has the advantage that the crystallization temperature can be lowered by depositing a metal thin film on the surface of the amorphous silicon and using it as a crystallization catalyst to proceed with the crystallization of the silicon film. However, this metal-induced crystallization method also causes the polycrystalline silicon film to be contaminated by metal, resulting in poor characteristics of the thin film transistor element formed from this silicon film, and the crystals formed also have small size and disordered problems.

Recently, in order to solve the problems of the conventional amorphous silicon crystallization methods, a metal-induced side crystallization method which sequentially induces crystallization while silicide generated by reacting metal and silicon continues to propagate to the side has been proposed. This metal-induced lateral crystallization method is characterized by the fact that the metal component used to crystallize the amorphous silicon layer hardly remains in the semiconductor active layer region, and because the crystal is large and directional, the leakage of current due to the residual metal component and other electrical There is no deterioration of the properties, there is an advantage that can induce crystallization at a relatively low temperature of 300 to 500 ℃.

Japanese Patent Laid-Open No. 7-58339 discloses a method for manufacturing a thin film transistor having an upper gate structure using metal induced side crystallization, as shown in FIGS. 1A to 1E. 1A and 1B, a buffer layer 102 is formed on a substrate 101, a metal layer is applied to a region of the opening 100 using a mask 103 having the opening 100 formed thereon, and then an amorphous layer thereon. The amorphous silicon layer was crystallized into a polycrystalline silicon layer by depositing and annealing the silicon layer. A thin film transistor is fabricated by patterning a polycrystalline silicon layer (see FIG. 1C) and forming a gate insulating layer 106 and a gate electrode 107 thereon (see FIGS. 1D and 1E). There is a problem that the process time is considerably longer, such as the silicon layer must be etched through a separate patterning process. In the prior art, since the metal layer is formed on the amorphous silicon layer and then heat treated immediately, not only the portion adjacent to the metal layer but also a substantial portion of the amorphous silicon layer, the metal component of the metal layer is retained at a high concentration, causing current leakage. The problem is that it can be done. These problems caused by the prior art are more prominent when the technique is applied to a thin film transistor having a bottom gate structure.

When the amorphous silicon layer of the lower gate structure thin film transistor is crystallized into a polycrystalline silicon layer, a laser irradiation method such as an excimer laser method is mainly used due to its structural characteristics. For example, Korean Patent Publication No. 269350 discloses a gate electrode on a substrate. Is formed, an insulating layer is formed, and then an amorphous silicon film is formed over the gate electrode and scanned using a laser beam. However, these prior art methods involve a problem that the process is complicated, various equipments are involved, and the production yield due to the cumbersome work process is significantly reduced.

The present invention, in order to solve the problems caused by the prior art through a simple process, crystallization of the source and drain regions by introducing a trace amount of the crystalline catalyst component into the semiconductor active layer, and from the side-induced crystallization of the channel region therefrom and fabrication thereof It is an object of the present invention to provide a flat display device, in particular an organic electroluminescent device, having such a thin film transistor.

In order to achieve the above object, according to an aspect of the present invention, a gate electrode formed on one side of the substrate, a semiconductor active layer formed on the gate electrode, and a source and drain electrode formed on the one surface of the semiconductor active layer In the thin film transistor having the semiconductor active layer, one surface facing the source and drain electrodes is provided with an etched portion embedded in a predetermined depth, the region corresponding to the etched portion of the semiconductor active layer is generally a MILC crystal And other regions generally have MIC crystals.

According to another aspect of the present invention, a region having a MILC crystal is a channel region of the semiconductor active layer, and a region having the MIC crystal is a source and a drain region.

According to another aspect of the invention, at least a portion of the upper surface of the semiconductor active layer is provided with a thin film transistor, characterized in that the crystal catalyst material layer is provided.

According to another aspect of the invention, the crystalline catalyst material is Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt Provided is a thin film transistor, characterized in that any one or more of metal materials.

According to another aspect of the present invention, the crystalline catalyst material layer provides a thin film transistor, characterized in that provided in the region excluding the etching portion.

According to another aspect of the invention, forming a gate electrode on a substrate, forming an amorphous silicon layer on the gate electrode so as to be insulated from it, and diffusing a crystalline catalyst material on the upper surface of the amorphous silicon layer Forming a source and drain electrode on top of the amorphous silicon layer, etching a portion of the amorphous silicon layer to a predetermined depth, and heat treating the amorphous silicon layer to crystallize it. A method of manufacturing a thin film transistor is provided.

According to another aspect of the present invention, the forming of the source and drain electrodes includes applying and patterning the source and drain material layers, and etching the portion of the amorphous silicon layer comprises: A thin film transistor manufacturing method is performed at the same time as patterning of an electrode.

According to another aspect of the invention, the etching step provides a method for manufacturing a thin film transistor, characterized in that for etching the region corresponding to the channel region of the amorphous silicon layer.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, characterized in that by the etching step, the crystalline catalyst material in at least a portion of the amorphous silicon layer is removed.

According to another aspect of the invention, the step of crystallizing by the heat treatment provides a method for manufacturing a thin film transistor, characterized in that is performed after forming an insulating layer on top of the source and drain electrodes.

According to another aspect of the invention, the diffusion step provides a method of manufacturing a thin film transistor, characterized in that it comprises the step of depositing and removing the crystalline catalyst material.

According to another aspect of the invention, the diffusion step comprises the steps of forming an insulating layer on the amorphous silicon layer, depositing the crystalline catalyst material, heat treatment to diffuse the deposited crystalline catalyst material, and heat treatment And then removing the remaining crystalline catalyst material.

According to still another aspect of the present invention, there is provided a flat panel display device including a thin film transistor formed on one surface of a substrate, wherein the thin film transistor includes a gate electrode, a semiconductor active layer formed on the gate electrode, and one surface of the semiconductor active layer. A flat panel display device having a source and a drain electrode formed thereon, wherein one surface of the semiconductor active layer facing the source and drain electrodes is provided with an etched portion having a predetermined depth, and the etching portion of the semiconductor active layer A flat area display device is characterized in that the corresponding regions generally have MILC crystals, and the other regions generally have MIC crystals.

According to another aspect of the present invention, a region having the MILC crystal is a channel region of the semiconductor active layer, and a region having the MIC crystal is a source and drain region.

According to another aspect of the invention, at least a portion of the upper surface of the semiconductor active layer is provided with a flat display device, characterized in that the crystal catalyst material layer is provided.

According to another aspect of the invention, the crystalline catalyst material is Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt Provided is a flat panel display device characterized in that any one or more of the metal materials.

According to another aspect of the present invention, the crystal catalyst material layer is provided in a region except for the etching portion provides a flat panel display device.

According to yet another aspect of the present invention, there is provided an organic electroluminescent display device having a thin film transistor formed on one surface of a substrate, wherein the thin film transistor comprises a gate electrode, a semiconductor active layer formed on the gate electrode, and the semiconductor. An organic electroluminescent display device having source and drain electrodes formed on one surface of an active layer, wherein one surface of the semiconductor active layer facing the source and drain electrodes is provided with an etched portion having a predetermined depth, and the semiconductor active layer includes: The region corresponding to the etch portion generally has a MILC crystal, and the other regions generally have a MIC crystal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E schematically illustrate a manufacturing process of a thin film transistor and an organic EL device according to an embodiment of the present invention.

As shown in FIG. 2A, a gate metal layer is formed on a substrate 201 using a material such as, for example, Cu, Al, Mo, MoW, Cr, or MoTa, and then gate patterned to form a gate electrode 210. ), Which is preferably formed of MoW in order to retain the heat resistance to the heat treatment in the future crystallization step. Although not shown in the drawing, when the gate electrode 210 is formed, the capacitor electrode may be formed of the same material at a position adjacent to the gate electrode 210.

In order to insulate the gate electrode 210, the gate insulating layer 220 is deposited. The gate insulating layer 220 is preferably made of SiO 2, SiN x, or the like. An amorphous silicon layer (a-Si: H, 230) is formed on one surface of the gate insulating layer 230. In order to reduce the resistance between the source and drain electrodes to be formed later and the undoped amorphous silicon layer 230 and to reduce the leakage current due to hole conduction, on one surface of the amorphous silicon layer 230, for example, highly doped n + amorphous Silicon layer 231 may be deposited, which is subsequently crystallized into a polycrystalline silicon layer through a crystallization step, acting as a semiconductor active layer, and these amorphous silicon layers 230 and 231 It can be patterned using the same mask.

On one surface of the n + amorphous silicon layer 231, for example, Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, The metal layer 231a composed of any one or more of Ag, Cu, and Pt is deposited and then removed again. Preferably, the metal layer 231a is made of Ni, but this crystal catalyst material is not limited to pure metal, and a material such as nickel silicide may be used. Due to the deposition process of the metal layer 231a, a small amount of metal constituting the metal layer 231a remains on one surface of the n + amorphous silicon layer 231 from which the metal layer 231a has been removed, The metal may be introduced or diffused into the n + amorphous silicon layer 231, in some cases beyond the n + amorphous silicon layer 231, to at least a portion of the undoped amorphous silicon layer 230.

In addition, the introduction or diffusion of the metal component according to another embodiment of the present invention is shown in FIG. 3. An insulator layer (insulating layer) 231b is first formed on one surface of the n + amorphous silicon layer 231, and Ni, Pd, Au, Sn as a predetermined crystal catalyst material is formed on one surface of the insulator layer 231b. A metal layer 231a composed of any one or more of Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt is deposited. The metal component of the metal layer 231a then extends to at least a portion of the n + amorphous silicon layer 231, or in some cases beyond the n + amorphous silicon layer 231 to at least a portion of the undoped amorphous silicon layer 230. It is heat-treated so that it can be drawn in, or diffused. After the heat treatment, the metal layer 231a and the insulator layer 231b are removed. The amount of the crystalline catalyst material introduced into the amorphous silicon layer 230 or 231 may be controlled by appropriately adjusting the thickness of the insulator layer 231b and the heat treatment temperature and time.

Through this process, at least a portion of the semiconductor active layer to be later polycrystallized may be provided with a crystalline catalyst material or a crystalline catalyst material layer.

After the introduction process of the metal component preset as the crystal catalyst component, as shown in FIG. 2B, the source and drain electrodes 240a and b are patterned and formed on one surface of the n + amorphous silicon layer 231. That is, it may be patterned after forming a layer by applying a material constituting the source and drain electrodes 240a and b. After the source and drain electrodes 240a and b are formed, a portion (so-called back channel) corresponding to the position of the gate electrode 210 is etched between the source and drain electrodes 240a and b. Dry etching is preferably performed to improve the resolution without causing an undercut on the side surface 232a. The etch 232 is preferably embedded in at least a portion of the n + amorphous silicon layer 231 and / or the undoped amorphous silicon layer 230. That is, the bottom surface 232b of the etching portion 232 preferably enters at least a portion of the undoped amorphous silicon layer 230 in the direction from the source and drain electrodes 240a and b toward the gate electrode 210. . The depth of the etched portion 232 may be determined according to the extent (concentration) of the metal component as the crystal catalyst material, or the depth of the etched portion 232. The bottom surface 232b of the etched portion 232 may be formed in the undoped amorphous silicon layer 230. Therefore, it is preferable that the crystal catalyst material reaches a region where at least a part is removed, and most preferably reaches a region where it is hardly present. Therefore, through this process, the crystalline catalyst material or the crystalline catalyst material layer may be provided in a region excluding the etching portion 232 in the amorphous silicon layers 230 and 231.

Thereafter, the amorphous silicon layers 230 and 231 are crystallized through an annealing process such as heat treatment to turn into polycrystalline silicon layers 230 'and 231', which are stacked below the source and drain electrodes 240a and b during the annealing process. One or more passivation layers 250, 260 (see FIG. 2D) may be further provided to protect the structure and improve device characteristics.

As shown in FIG. 2C, during this annealing, ie, heat treatment, an amorphous silicon layer is introduced into the undoped amorphous silicon layer 231, ie by a residual or diffused crystalline catalyst material, for example a metal component such as Ni. Crystals grow at (230, 231). Accordingly, metal induced crystallization (MIC) is performed in the source and drain regions 230'a and b of the amorphous silicon layers 230 and 231 corresponding to the source and drain electrodes 240a and b, The channel region 230'c between the source and drain regions crystallized by the MIC is subjected to metal induced lateral crystallization (MILC) from the source and drain regions 230'a and b. In some cases, metal induced crystallization may occur due to the crystal catalyst material remaining on the bottom surface 232b of the etching portion 232 in the channel region 230'c, but the source and drain regions 230'a and b may be formed. Occupies a considerably small portion for lateral crystallization from Therefore, through the thin film transistor and the manufacturing method thereof according to the present invention, the crystallization of the source and drain regions and the channel region of the amorphous silicon layer 230 is crystallized by different types. That is, the source and drain regions of the amorphous silicon layer may be MIC formed, and the channel region may be MILC formed.

On the other hand, according to another embodiment of the present invention, the thin film transistor and its manufacturing method may be provided in a flat panel display device, preferably an organic electroluminescent display device and a manufacturing method thereof. For example, in the case of the organic electroluminescent display device, as shown in FIG. 2E, the first electrode layer 270, the pixel defining layer 280, the organic electroluminescent unit 290, and the second electrode layer ( And a pixel portion including 295.

One or more passivation layers 250 and 260 are formed on one surface of the source and drain electrodes 240a and b, and contact holes 261 are formed in the passivation layers 250 and 260 to extend to the drain electrode 240b. . Thereafter, a first electrode layer 270 serving as an anode having a first electrode connecting portion 271 formed in the contact hole 261 is formed on at least a portion of the passivation layer 260, for example, at a gate electrode. It is formed at the location of the adjacent area. After the first electrode layer 270 is formed, a pixel defining layer 280 is formed to cover the passivation layer 260 and at least a portion of the first electrode layer 270, which is defined as a pixel defining layer 280. It has a constant opening area, that is, a pixel area, and also serves as a planarization layer. An organic light emitting unit 290 is formed on one surface of the first electrode layer 270 as the pixel region. A second electrode layer 295 as a cathode is formed to cover the pixel defining layer 280 and the pixel region, specifically the organic electroluminescent portion 290.

Accordingly, holes or electrons controlled by the first electrode layer and the second electrode layer driven by the thin film transistor having the lower gate structure according to the present invention are recombined in the organic light emitting part of the organic electroluminescent part 290 so that the organic light emitting part is self-luminous. By this, light can be taken out to the outside.

According to the present invention as described above, the channel region of the amorphous silicon layer is lateral through a simple process of drawing a small amount of the crystalline catalyst material on one surface of the amorphous silicon layer and then etching at least a portion of the channel region of the amorphous silicon layer. By inductively crystallizing the polycrystallized channel region, it is possible to fabricate a thin film transistor having a lower gate structure with a significantly reduced leakage current.

In addition, in the case where the crystalline catalyst material is introduced onto one surface of the amorphous silicon layer, only a small amount of the crystalline catalyst material in the source and drain regions of the amorphous silicon layer may be removed by depositing and removing the crystalline catalyst material layer or heat treatment through the insulator layer. Residual or diffusion may significantly increase the driving efficiency of the thin film transistor by removing the crystalline catalyst material in the channel region adjacent the source and drain regions.

In addition, by manufacturing a flat panel display device, in particular an organic electroluminescent display device using the above-described thin film transistor, and in the organic electroluminescent display device having a thin film transistor manufactured by the prior art, in particular, Excimer Laser Annealing (ELA) Alternatively, it may lead to stability of the production process, simplification of the process flow and increased yield.

In particular, since the 5 Mask process using five masks is possible up to the process of forming an opening in the passivation layer formed on the thin film transistor and forming the first electrode layer, the same as described above in the conventional a-Si thin film transistor process. Since a poly-Si thin film transistor and a flat panel display device having the same can be produced by the addition of a simple process, a thin film transistor having an effective driving performance using a conventional a-Si thin film transistor production apparatus without any increase in production cost is provided. It can also produce.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

Claims (18)

A thin film transistor comprising a gate electrode formed on an upper surface of a substrate, a semiconductor active layer formed on an upper portion of the gate electrode, and a source and drain electrode formed on an upper surface of the semiconductor active layer. An etching portion embedded in a channel region on one surface of the semiconductor active layer facing the source and drain electrodes; A portion of the upper surface of the semiconductor active layer except for the etching portion includes a crystal catalyst material layer, Wherein the source and drain regions of the semiconductor active layer have a MIC crystal and the channel region has a MILC crystal. delete delete The method of claim 1, wherein the crystal catalyst material is any one of Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt. The thin film transistor characterized by the above-mentioned metal substance. delete Forming a gate electrode on the substrate; Forming an amorphous silicon layer over and insulated from the gate electrode; Diffusing a crystalline catalyst material on an upper surface of the amorphous silicon layer; Forming source and drain electrodes on top of the amorphous silicon layer; Etching a portion of the amorphous silicon layer to remove the crystalline catalyst material; and Thermally treating the amorphous silicon layer to crystallize, The diffusing of the crystalline catalyst material may include forming an insulating layer on an upper surface of the amorphous silicon layer and diffusing the crystalline catalyst material after forming the crystalline catalyst material on the upper surface of the insulating layer. . 7. The method of claim 6, wherein forming the source and drain electrodes comprises applying and patterning the source and drain material layers, and etching a portion of the amorphous silicon layer comprises patterning the source and drain electrodes. A thin film transistor manufacturing method characterized in that the step is carried out simultaneously. The method of claim 6, wherein the etching comprises etching an area corresponding to a channel region of the amorphous silicon layer. delete 7. The method of claim 6, wherein the step of crystallizing by heat treatment is performed after forming an insulating layer on top of the source and drain electrodes. The method of claim 6, wherein the diffusing step comprises depositing and removing the crystalline catalyst material. 7. The method of claim 6, wherein the diffusing step comprises forming an insulating layer over the amorphous silicon layer, depositing the crystalline catalyst material, heat treatment to diffuse the deposited crystalline catalyst material, and remaining after the heat treatment. Removing the crystalline catalyst material. A flat panel display device having a thin film transistor formed on an upper surface of a substrate, the thin film transistor comprising: A flat panel display device comprising a gate electrode, a semiconductor active layer formed over the gate electrode, and a source and drain electrode formed over one surface of the semiconductor active layer. An etching portion embedded in a channel region on one surface of the semiconductor active layer facing the source and drain electrodes; A portion of the upper surface of the semiconductor active layer except for the etching portion includes a crystal catalyst material layer, And the channel region of the semiconductor active layer has a MIC crystal, and the channel region has a MILC crystal. delete delete The method of claim 13, wherein the crystal catalyst material is any one of Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt. The flat metal display element characterized by the above-mentioned metal substance. delete An organic electroluminescent display device having a thin film transistor formed on an upper surface of a substrate, the thin film transistor comprising: An organic electroluminescent display device comprising a gate electrode, a semiconductor active layer formed over the gate electrode, and a source and drain electrode formed over one surface of the semiconductor active layer. An etching portion embedded in a channel region on one surface of the semiconductor active layer facing the source and drain electrodes; A portion of the upper surface of the semiconductor active layer except for the etching portion includes a crystal catalyst material layer, Wherein the source and drain regions of the semiconductor active layer have a MIC crystal and the channel region has a MILC crystal.

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