KR100606368B1 - Apparatus and method for clock recovery in ATM receiver - Google Patents

Abstract

The present invention provides a clock recovery apparatus and method thereof in an ATM receiver, comprising: a difference value calculator for calculating a difference value between a write cell address and a read cell address; An average value extracting unit obtaining an average value of the difference values calculated by the difference value calculating unit, and obtaining an average value of an address at which a cell buffer is currently read and a currently reading data address; And a threshold controller configured to control the threshold value to an intermediate value of the average value output from the average value extractor to adjust the up / down of the output clock. By adjusting the read speed, the buffer's efficient management and output jitter can be minimized.

Description

Apparatus and method for clock recovery in ATM receiver

1 is a block diagram of a clock recovery device and its neighboring blocks in a conventional ATM receiver;

2 is a flowchart illustrating a clock recovery method in a conventional ATM receiver.

3 is a block diagram of a clock recovery device and its neighboring block in an ATM receiver according to the present invention;

4 is a flowchart illustrating a clock recovery method in an ATM receiver according to the present invention.

Explanation of symbols on the main parts of the drawings

100: difference value calculation unit 200: average value extraction unit

210: first average value calculator 211 to 214: first to fourth delay units

215: first adding unit 220: second average value calculating unit

221 to 224: fifth to eighth delay units 225: second adder

300: limit control unit 410: 256 counter

420: delay unit 430: up / down control unit

440 DS1E Distribution Counter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for recovering a clock in an Asynchronous Transfer Mode (Asynchronous Receiver) receiver. In particular, in an ATM cell receiver, a buffer is controlled by adjusting a read speed to a buffer so that a receiving cell buffer maintains an appropriate amount of data. An apparatus and method for clock recovery in an ATM receiver suitable for minimizing output management and minimizing output jitter.

In general, ATM is determined by ITU-T (formerly CCITT) as a transmission method of B-ISDN (Broadband Integrated Services Digital Network) in 1988, which is a core transmission and switching technology of B-ISDN. This is a method of dividing all information into fixed length blocks called ATM cells and transmitting them sequentially.

The header contains a Virtual Channel Identifier (VCI) for identifying the connection to which the cell belongs, a Virtual Path Identifier (VPI), and a Cell Loss Priority indicating whether the cell should be discarded during congestion. , CLP), cell information identification (Payload Type, PT) for distinguishing network control information, header error detection and control (Header Error Control, HEC), and the like. The feature of ATM multiplexing is that the multiplexing efficiency is higher than that of partitioning due to statistical multiplexing, and the transmission band allocated to individual communication can be freely set. In the ATM exchange, since the routine information is stored in the header, each ATM exchanger can independently relay and exchange cells, and the exchange processing can be realized in hardware, thereby improving the exchange speed.

The ATM switching network consists of two levels of networks called virtual paths (VPs) and virtual channels (VCs). As described above, ATM inherits high transmission efficiency of packet switching and corrects a decrease in switching delay line use efficiency, which is a disadvantage of circuit switching, so that various information can be processed at high speed.

The ATM receiver then operates to receive and process these ATM cells.

1 is a block diagram of a clock recovery apparatus and its neighboring blocks in a conventional ATM receiver.

As shown therein, a difference value calculator 10 for calculating a difference value between a write cell address WCELLAD and a read cell address RCELLAD; An average value extraction unit 20 for extracting an average value of the four difference values from the difference value calculation unit 10; The threshold value control unit 30 is configured to control the threshold value to the intermediate value of the average value output from the average value extraction unit 20 to adjust the output clock up / down.

The average value extractor 20 includes: first to fourth delay units 21 to 24 for sequentially delaying the output of the difference calculator 10; And an adder 25 which adds the outputs of the first to fourth delay units 21 to 24 to extract an average value and transmits the average value to the limit controller 30.

Reference numeral 41 is a 256 counter, 42 is a delay unit, 43 is an up / down control unit, and 44 is a DS1E distribution counter.

2 is a flowchart illustrating a clock recovery method in a conventional ATM receiver.

As shown therein, a step ST1 of calculating a difference value between the current address being written and read and a step ST2 of extracting an average value of the calculated four difference values; Steps ST3 and ST4 are performed to control the threshold value to the middle value of the extracted average value and to adjust the up / down of the output clock to the threshold value.

The operation of the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First of all, when designing an ATM receiver that receives a high speed ATM cell transmitted from the network and outputs it at 2.048Mbps for DS1E service, 64 Byte size cell buffers should be placed on the receiver side.

At this time, in order for the entire cell buffer to perform data input / output while maintaining an appropriate capacity, it is necessary to adjust the output speed according to the amount of input data written at a higher speed than the output.

For the smooth data flow of ATM cell buffers, it is most stable to design data to be input and output at the intermediate position of all cell buffers, and the output jitter is small.

In order to achieve this effect, a clock recovery method that adjusts the output data rate while dividing the reference clock and changing its duty cycle is used as the output clock.

To illustrate the prior art, it is assumed that the entire cell buffer has 16 single cell buffers having a size of 64 bytes.

1, WCELLAD [3: 0] is the address of the cell buffer currently being written, and RCELLAD [3: 0] is the address of the cell buffer currently being read.

By using the difference between the current address being written and the read address, the speed of the output clock to be read is controlled to prevent the buffer from being pulled.

At this time, the difference between the write and read addresses uses the average of the four difference values to reduce the error caused by the temporary difference.

In FIG. 1, the average value of the difference between the write and read addresses is calculated as a value of MSB (Most Significant Bit) [5: 0], and is determined based on the intermediate value by the threshold controller 30. It sends up / down (UP / DN) discrimination signal to increase or decrease speed or maintain current clock speed.

The signal exported to the UP / DN then affects the duty cycle adjustment in the block that divides the reference clock to produce a 2.048M clock, ultimately effectively managing the proper data storage in the buffer.

However, this conventional technology has the following problems.

In other words, even if the output clock value is continuously controlled rapidly at the time of excessively continuous ATM cell reception, a buffer pool may occur in the cell buffer when the I / O data rate is different. There is a problem that you need to put more buffers than necessary.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to efficiently manage the buffer by adjusting the read speed of the buffer so that the reception cell buffer maintains an appropriate amount of data in the ATM cell receiver. To provide a clock recovery apparatus and method in an ATM receiver that can minimize the output jitter.

Clock recovery apparatus in an ATM receiver according to an embodiment of the present invention to achieve the above object,

A difference value calculator for calculating a difference value between the write cell address and the read cell address; An average value extracting unit obtaining an average value of the difference values calculated by the difference value calculating unit, and obtaining an average value of an address at which a cell buffer is currently read and a currently reading data address; It is characterized in that the technical configuration is made to include a limit control unit for controlling the up and down of the output clock by controlling the threshold value to the median value of the average value output from the average value extraction unit.

Clock recovery method in an ATM receiver according to an embodiment of the present invention to achieve the above object,

A first step of obtaining an average value of the difference between the current address being read and read, and extracting an average value of the current read operation of the one cell buffer and the currently read data address; And a second step of controlling the limit value using the average value extracted in the first step to perform an up / down adjustment of the output clock with the limit value.

Hereinafter, an embodiment according to the present invention, a clock recovery apparatus of an ATM receiver, and a method thereof will be described with reference to the accompanying drawings.

3 is a block diagram of a clock recovery device and its neighboring block in an ATM receiver according to the present invention.

As shown therein, a difference value calculator 100 for calculating a difference value between a write cell address WCELLAD and a read cell address RCELLAD; The difference value calculated by the difference calculator 100 calculates an average value of the difference value, and reads the current row (Read row Column Address, RCAD) and the currently read data address (Read Row Address, RRAD) of one cell buffer. An average value extracting unit 200 for obtaining an average value with respect to; The threshold value control unit 300 is configured to control the threshold value to the middle value of the average value output from the average value extraction unit 200 to adjust the output clock up / down.

The average value extractor 200 includes: a first average value calculator 210 for obtaining an average value of the difference values calculated by the difference value calculator 100; And a second average value calculator 220 for obtaining an average value of the address RCAD where the current read operation of the one cell buffer is performed and the data address RADD currently being read.

The first average value calculator 210 includes: a plurality of delay units 211 to 214 for sequentially delaying the output of the difference value calculator 100; The first adder 215 extracts an average value by adding the outputs of the plurality of delay units 211 to 214 and transmits the average value to the limit controller 300.

The plurality of delay units 211 to 214 are configured as four of the first to fourth delay units 211 to 214.

The second average value calculator 220 receives a plurality of delay units 221 to sequentially receive an address RCAD on which a current cell read operation is performed and a data address RADD currently being read. 224); And a second adder 225 for extracting an average value by adding outputs of the plurality of delay units 221 to 224 and transmitting the average value to the limit controller 300.

The plurality of delay units 221 to 224 may be configured as four of the fifth to eighth delay units 221 to 224.

Reference numeral 410 denotes 256 counters, 420 denotes delay units, 430 denotes up / down controllers, and 440 denotes DS1E distribution counters.

4 is a flowchart illustrating a clock recovery method in an ATM receiver according to the present invention.

As shown in the figure, an average value is obtained for the difference between the current address being written and read, and the average value is obtained for the address RAD currently read to the one cell buffer and the RDRAD currently being read. First steps ST11 to ST13 to be extracted; A second step (ST14, ST15) is performed by controlling the threshold value using the average value extracted in the first step to perform the up / down adjustment of the output clock to the threshold value.

The first step may include: an eleventh step (ST11) of calculating a difference value between the current address being written and read; A twelfth step (ST12) of extracting an average value by adding the difference value a predetermined number of times (for example, four times) to the difference value calculated in the eleventh step; And a thirteenth step ST13 of extracting an average value of the address RCAD and the currently read data address RADD of the one cell buffer after the twelfth step and returning to the second step. Do it.

The operation of the clock recovery apparatus and the method in the ATM receiver according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the present invention is to minimize the output jitter and efficient management of the buffer by adjusting the read speed to the buffer so that the receiving cell buffer maintains an appropriate amount of data in the ATM cell receiver.

An ATM receiver stores an ATM cell that is received at high speed, and an ATM cell buffer that reads at a 2.048M clock is used in a device that receives an ATM cell and outputs DS1E (2.048Mbps) data. When the data stored in the buffer is full (buffer full state), the output jitter value increases and data loss occurs.

To prevent this, it is important to keep the cell buffer data volume at the median of the buffer's total capacity. In other words, if the amount of data transferred to the buffer increases, the read clock speed is increased to read data quickly. On the contrary, if the amount of data transferred to the buffer is small, the read clock speed is decreased to read data slowly. To go.

This fine read clock adjustment technique uses a clock recovery method that efficiently divides a reference clock to generate a read clock. In the present invention, the control of the frequency adjustment of the read clock is effectively performed when the clock recovery method is used. do.

Thus, the present invention adds the byte address check function to the operation of the prior art to enable more efficient output speed adjustment.

Accordingly, the difference calculator 100 receives the write cell address WCELLAD [3: 0] and the read cell address RCELLAD [3: 0], calculates the difference value, and calculates the difference value. The data is transmitted to the first delay unit 211 of the calculator 210.

In the mean value extractor 200, the first mean value calculator 210 calculates an average value of the difference values calculated by the difference value calculator 100.

The first delay unit 211 in the first average value calculation unit 210 delays the difference value calculated by the difference value calculation unit 100 to Q1 to the second delay unit 212 and the first adder 215. Send [3: 0].

In addition, the second delay unit 212 transmits Q2 [3: 0] to the third delay unit 213 and the first adder 215 by delaying the difference delayed by the first delay unit 211.

In addition, the third delay unit 213 delays the difference value delayed by the second delay unit 212 and transmits Q3 [3: 0] to the fourth delay unit 214 and the first adder 215.

In addition, the fourth delay unit 214 delays the difference value delayed by the third delay unit 213 and transmits Q4 [3: 0] to the first adder 215.

The first adder 215 adds Q1 [3: 0] to Q4 [3: 0] transmitted from the first to fourth delay units 211 to 214 by 6-bit adders, and adds the MSB [ 5: 0] outputs a signal to the threshold controller 300.

In this way, the first average value controller 210 receives the difference value calculated by the difference calculator 100 for four times and averages the output. The number of delays of the first average value controller 210 may be increased or decreased according to circumstances.

In addition, the second average value calculator 220 obtains an average value of the address RCAD where the current read operation of the cell buffer is currently performed and the data address RRAD currently being read, and transmits the average value to the threshold controller 300.

In the second average value calculating unit 220, the fifth delay unit 221 is RCAD [5: 0], which is an address at which a current cell read operation is being performed, and RRAD [2: 0], which is a data address currently being read. After receiving the delay, DT1 [8: 0] is transmitted to the sixth delay unit 222 and the second adder 225.

In addition, the sixth delay unit 222 delays the difference delayed by the fifth delay unit 221 and transmits DT2 [8: 0] to the seventh delay unit 223 and the second adder 225.

In addition, the seventh delay unit 223 delays the difference delayed by the sixth delay unit 222 and transmits DT3 [8: 0] to the eighth delay unit 224 and the second adder 225.

In addition, the eighth delay unit 224 delays the difference value delayed by the seventh delay unit 223 and transmits DT4 [8: 0] to the second adder 225.

The second adder 225 adds DT1 [8: 0] to DT4 [8: 0] transmitted from the fifth to eighth delay units 221 to 224 by the 11-bit adder, and adds the LSB ( Least Significant Bit) [10: 0] is output to the threshold controller 300.

In this way, the second average value controller 220 receives and outputs the address RCAD and the data address RRAD currently being read for one cell buffer for four times and averages them. The number of delays of the second average value controller 220 may be increased or decreased according to circumstances.

Therefore, the read byte address (RCAD [5: 0], RRAD [2: 0]) is continuously checked when an ATM cell written to one cell buffer of 64 bytes is read in 8-bit units according to the output clock.

The average value of the addresses checked four times in a row is exported to LSB [10: 0].

In addition, the limit value control unit 300 controls the limit value to be an intermediate value of the average value output from the average value extraction unit 200 so that the up / down of the output clock is adjusted. Thus, the threshold controller 300 adjusts the output clock value by determining whether an address on one cell buffer in which a read operation is being performed is located above a reference value or has a low address value.

At this time, the threshold value control unit 300 uses both the address check value of the cell unit used in the prior art and the address value of the byte unit added in the present invention to export the UP / DN control value.

That is, when there is a difference between the address of the write and the read checked in the cell unit, the difference value is applied as in the conventional art to adjust the duty cycle of the output clock, and when the cell unit maintains a stable state in bytes. Monitor the address location to determine the UP / DN control value.

The operation at this time is described in detail as follows.

First, when the decimal value of the MSB [5: 0] transmitted from the first average value calculating unit 210 is greater than 32, the up (UP) and the decimal value of the MSB [5: 0] is smaller than 32 If the decimal value of down (DN) and MSB [5: 0] is exactly 32, the present invention checks the current state of the byte address in one cell buffer by referring to the newly added value of LSB [10: 0]. .

That is, the cell address check checked in the multi-cell buffer is performed first, and if it is stable, the control of more stable data flow is performed by additionally checking the value of LSB [10: 0], which is made to be checked in one cell buffer in the second order. It is. If the decimal value of LSB [10: 0] is greater than 1536, it will be up; if the decimal value of LSB [10: 0] is less than 1536, down; Export control values.

As such, the present invention adjusts the read speed of the buffer so that the receiving cell buffer maintains an appropriate amount of data in the ATM cell receiver, thereby minimizing efficient management of the buffer and minimizing output jitter.

Although preferred embodiments of the present invention have been described above, the present invention may use various changes and modifications and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the clock recovery apparatus and method in the ATM receiver according to the present invention adjust the read speed of the buffer so that the reception cell buffer maintains an appropriate amount of data in the ATM cell receiver, thereby efficiently managing the buffer and output jitter. There is an effect that can be minimized.

In the conventional clock recovery scheme, the multi-cell buffer takes a long time until the adjustment value is applied by adjusting the output speed only by the write / read address check of the cell unit. That is, one cell is filled with data, and there is a disadvantage in that the threshold controller reacts by comparing the speed difference between the light units and the read units of the cell unit, and thus, the buffer pool phenomenon is relatively high.

Thus, in the present invention, the byte address of each cell buffer is checked at the same time to further monitor the current state of the entire buffer.

As a result, the current clock speed is maintained without control of the duty cycle adjustment when the write / lead address of each cell is stable. However, according to the present invention, it is stable before the write / lead speed difference of the cell unit occurs. In this case, the speed difference between the input and output in one cell can be adjusted in advance.                     

Therefore, the present invention has an effect that can prevent the buffer pool phenomenon in advance while having the same buffer size than the prior art.

Claims (8)

A difference value calculator for calculating a difference value between the write cell address and the read cell address; An average value extracting unit obtaining an average value of the difference values calculated by the difference value calculating unit, and obtaining an average value of an address at which a cell buffer is currently read and a currently reading data address; And a threshold controller configured to control a threshold value to an intermediate value of the average value output from the average value extractor so that up / down of the output clock is adjusted. The method of claim 1, wherein the average value extraction unit, A first average value calculator for obtaining an average value of the difference values calculated by the difference value calculator; And a second average value calculator for calculating an average value of the address at which a cell buffer is currently read and the currently read data address. The method of claim 2, wherein the first average value calculation unit, A plurality of delay units for sequentially delaying the output of the difference value calculator; And a first adder for extracting an average value by adding outputs of the plurality of delay units and transmitting the average value to the threshold controller. The method of claim 3, wherein the plurality of delay unit, A clock recovery apparatus for an ATM receiver, comprising four first to fourth delay units. The said 2nd average value calculation part of Claim 2 thru | or 4, A plurality of delay units configured to sequentially receive an address at which a current read operation of a cell buffer is performed and a data address currently being read; And a second adder for extracting an average value by adding outputs of the plurality of delay units and transmitting the average value to the threshold controller. The method of claim 5, wherein the plurality of delay unit, A clock recovery apparatus for an ATM receiver comprising four fifth to eighth delay units. A first step of obtaining an average value of the difference between the current address being read and read, and extracting an average value of the current read operation of the one cell buffer and the currently read data address; And a second step of controlling the threshold value using the average value extracted in the first step to perform an up / down adjustment of the output clock with the threshold value. The method of claim 7, wherein the first step, An eleventh step of calculating a difference value between the current address being written and read; A twelfth step of extracting an average value by adding a difference value a predetermined number of times with respect to the difference value calculated in the eleventh step; And a thirteenth step of extracting an average value for the address where the current read operation is performed on the one cell buffer and the currently read data address after the twelfth step, and returning the average value to the second step. Clock recovery method in.

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