KR100675132B1 - A device for changing the ATM Cell header - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication system, and in particular, replaces virtual resources of a field-programmable gate array The present invention relates to an AT cell header conversion apparatus capable of minimizing the use of CAM and reducing the cost by using a wealth.

According to the present invention, a virtual VPi replacement part and a virtual VPo replacement part are provided in the FPGA, so that the VP and the VC of the ATM cell data can be changed with a small number of CAMs because the virtual VPi replacement part is used. In addition, the present invention can minimize the use of the CAM by providing a virtual resource replacement in the FPGA used in the ATM network of the mobile communication system can reduce the cost of the board using the CAM.

Description

A device for changing the ATM cell header             

1 illustrates a configuration of an apparatus for converting a virtual path (VP) and a virtual channel (VC) in a header of ATM cell data in an ATM network of a conventional mobile communication system.

2 shows a detailed configuration diagram of FIG. 1,

3 is a detailed FPGA and CAM detailed diagram for CAM capacity optimization through virtual resource substitution of the present invention.

4 shows an example in which the VP and VC values of an ATM cell externally received from the FPGA set new values via CAM.

<Description of Major Symbols in Drawing>

20: CPU 22, 50: FPGA

24, 60: CAM 52: virtual VPi (path input) substitution

54: CAM access logic 56: virtual VPo (path output) replacement

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication system. In particular, a field-programmable gate array (FPGA) is provided for a CAM (Contents Access Memory) used for changing a virtual path and a virtual channel of ATM cell data used in an asynchronous transfer mode network. The present invention relates to an AT cell header conversion apparatus capable of minimizing use and reducing costs by using a virtual resource replacement unit.

In general, asynchronous transfer mode (ATM) is called asynchronous transfer method. In 1988, the ITU-T decided to use a broadband integrated information network (B-ISDN) as a transmission and exchange technology that is the core of B-ISDN. All information is divided into fixed length blocks called ATM cells and transmitted in sequence. The ATM cell has 53 bytes, of which the header is 5 bytes and the information field is 48 bytes. The header contains a virtual channel identifier (VCI) for identifying the connection to which the cell belongs, a virtual path identifier (VPI), a cell priority indicating whether the cell is allowed to be discarded during congestion, and a network control information for distinguishing the network control information. Functions include cell information identification (PT) and header error detection and control (HEC). The characteristic of ATM multiplexing is that the multiplexing efficiency higher than time division can be achieved by statistical multiplexing effect, and the transmission band allocated to individual communication can be freely set. The characteristic of ATM exchange is that since routine information is stored in a header, each ATM exchange can independently relay and exchange cells, and the exchange process can be realized by hardware (chip), thereby increasing the exchange speed. The ATM switching network consists of two levels of networks: virtual paths (VPs) and virtual channels (VCs). As described above, ATM is a technology capable of processing a variety of information at high speed by inheriting high transmission efficiency of packet switching and correcting a decrease in switching delay line usage efficiency, which is a disadvantage of circuit switching.

FIG. 1 illustrates a configuration of an apparatus for converting a virtual path (VP) and a virtual channel (VC) in a header of ATM cell data in an ATM network of a conventional mobile communication system. FIG. 2 is a detailed configuration diagram of FIG. It is shown.

1 is composed of a CPU 20, a field-programmable gate array (FPGA) 22, and a CAM 24, and the CPU 20 has 16 bits of data for control of writing and reading resources to and from the CAM 24. And control the CAM with an address of 3 bits, and the FPGA 22 receives ATM cell data received from the outside and accesses the CAM of the FPGA 22 to convert it into a conversion resource and output it back to the ATM cell. The CAM 24 receives ATM cell data from the FPGA 22 and converts and stores a virtual path (VP) and a virtual channel (VC) recorded in a header to change and provide a virtual path and a virtual channel of the ATM cell data. do.

The VP and VC are converted between the FPGA 22 and the CAM 24 using a match signal, a 32-bit signal, and a control signal.

The CAM access logic of the FPGA 22 accesses the CAM 24 and exchanges conversion resources. When the FPGA 22 transmits VP and VC information of ATM cell data, the CAM 24 transmits new information. VP and VC are set and transmitted back to the FPGA 22, and the FPGA 22 transmits ATM cell data to the changed VP and VC again.

Changing the VP and VC occurs when ATM cell data has to be changed to the path and channel to the destination during transmission.

2 shows a detailed configuration diagram of FIG. 1.

The conventional CAM 24 requires an additional CAM, such as CAM2, when the VP needs 10 or more conversion resources when using the CAM 24, which can store five conversion resources each. Therefore, there is a problem in that the cost increases because the number of CAMs required increases according to the capacity of the conversion resource.

When the ATM cell data is externally received from the FPGA 22, the CAM access logic unit accesses the CAM 24 with the VP and VC values of the received ATM cell, and the CAM 24 converts the newly set VP and VC values into output values. The controller 22 outputs the changed VP and VC values in the FPGA 22 to route the same.

Therefore, in the related art, one CAM 24 may process 1 to 5 VPs and 1 to 5 VCs. However, in the case of 10 VPs and 5 VCs, additional CAMs may be used as shown in FIG. Costly problem with using and storing increased translation resources

In order to solve the above problems, the present invention provides a virtual VPi replacement unit and a virtual VPo replacement unit in the FPGA, and when the VP is 5 or more, the virtual replacement is used, so that VP and VC of ATM cell data can be changed with a small number of CAMs. An object of the present invention is to provide an AT cell header conversion apparatus.

In order to achieve the above object, the AT cell header conversion apparatus of the present invention receives ATM cell data from outside and determines whether to virtually convert and virtualizes the exceeded virtual path value when the virtual path value of the CAM is exceeded. The FPGA converts the virtual path value from the ATM cell data output by converting the virtual channel value from the CAM and converts the virtual path value into the original virtual path value, and the virtual path of the ATM cell data from the FPGA. A CAM for receiving a value and a virtual channel value and changing and providing the virtual path value and the virtual channel value, and a CPU controlling the overall operation of converting the virtual path and the virtual channel of the ATM cell data of the CAM and the FPGA. .

The FPGA of the present invention includes a CAM access unit for accessing a CAM to transmit and receive the virtual path value and the virtual channel value, and a virtual path input exchanger for converting the virtual path value when the virtual path value is required to be converted. It includes a virtual path output replacer for providing a substitute for the actual virtual path value from the converted virtual path value received from the CAM.

The AM access unit of the present invention includes a virtual substitution register that informs the virtual path input substitution unit and the virtual path output substitution unit when the virtual path value of the received ATM cell data needs to be converted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a detailed FPGA and CAM detailed diagram for CAM capacity optimization through virtual resource substitution according to the present invention, and FIG. 4 is a VP, VC value of an ATM cell externally received by the FPGA 50, and CAM value. The following example shows how to set a new value via a.

3 of the present invention shows an FPGA detailed configuration and CAM detailed diagram for CAM capacity optimization through virtual resource substitution.

According to the present invention, the CPU 20 responsible for writing and reading resources to and from the CAM using 16 bits of data and 3 bits of address and ATM data received from the outside are input to the CAM 60 to convert VP and VC. FPGA 50, which functions to receive the output resources again and output them back to the external ATM output, and CAM 60 that stores the resources to be converted.

The FPGA 50 of the present invention is composed of a CAM access logic 54, a virtual VPi replacement unit 52, and a virtual VPo replacement unit 56.

The CAM access logic 54 extracts the VP and VC values from the header of the ATM cell from the outside and inputs them to the external CAM 60 to receive the converted resources and output them back to the ATM cell.

The virtual VPi substitution (virtual path input substitution) 52 stores the actual VPi value to virtually set the VP value when the VPi value of the ATM cell received by the CAM access logic 54 is more than five, Replace with a virtual VP value.

The virtual VPo substitution unit (virtual path output substitution unit) 56 is a virtual VP stored in the virtual Vpi substitution unit (virtual path input substitution unit) 52 to which the VP and VC are newly set, and the virtual VPi value from the CAM 60 is set. It consists of a virtual VPo substitution part (virtual path output substitution part) 56 which changes a value and outputs it to an ATM cell.

That is, the virtual Vpi substitution unit 52 stores the actual VP value and repeatedly designates a virtual VP value by repeating 1 to 5 when the VP exceeds 5, such that 6 is 1, 7 is 2, and 11 is 1 The VP value is virtually assigned and transmitted, and the VP value converted and received from the CAM 60 is converted into the actual VP value stored in the virtual VPi substitution part 52 in the virtual VPo substitution part 56, and the CAM access is performed. The logic unit 54 outputs it again.

Accordingly, the present invention can convert VP and VC of ATM cell data into a small number of CAMs 60 using the virtual Vpi replacement unit 52 and the virtual VPo replacement unit 56 of the FPGA 50.

The CAM access logic section 54 of the FPGA 50 is provided with a virtual substitution register, which is set when the number of VPs of the ATM cell received from the outside exceeds 5, and the virtual Vpi replacement unit 52 and the virtual VPo are required. The substitution unit 56 performs the virtual conversion only when the virtual substitution register is set with reference to the virtual substitution register, and does not perform the virtual conversion if it is not set.

If the types of resources to be converted from the external ATM cell are VP 1 to 10 and VC a to e, it can be seen that there are 10 types of VPs and 5 types of VCs.

If one CAM can change resources for five VCs and five VPs, two CAMs have been conventionally used for ten VPs and five VCs.

However, the present invention performs the function as one CAM 60 storing five resources in a state where VP 10 resources are needed as shown in FIG. 3.

First, the CPU 20 controls the VP 10 resources to be stored in the CAM like the resources stored in the CAM 60 of FIG. 3.

    In other words, VC is set to 5 with a to e and VP is set to 5 with 1 to 5. Therefore, only VC a to e and VP store only 1 to 5 in the actual CAM 60.

The remaining five VCs from VP 6 to 10 should be set to the same value.

According to the present invention, when the VP of the input ATM cell data is 10 and the VC is 5, the VP stores the actual VP value in the virtual VPi replacement unit 52 from 6, and the CAM 60 in the CAM access logic unit 54. In this case, VP is virtually substituted for VP in the same manner as 6 is 1, 7 is 2, 8 is 3, 9 is 4, 10 is 5, and VC is left unchanged. Send to 60.

The CAM 60 extracts the VP and VC from the ATM cell data received by the CAM access logic unit 54, sets it as a new VP and VC, and transmits the converted value to the CAM access logic unit 54 again. 50, the virtual Vpo exchanger 56 replaces the actual VP value and the received VP value stored in the virtual VPi replacer 52, and the CAM access logic unit 54 again converts the new path VP and the ATM cell data. The channel (VC) value is recorded in the header and output.

Therefore, in the present invention, the CAM 60 can be used with CAMs according to the number of VCs, thereby saving expensive CAMs, thereby reducing costs.

4 shows an example in which the VP and VC values of an ATM cell externally received by the FPGA 50 set new values via CAM.

 As a), if the VP of the ATM cell coming from outside 1 to 5 can be handled as it is, the operation of the virtual VPi, VPo replacement unit 52, 56 is not necessary, only the CAM access logic unit 54 In operation, the VP and VC values input to the CAM 60 are 1, a, the output of the CAM is 1, 1, and the VP and VC output to the ATM cell are 1,1.

B) In case that the VP of ATM cell received from the FPGA 50 from the outside enters 6 to 10, the CAM access logic unit 54 has a VP value of 6 or more, so the VP value is transferred to the virtual Vpi replacement unit 52. send.

The virtual VPi switching unit 52 stores the actual VP = 6 value received from the CAM access logic unit 54 and transfers the virtual VP = 1 value corresponding to the value to the CAM access logic unit 54.

The CAM access logic unit 54 accesses the CAM 60 with a value of virtual VP = 1, and VC accesses the CAM 60, and receives the VP and VC values converted and output from the CAM 60 again. The value 1 is returned by the virtual VPo substitution unit 56 as the actual VP = 6 value, and is converted to 6 and 1 for transmission to the ATM cell.

If the VP value is 6 or more and the virtual conversion is required, the virtual substitution register of the CAM access logic unit 54 is set. If the VP value is 6 or less, the virtual substitution register is not set, and the virtual VPi replacement unit 52 and the virtual VPo are set. The substitution unit 56 performs virtual conversion with reference to the setting of the virtual substitution register.

The virtual VPi substitution unit 52 and the virtual VPo substitution unit 56 operate only when the virtual substitution register is set, and when the virtual VPi substitution unit 52 is not set, virtual conversion is not necessary.

In this case, since VP is 7, VC is b, virtual conversion is required, and the virtual substitution register of the CAM access logic section 54 of the FPGA 50 is set, and the virtual VPi replacement section 52 sets the VP to two. Virtual conversion to 2, b from CAM access logic section 54 to CAM 60, and CAM 60 converts 2, b to 2, 2 and send back to CAM access logic section 54, virtual The VPo replacement unit 56 converts the VP and the VC to the CAM access logic unit 54 of the FPGA 50 by converting the pre-stored actual VP 7, 7 into an external terminal.

As described above, the present invention has an effect of minimizing the use of the CAM and reducing the cost of the board using the CAM by providing a virtual resource replacement unit in the FPGA used in the ATM network of the mobile communication system.

Claims (3)

When ATM data is received from outside and it is determined whether or not to convert the virtual path, if it exceeds the CAM processable virtual path value, the virtual path value is virtually converted and transmitted to the CAM, and the virtual channel value is converted and output from the CAM. An FPGA for converting the virtual path value virtually converted from the cell data into an original virtual path value and outputting the original virtual path value ; A CAM for receiving the virtual path value and the virtual channel value of the ATM cell data from the FPGA and changing and providing the virtual path value and the virtual channel value; Atm cell header conversion apparatus comprising a CPU for controlling the overall operation of the virtual path and the virtual channel of the ATM cell data of the CAM and the FPGA. The method of claim 1, The FPGA, A CAM access unit which accesses the CAM and transmits and receives the virtual path value and the virtual channel value; A virtual path input exchanger for converting the virtual path value and providing the virtual path value when a virtual conversion of the virtual path value is required; And a virtual path output replacer which replaces the converted virtual path value received from the CAM with an actual virtual path value. The method of claim 2, The CAM access unit includes a virtual substitution register for informing the virtual path input replacement unit and the virtual path output replacement unit when the virtual path value of the received ATM cell data needs to be converted. Device.

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