KR100590097B1 - Driving Method of Plasma Display Panel and Plasma Display Device - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel. In the driving method of the plasma display panel, a sustain discharge pulse having a voltage of Vs and a voltage of -Vs is alternately applied to the scan electrodes while a voltage of 0 V is applied to the sustain electrodes in the sustain period. The address electrode is then floated in the sustain period. At this time, a power supply for supplying a voltage applied to the address electrode of the discharge cell to be turned on in the address period and a first switch for blocking the address electrode, and a power supply for supplying a voltage to the address electrode of the discharge cell not to be turned on in the address period And a second switch to block the address electrode electrode, thereby floating the address electrode with the first switch turned off while the Vs voltage is applied to the scan electrode in the sustain period, and the -Vs voltage to the scan electrode in the sustain period. The address electrode is floated while the second switch is turned off while it is being applied.

PDP, scan electrode, sustain electrode, drive board, floating, switching element

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a typical AC plasma display panel.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

3 is a schematic concept of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

Fig. 6 is a diagram showing the wall charge state of cells not selected in the address period.

7 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

8 is a diagram illustrating a general address selection circuit.

FIG. 9 is a diagram illustrating an address selection circuit according to a first embodiment of the present invention for generating an address driving waveform in the sustain period shown in FIG. 7.

10 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

FIG. 11 is a diagram illustrating an address selection circuit according to a second embodiment of the present invention for generating an address driving waveform in the sustain period shown in FIG. 10.

12 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention.

The present invention relates to a method for driving a plasma display panel (PDP).

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

In the AC plasma display panel, scan electrodes and sustain electrodes that are parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a partial perspective view of a typical AC plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 13 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell. The address period is a wall charge in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display panel having an integrated board capable of driving a scanning electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

In order to solve this problem, the present invention grounds the sustain electrode and applies a driving waveform to the scan electrode.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. The driving method includes, in at least one subfield, a third of the discharge cells to be turned on through a plurality of first transistors respectively connected between the plurality of third electrodes and a first power supply for supplying a fourth voltage in an address period. The discharge cell of the discharge cell that is not to be turned on by applying the fourth voltage to the electrode and being connected between the plurality of third electrodes and the second power supply respectively supplying a fifth voltage lower than the fourth voltage. Applying the fifth voltage to a third electrode, and in the sustaining period, the second voltage higher than the first voltage and the second voltage to the plurality of second electrodes in a state in which the plurality of first electrodes are biased to the first voltage; Alternately applying a third voltage lower than the first voltage, wherein the first switch is connected between the second power supply and the plurality of second transistors in the sustain period. In the off state during at least a second electrode of the plurality applied with the third voltage and floating the plurality of third electrodes.

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According to another feature of the present invention, a plasma display device is provided. The plasma display device includes a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes, and a first voltage. A plurality of first transistors connected between the first power supply and the plurality of third electrodes, respectively, and a second power supply for supplying a second voltage lower than the first voltage and the plurality of third electrodes, respectively. And a second transistor, wherein the first voltage is applied to a third electrode of a discharge cell to be turned on through the plurality of first transistors in an address period and is not turned on through the plurality of second transistors. A plurality of selection circuits for selectively applying the second voltage to three electrodes, and in the sustain period, the plurality of second electrodes in a state in which a third voltage is applied to the plurality of first electrodes. The fourth voltage higher than the third voltage and the fifth voltage lower than the third voltage are alternately applied to the pole, and the plurality of third electrodes are applied while the fifth voltage is applied to at least the plurality of second electrodes. A floating driving circuit and a first switch connected between the second transistor of the plurality of selection circuits and the second power source and turned off while the third electrodes are floating.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 3 is a schematic concept of a plasma display panel according to an exemplary embodiment of the present invention. 4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 2, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40.

The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10.

The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

3, the plasma display panel 10 includes a plurality of address electrodes A1-Am extending in the vertical direction, a plurality of scan electrodes Y1-Yn and a plurality of sustain electrodes X1 extending in the horizontal direction. -Xn).

The sustain electrodes X1-Xn are formed corresponding to the scan electrodes Y1-Yn, and generally have one end connected in common with each other.

The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X 1 -X n and Y 1 -Y n are arranged, and an insulating substrate on which address electrodes A 1 -A m are arranged.

The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1-Yn and the address electrodes A1-Am and the sustain electrodes X1-Xn and the address electrodes A1-Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1-Am and the sustain and scan electrodes X1-Xn and Y1-Yn forms the discharge cells 12.

As shown in FIG. 4, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20.

The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 4, a plasma display apparatus for dual driving is described as an example. However, in the case of a single driving, the address buffer board 100 is disposed at one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage to each address electrode A1-Am to select a discharge cell to be displayed.

The scan drive board 200 is disposed on the left side of the chassis base 20, and the scan drive board 200 is electrically connected to the scan electrodes Y1-Yn through the scan buffer board 300 and is processed. The driving signal is received from the control board 400 and a driving voltage is applied to the scan electrodes Y1-Yn. The sustain electrodes X1-Xn are biased at a constant voltage.

The scan buffer board 300 applies a voltage to the scan electrodes Y1-Yn to sequentially select the scan electrodes Y1-Yn in the address period.

In FIG. 4, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1-Am and a control signal for driving the scan electrodes Y1-Yn, respectively. ) And the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first exemplary embodiment of the present invention will be described with reference to FIG. 5.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased with a reference voltage (0 V in FIG. 5), the description of the voltage applied to the X electrode is omitted.

Referring to FIG. 5, one subfield is divided into a reset period (P _r), an address period (P _a), and a sustain period, comprising the (P _s) the reset period (P _r) is the rising period (P _r1) and the falling period (P _r2 ).

The rising period P _r1 of the reset period P _r is a period in which wall charges are formed on the Y electrode, the X electrode and the A electrode, and the falling period P _r2 is a part of the wall charges formed in the rising period P _r1 . This is a period for erasing to facilitate address discharge. An address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in the sustain period (P _s) from a plurality of discharge cells. Sustain period (P _s) is a period during which sustain discharge for a discharge cell selected in the address period (P _a).

The plasma display panel is connected to a scan / hold driving circuit for applying a driving voltage to the Y electrode and the X electrode in each period P _r , P _a , and P _s , and an address driving circuit for applying the driving voltage to the A electrode. It forms one display device.

In the rising period (P _r1) of the reset period (P _r) and a voltage gently increasing toward voltage Vset from the voltage V _s while maintaining the A electrode and X electrode at the reference voltage is applied to the Y electrode. In FIG. 5, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 5, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally the same voltage as that applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period P _r2 , Vnf at the voltage Vs while maintaining the A electrode at the reference voltage. A voltage slowly falling down to the voltage is applied to the Y electrode. Then, while the voltage of the Y electrode decreases, a weak discharge occurs between the Y electrode and the X electrode, and between the Y electrode and the A electrode, and the negative wall charges formed on the Y electrode and the positive wall charges formed on the X electrode and the A electrode. Is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the Y electrode (Y1 in FIG. 3) of the first row, and an address pulse of Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode (Y2 in FIG. 3) of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode in the second row, thereby forming wall charges in the cell. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be explained. When the Vnf voltage is applied in the reset period, the wall voltage between the A and Y electrodes is applied. The sum of the external voltage Vnf between the A electrode and the Y electrode is determined by the discharge start voltage Vfay between the A electrode and the Y electrode. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, the address period (P _a) in the cell where the address discharge is generated in a pulse having the Vs voltage first to the Y electrodes been formed in the high voltage Y wall voltage (Vwxy) of the electrodes, in the sustain period of the X electrode and Y A sustain discharge is caused between the electrode and the X electrode. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse having the Vs voltage and the -Vs voltage alternately to the Y electrode is repeated the number of times corresponding to the weight indicated by the corresponding subfield.

As described above, in the first exemplary embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

Referring to FIG. 5, in the first embodiment of the present invention, voltages Vs and −Vs for sustain discharge are alternately applied only to the Y electrode during the sustain period P _s , and the voltage of the X electrode is maintained at the reference voltage. do. However, in this case, the voltage to the Y electrode in the sustain period (P _s) because it is in the non-selected cells on as long as they have the same conditions in all the discharge cells during the address period (P _a) substantially the wall voltage between the X electrode and the Y electrode 0V ( Even when Vs and -Vs) are applied, no discharge occurs between the Y electrode and the X electrode of the discharge cell which are not selected.

On the other hand, in the falling period P _r2 of the reset period P _r , the voltage of the Y electrode drops to the Vnf voltage, where the magnitude of the Vnf voltage is similar to the discharge start voltage Vfxy between the Y electrode and the X electrode. . However, in general, since the Vfxy voltage is greater than the Vfay voltage, when the voltage of the Y electrode decreases to the Vnf voltage, a positive wall charge is formed on the A electrode and a negative wall charge is formed on the Y electrode as shown in FIG. do. In this state, if the -Vs voltage is applied to the Y electrode and the reference voltage is applied to the A electrode in the sustain period, erroneous discharge may occur in the unaddressed cells in the address period due to the wall voltage between the A and Y electrodes.

An embodiment capable of preventing such a discharging will be described in detail with reference to FIG. 7. 7 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

As shown in FIG. 7, the driving waveform according to the second exemplary embodiment of the present invention is the first waveform of the present invention except for floating the A electrode when the -Vs voltage is applied to the Y electrode during the sustain period P _s . Same as the embodiment.

Specifically, in the sustain period P _s , a sustain discharge pulse having a voltage of Vs and a voltage of -Vs is alternately applied to the Y electrode, and the A electrode is floated when the voltage of -Vs is applied to the Y electrode. Since the capacitance component is formed by the A electrode and the Y electrode, when the A electrode is floated when the voltage of the Y electrode decreases, the voltage of the A electrode also decreases along with the voltage of the Y electrode. Therefore, when the -Vs voltage is applied to the Y electrode, the voltage between the A electrode and the Y electrode is smaller than in the first embodiment, so that the misdischarge between the Y electrode and the A electrode of the cell that is not selected in the address period Pa _a Can be prevented.

8 shows a general address IC.

As shown in Fig. 8, a general address IC includes a plurality of address selection circuits. Specifically, the address selection circuit is connected to the plurality of A electrodes, respectively, and includes two transistors A _H and A _L. The transistors A _H and A _L are field effect transistors having a body diode. A capacitance component (hereinafter referred to as panel capacitor Cp) is formed by the A electrode and the Y electrode. The scan electrode driver is connected to the Y electrode of the panel cache sheeter Cp.

The transistor A _H is connected between the power supply Va supplying the Va voltage and the A electrode, and the transistor A _H is turned on to supply the Va voltage to the A electrode. The transistor A _L is connected between the power supply GND supplying the ground voltage and the A electrode, and the transistor A _L is turned on to supply the ground voltage to the A electrode. That is, in the address period _Pa , the transistor A _H is turned on to select the A electrode to which the Va voltage is applied, and the switching element A _L is turned on to select the A electrode to which the ground voltage is applied.

However, since the address selection circuit shown in FIG. 8 has a body diode, when the A electrode is floated when the -Vs voltage is applied to the Y electrode during the sustain period P _s as shown in FIG. 7, the voltage of the A electrode is increased. When the voltage decreases along the voltage and becomes lower than the ground voltage, the voltage of the A electrode is clamped to the ground voltage through the body diode of the switching element A _L of the address selection circuit. Therefore, the voltage of the A electrode cannot fall below the ground voltage. In this case, since the driving waveform of FIG. 6 is the same, the effect of floating the A electrode does not appear. An embodiment for solving this problem will be described in detail with reference to FIG. 9.

FIG. 9 is a diagram illustrating an address IC according to a first embodiment of the present invention for generating an address driving waveform in the sustain period shown in FIG. 7.

As shown in FIG. 9, the switch IC is the same as the address IC of FIG. 8 except that the switch SW1 is connected between the power supply 0V and the transistor A _L.

Specifically, in the address IC according to the first embodiment of the present invention, the switching element SW1 is electrically connected between the transistors A _L of the plurality of address selection circuits and the power supply 0V. The switch SW1 is turned off when the A electrode floats when the -Vs voltage is applied to the Y electrode in the sustain period P _s to cut off the A electrode from the power supply (0 V) so that the voltage of the A electrode follows the voltage of the Y electrode. It can also be reduced to negative voltages. As a result, the voltage difference between the Y electrode and the A electrode is reduced to prevent erroneous discharge in a cell not selected in the address period.

In addition, since the driving waveform according to the second embodiment of the present invention floats the A electrode when the -Vs voltage is applied to the Y electrode, the switch SW1 repeatedly turns off or turns on, thereby increasing power consumption. In addition, when the Vs voltage is applied to the Y electrode and discharge occurs, electrons move toward the Y electrode and cations move toward the A electrode. At this time, the A electrode is covered with a phosphor for color expression, and this cation continues to collide with the phosphor surface, thereby shortening the lifetime of the phosphor. Therefore, below, an embodiment which can prevent such a problem will be described in detail with reference to FIG. 10.

10 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention. As shown in FIG. 10, the same as in FIG. 7 except that the A electrode is floated even when the Vs voltage is applied to the Y electrode in the sustain period.

Specifically, during the sustain period, the A electrode is floated, and a sustain discharge pulse having an alternating voltage of Vs and -Vs is applied to the Y electrode. That is, when the A electrode is floated when the Vs voltage is applied to the Y electrode, the voltage of the A electrode increases along with the voltage of the Y electrode. Therefore, the A electrode becomes high so that a large amount of cations move toward the X electrode after the sustain discharge, thereby protecting the phosphor covering the A electrode.

However, when the A electrode is floated when the Vs voltage is applied to the Y electrode, when the general address IC shown in FIG. 8 is used, the voltage of the A electrode is clamped to the Va voltage, and the voltage of the A electrode is increased above the Va voltage. You will not be able to. Therefore, in order to supply a voltage higher than Va voltage to the A electrode, the power supply Va and the A electrode should be cut off when the A electrode is floated. This embodiment will be described in detail with reference to FIG. 11.

FIG. 11 is a diagram illustrating an address IC according to a second embodiment of the present invention for generating an address driving waveform in the sustain period shown in FIG. 10.

As shown in FIG. 11, the switch IC is the same as the address IC of FIG. 9 except that the switch SW2 is connected between the power supply Va and the transistor A _H of the address selection circuit.

Specifically, the address IC according to the second embodiment of the present invention is a switch between the transistor A _H and the power supply Va of the address selection circuit and between the transistor A _L and the power supply 0V of the address selection circuit, respectively. SW2, SW1) are electrically connected.

In the sustain period, the switch SW2 is turned off when the A electrode is floating while the Vs voltage is applied to the Y electrode, and the switch SW1 is turned off when the A electrode is floating while the -Vs voltage is applied to the Y electrode. When the Vs voltage is applied, the voltage of the A electrode is increased to a positive voltage, and when the -Vs voltage is applied to the Y electrode, the voltage of the A electrode is reduced to a negative voltage. That is, when the switches SW1 and SW2 are turned off in the sustain period, the A electrode is cut off from the power sources 0V and Va, respectively, so that when the voltage Vs is applied to the Y electrode, a voltage higher than the Va voltage may be applied and Y When the voltage -Vs is applied to the electrode, a voltage lower than 0V may be applied.

As described above, according to the exemplary embodiment of the present invention, the driving waveform is applied only to the Y electrode while the X electrode is biased to a predetermined voltage, thereby performing the reset operation, the address operation, and the sustain discharge operation. You can remove the board. In addition, since the pulse for sustain discharge is supplied only from the scan driving board 300, the impedance in the path to which the sustain discharge pulse is applied may be constant.

Although the reset period of the plurality of subfields forming one frame may be formed in both the rising period P _r1 and the falling period P _r2 , as in the first and second embodiments of the present invention, some of the subfields are reset. The period may be formed only by the falling period P _r2 . Hereinafter, such an embodiment will be described in detail with reference to FIG. 12.

12 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention. In FIG. 12, two subfields are shown for convenience, and the two subfields are shown as a first subfield and a second subfield, respectively. The second subfield only shows the reset period.

Referring to FIG. 12, the reset period P _r of the first subfield among the plurality of subfields forming one frame includes the rising period P _r1 and Y for gradually increasing the voltage of the Y electrode from the voltage Vs to the voltage Vset. It is formed with a falling period (P _r2 ) that gradually lowers the voltage of the electrode from the voltage Vs to the voltage Vnf, and the reset period P _r of the second subfield gradually changes the voltage of the Y electrode from the voltage Vs to the voltage Vnf. It is formed only in the fall period P _r2 which makes it descend. That is, the first is the falling waveform, after the rising waveform applied to the reset period (P _r) of the sub-field is applied and the second is applied in only the reset falling waveform period (P _r) of the sub-field. At this time, when sustain discharge occurs in the sustain period of the first subfield, since negative (−) wall charges are formed on the Y electrode and positive (+) wall charges are formed on the X electrode and the A electrode, the voltage of the Y electrode gradually decreases. When the discharge start voltage is exceeded together with the wall voltage formed in the cell, weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the Y electrode is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield ends in the falling period of the first subfield. It becomes substantially the same as the later wall charge state.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, discharge does not occur when the voltage of the Y electrode decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge. Therefore, if the first subfield is formed like the first subfield in one field and the other subfield is formed like the second subfield, when the zero gray scale (black gray scale) is displayed, the reset discharge (weak discharge) only in the reset period of the first subfield. This will happen. That is, since no discharge occurs in other subfields when displaying the black gradation, the contrast ratio can be increased.

As described above, when the discharge start voltage is exceeded along with the wall voltage formed in the cell while the voltage of the Y electrode is gradually decreasing, a weak discharge occurs, and since the discharge start voltage is not exceeded at the beginning of the reset period P _r2 , It is also possible to lower the voltage of the electrode immediately and then gradually lower it to the Vnf voltage. In this way, there is an effect that the reset period P _r of the first and second subfields can be shortened.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan drive board, the impedance is always constant.

According to the present invention, the address electrode is floated in the sustain period, and a switch is added between each power supply and the address IC which supplies the address voltage and the viadress voltage applied to the address electrode in the address period, thereby floating the address electrode in the sustain period. It is possible to increase or decrease the voltage above the address voltage or below the ground voltage to prevent erroneous discharge during the sustain period.

Claims (14)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In at least one subfield, The fourth voltage is applied to a third electrode of a discharge cell to be turned on through a plurality of first transistors respectively connected between the plurality of third electrodes and a first power supply for supplying a fourth voltage in an address period. Applying the fifth voltage to a third electrode of a discharge cell that will not be turned on through a plurality of second transistors that are respectively connected between a third electrode of the second power supply and a second power supply for supplying a fifth voltage lower than the fourth voltage. , And Alternately applying a second voltage higher than the first voltage and a third voltage lower than the first voltage to the plurality of second electrodes while the plurality of first electrodes are biased to the first voltage in the sustain period; Including; The plurality of first transistors and the plurality of second transistors are transistors having a body diode, The plurality of thirds while the third voltage is applied to at least the plurality of second electrodes in a state in which a first switch connected between the second power supply and the plurality of second transistors is turned off in the sustain period; A method of driving a plasma display panel that floats electrodes. delete The method of claim 1, And driving the plurality of third electrodes during the sustain period. The method of claim 3, The third electrode while the second voltage is applied to at least the plurality of second electrodes in a state in which the second switch connected between the first power supply and the plurality of first transistors is turned off in the sustain period. A method of driving a plasma display panel which floats. The method according to any one of claims 1, 3 and 4, And the first electrode is biased to the first voltage in a reset period and an address period. The method of claim 5, And the first voltage is a ground voltage. The method of claim 6, And the fifth voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode; A plurality of first transistors connected between a first power supply for supplying a first voltage and the plurality of third electrodes, and a second power supply for supplying a second voltage lower than the first voltage and the plurality of third electrodes, respectively. And a plurality of second transistors connected between the plurality of second transistors, wherein the first voltage is applied to a third electrode of a discharge cell to be turned on through the plurality of first transistors in an address period, and is turned on through the plurality of second transistors. A plurality of selection circuits for selectively applying the second voltage to a third electrode of a discharge cell, In the sustain period, a fourth voltage higher than the third voltage and a fifth voltage lower than the third voltage are alternately applied to the plurality of second electrodes while a third voltage is applied to the plurality of first electrodes. A driving circuit floating the plurality of third electrodes while the fifth voltage is applied to at least the plurality of second electrodes, and A first switch coupled between the second transistor of the plurality of select circuits and the second power source and turned off while the plurality of third electrodes are floating Including; And the plurality of first transistors and the plurality of second transistors are transistors having a body diode. delete The method of claim 8, A second switch connected between the first transistor and the first power source of the plurality of selection circuits More, The driving circuit may float the plurality of third electrodes during the sustain period, and the second switch is turned off while the fourth voltage is applied to at least the plurality of second electrodes in the sustain period. . The method of claim 8 or 10, And the first electrode is biased to the third voltage in a reset period and the address period. The method of claim 11, And the third voltage is a ground voltage. delete delete

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