KR100578850B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

In the plasma display device, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed. In the reset period of the second subfield among the plurality of subfields, the voltage of the scan electrode is gradually decreased while the sustain electrode is biased to the ground voltage, thereby initializing the discharge cells in which the sustain discharge has occurred in the previous subfield. At this time, the voltage reduction start voltage of the scan electrode is set to the ground voltage or less. This makes it possible to prevent strong discharge in the reset period and to shorten the reset period. In the first subfield of the plurality of subfields, the voltage of the scan electrode is gradually increased while the sustain electrode is biased to the ground voltage, and then the voltage of the scan electrode is gradually decreased to initialize all the discharge cells. At this time, in the reset period of the first subfield, the voltage of the address electrode is set to a positive voltage state in a period which is at least a part of the period in which the voltage of the scan electrode gradually increases.

PDP, integrated board, voltage difference, impedance, scan electrode, sustain electrode, reset, drop

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a plasma display panel.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

3 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

6 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a wall charge state of a cell after the end of the sustain period of the first subfield of FIG. 6.

8 is a diagram showing a wall charge state of a cell when a strong discharge occurs in the reset period.

9 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

The present invention relates to a method of driving a plasma display panel and a plasma display device.

A plasma display panel is a display panel that displays characters or images by using plasma generated by gas discharge, and tens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of a plasma display panel. As shown in FIG. 1, the plasma display panel includes two insulating substrates 1 and 2 facing each other apart from each other. A plurality of scan electrodes 3a and sustain electrodes 3b are formed in pairs and parallel on the insulating substrate 1, and the scan electrodes 3a and the sustain electrodes 3b are formed of a dielectric layer 4 and a protective film 5. Covered with). A plurality of address electrodes 6 are formed on the glass substrate 2, and the address electrodes 6 are covered with the insulating layer 7. The partition 8 is formed on the insulating layer 7 between the two address electrodes 6. In addition, the phosphor 9 is formed on the surface of the insulating layer 7 and on both sides of the partition 8. The insulating substrates 1 and 2 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 3a, the address electrode 6, the sustain electrode 3b, and the address electrode 6 are orthogonal to each other. The discharge space at the intersection of the address electrode 6 and the pair of scan electrode 3a and sustain electrode 3b forms a discharge cell (hereinafter referred to as a "cell") 12.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, if there is a separate driving board, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

In order to solve this problem, the present invention applies a drive waveform to the scan electrode while the sustain electrode is biased at a constant voltage.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. In this driving method, the voltage of the second electrode is changed to a second voltage which is less than or equal to the ground voltage in the reset period of the second subfield among the plurality of subfields while the voltage of the first electrode is biased to the first voltage. And gradually reducing a voltage of the second electrode from the second voltage to a third voltage in the reset period of the second subfield, and in the reset period of the first subfield of the plurality of subfields. Gradually increasing the voltage of the second electrode from the fourth voltage to the fifth voltage, and gradually decreasing the voltage of the second electrode from the sixth voltage to the seventh voltage in the reset period of the first subfield. And a voltage of the third electrode in a positive voltage state in a period which is at least a part of a period in which the voltage of the second electrode increases to the fifth voltage.

delete

In this driving method, the first electrode may be biased to the first voltage in an address period and a sustain period, and the first voltage may be a ground voltage.

According to another aspect of the present invention, there is provided a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A control unit for dividing the frame into a plurality of subfields, and a driving waveform for displaying an image by the plasma display panel to the second electrode and the third electrode, and the first electrode while the image is displayed. The present invention provides a plasma display device including a driving board for biasing a voltage to a first voltage and including a chassis base facing the plasma display panel. At this time, the driving board, in the reset period of the second subfield of the plurality of subfields, gradually reduces the voltage of the second electrode from the second voltage to the third voltage which is less than the ground voltage, the plurality of subfields In the reset period of the first subfield, the voltage of the second electrode is gradually increased from the fourth voltage to the fifth voltage during the first period, and the voltage of the second electrode is increased from the sixth voltage during the second period. The voltage is gradually decreased to seven voltages, and a positive voltage is applied to the third electrode in at least a part of the first period.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 3 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 2, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 3, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and an insulating substrate on which address electrodes A1 to Am are arranged. The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a cell (12 in FIG. 1).

As shown in FIG. 4, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 4, a plasma display apparatus for dual driving is described as an example. However, in the case of a single driving, the address buffer board 100 is disposed at one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 4, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first embodiment of the present invention will be described with reference to FIG. 5.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (the ground voltage in FIG. 5), the description of the voltage applied to the X electrode is omitted.

In addition, in FIG. 5, only two subfields of the plurality of subfields are illustrated, and for convenience, the two subfields are illustrated as first and second subfields, respectively. The reset period of the first subfield is shown as consisting of a rising period and a falling period, and the reset period of the second subfield is shown as being a falling period. That is, in the reset period of the first subfield, all discharge cells are initialized. In the reset period of the second subfield, initialization is performed for the discharge cells in which sustain discharge has occurred in the first subfield.

Referring to FIG. 5, the first subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while the A electrode is maintained at the reference voltage (0 V in FIG. 5). In FIG. 5, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 5, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage higher than the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is maintained at the reference voltage. Then, while the voltage of the Y electrode decreases, a slight discharge occurs between the Y electrode and the X electrode, and between the Y electrode and the A electrode, and the negative wall charges formed on the Y electrode and the (+) formed on the X electrode and the A electrode The wall charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the Y electrode (Y1 in FIG. 3) of the first row, and an address pulse of Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode (Y2 in FIG. 3) of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, in the cell where the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. In the sustain period, the Y electrode and the X electrode were first applied with a pulse having a Vs voltage to the Y electrode. It causes maintenance discharge between them. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode.

As described above, the reset period of the second subfield is formed only in the falling period, and in the reset period of the second subfield, the sustain discharge pulse of the voltage Vs is applied to the Y electrode in the sustain period of the first subfield. The voltage at the electrode is gradually reduced to the voltage Vnf.

At this time, when sustain discharge occurs in the sustain period of the first subfield, since negative (−) wall charges are formed on the Y electrode and positive (+) wall charges are formed on the X electrode and the A electrode, the voltage of the Y electrode gradually decreases. When the discharge start voltage is exceeded together with the wall voltage formed in the cell, weak discharge occurs as in the falling period of the reset period of the first subfield. And since the final voltage Vnf of the Y electrode is equal to the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield ends is the falling period of the first subfield. It becomes substantially the same as the wall charge state after termination.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, discharge does not occur when the voltage of the Y electrode decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge. Therefore, if the first subfield is formed like the first subfield in one field and the other subfield is formed like the second subfield, when the zero gray scale (black gray scale) is displayed, the reset discharge (weak discharge) only in the reset period of the first subfield. This will happen. That is, since no discharge occurs in other subfields when displaying the black gradation, the contrast ratio can be increased.

Since the driving waveform after the reset period of the second subfield is the same as that of the first subfield, description of overlapping portions is omitted. However, the process of applying the sustain discharge pulse of the voltage Vs and the voltage -Vs to the Y electrode in the sustain period is repeated a number of times corresponding to the weight indicated by the corresponding subfield.

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

In general, the weaker the discharge occurs in the cell, the slower the slope of the electrode's voltage gradually changes with time. However, in the falling period of the second subfield, the final voltage applied to the Y electrode is set to the Vnf voltage, and as described above, the final voltage Vnf is a voltage near the discharge start voltage between the Y electrode and the X electrode, and thus the given falling voltage is given. In the period, the descending slope is formed rapidly. As such, when the slope is steep, a strong discharge may occur in the falling period. Therefore, a method of causing weak discharge in the reset period by adjusting the slope at which the voltage of the Y electrode decreases in the reset period of the second subfield will be described in detail with reference to FIGS. 6 and 7.

6 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention, and FIG. 7 is a diagram illustrating a wall charge state of a cell after a sustain period is finished.

As shown in FIG. 6, it is the same as the first embodiment of FIG. 5 except that the starting point of the falling slope is equal to or less than the voltage Vs in the reset period of the second subfield.

As described above, the weaker the discharge occurs in the cell, the more gradually the slope of the voltage of the electrode gradually changes with time. Therefore, when the falling start voltage of the Y electrode is set to a low voltage as in the second embodiment, the falling slope of the Y electrode can be set more gently in a given falling period. Then, even when the strong discharge occurs in the rising period, the strong discharge can be prevented because the voltage of the Y electrode changes at a slower speed than in the first embodiment. In this case, an additional power source may not be used when the falling start voltage of the Y electrode is set to the reference voltage (0V).

For example, when the falling start voltage of the Y electrode is 0 V, the difference between the voltage applied to the X electrode and the Y electrode from the outside at the time of falling of the Y electrode and the difference of the voltage applied to the A electrode and the Y electrode are all 0 V and thus discharged. This does not happen. Next, when the voltage of the Y electrode gradually decreases from 0V, weak discharge occurs when the difference between the wall voltage formed in the cell and the voltage applied from the outside exceeds the discharge start voltage, so that the wall charge can be set. In the third embodiment of FIG. 8, the case where the falling start voltage of the Y electrode is set to 0V is illustrated. In this way, strong discharge can be prevented in the rising period of the reset period, and since the falling start voltage in the falling period is lowered, the falling period can also be reduced.

Specifically, after the end of the sustain period, wall charges are formed in the X electrode, the Y electrode, and the A electrode as shown in FIG. In the falling period of the second subfield, when the voltage of the Y electrode decreases to the voltage Vnf while the voltage of the Y electrode is applied to the Y electrode, the discharge occurs when the discharge start voltage Vfxy between the X electrode and the Y electrode is higher than the discharge. As described in the sustain period, the discharge between the X electrode and the Y electrode is caused to occur when the voltage of the Y electrode is near the -Vs voltage.

Since the wall voltage due to the wall charge between the A electrode and the Y electrode is smaller than the discharge start voltage Vfay between the A electrode and the Y electrode, even if a 0 V voltage is applied to the Y electrode, a discharge is generated between the A electrode and the Y electrode. Does not happen. When the voltage of the Y electrode is reduced to the -Vs voltage, the wall voltage due to the wall charge between the A electrode and the Y electrode can be discharged by the voltage (-Vs), and the falling start voltage of the Y electrode is -Vs. It can be set to a negative voltage higher than the voltage or to 0V. At this time, if the falling start voltage of the Y electrode is used as 0 V, no additional power supply is required.

In this case, the falling start voltage of the Y electrode is lowered in the falling period of the second subfield, so that the falling slope of the Y electrode can be set more gently in the given falling period, thereby preventing strong discharge in the falling period. Since the fall start voltage in the period is lowered, the fall period may be reduced.

The same applies to the falling period of the reset period of the first subfield.

On the other hand, in the first subfield, in general, since the discharge start voltage Vfay between the Y electrode and the A electrode is lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, at the final voltage Vnf of the falling period, Since the potential of the Y electrode due to the wall charge is higher than that of the A electrode, the wall voltage of the Y electrode with respect to the A electrode can be set to a positive voltage. Since the sustain discharge does not occur in the cell which does not have address discharge, the reset period of the next subfield is performed while maintaining the wall charge state. In the cell in this state, the wall voltage of the Y electrode to the A electrode is higher than the wall voltage of the Y electrode to the X electrode, so that when the voltage of the Y electrode increases in the rising period of the reset period, the voltage between the A electrode and the Y electrode is decreased. After a certain period of time passes after the discharge start voltage Vfay is exceeded, the voltage between the X electrode and the Y electrode exceeds the discharge start voltage Vfay.

프로세스라 한다. 일반적으로 플라즈마 표시 패널에서 A 전극은 색상 표현을 위해 형광체로 덮여 있는 반면, X 전극과 Y 전극은 유지방전의 효율을 위해 MgO 성분의 보호막과 같이 2차 전자 방출 계수가 높은 물질로 덮여 있다. 그런데 상승 기간에서 A 전극과 Y 전극 사이의 전압이 방전 개시 전압(Vfay)을 넘어도 형광체로 덮여 있는 A 전극이 음극으로 작용하기 때문에, A 전극과 Y 전극 사이에서 방전이 지연된다. 방전 지연에 의해 A 전극과 Y 전극 사이에서 실제 방전이 일어나는 시점에서는 A 전극과 Y 전극 사이의 전압이 방전 개시 전압(Vfay)보다 더 높은 전압이다. 따라서 이러한 높은 전압에 의해 A 전극과 Y 전극 사이에서 약 방전이 아닌 강 방전이 발생할 수 있다. 이러한 강 방전에 의해 X 전극과 Y 전극 사이에서도 강 방전이 일어나서 정상적인 상승 기간에서 생성되는 벽 전하보다 많은 양의 벽 전하가 셀에 형성되고 또한 많은 양의 프라이밍 입자가 생성될 수 있다.In the rising period of the reset period of the first subfield, since a high voltage is applied to the Y electrode, the Y electrode serves as the anode, and the A and X electrodes serve as the cathode. The discharge in the cell is determined by the amount of secondary electrons emitted from the cathode when the cation strikes the cathode.

It is called a process. In general, in the plasma display panel, the A electrode is covered with a phosphor for color expression, while the X electrode and the Y electrode are covered with a material having a high secondary electron emission coefficient such as a protective film of MgO component for efficiency of sustain discharge. However, in the rising period, even if the voltage between the A electrode and the Y electrode exceeds the discharge start voltage Vfay, since the A electrode covered with the phosphor acts as a cathode, the discharge is delayed between the A electrode and the Y electrode. When the actual discharge occurs between the A electrode and the Y electrode due to the discharge delay, the voltage between the A electrode and the Y electrode is higher than the discharge start voltage Vfay. Therefore, such a high voltage may cause a strong discharge rather than a weak discharge between the A electrode and the Y electrode. Such strong discharges also cause strong discharges between the X electrodes and the Y electrodes, so that a larger amount of wall charges are formed in the cell than the wall charges generated in the normal rising period, and a large amount of priming particles can be produced.

Then, a strong discharge may occur due to a large amount of wall charges and priming particles in the falling period, and thus, wall charges may not be sufficiently erased between the X electrode and the Y electrode as shown in FIG. 8. In the cell in this state, a high wall voltage is formed between the X electrode and the Y electrode even after the end of the reset period, and even if an address discharge does not occur due to this wall voltage, erroneous discharge may occur between the X electrode and the Y electrode in the sustain period. Hereinafter, an embodiment capable of preventing mis-discharge will be described in detail with reference to FIG. 9.

9 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

As shown in FIG. 9, the driving waveform according to the third embodiment of the present invention biases the A electrode to a constant voltage in the rising period of the reset period and the driving waveform according to the second embodiment of FIG. 6 in the falling period of the reset period. The same as in the first embodiment except that the falling period of the second subfield is applied in the same manner.

Specifically, in the rising period of the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while the A electrode is biased to a constant voltage (voltage higher than the reference voltage). In this case, when the Va voltage is used as the bias voltage of the A electrode as illustrated in FIG. 8, an additional power source may not be used. When the voltage of the Y electrode is increased while the voltage of the A electrode is biased to the Va voltage, the voltage between the A electrode and the Y electrode is smaller than that of the first embodiment so that the voltage between the X electrode and the Y electrode is smaller than the A and Y electrodes. The discharge start voltage is exceeded before the voltage in between. Then, a weak discharge occurs first between the X electrode and the Y electrode, and the voltage between the A electrode and the Y electrode exceeds the discharge start voltage while the priming particles are formed by the weak discharge. The priming particles reduce the discharge delay between the A electrode and the Y electrode, so that the weak discharge is performed without generating the strong discharge as described above, thereby forming a desired amount of wall charge. Therefore, weak discharge does not occur even in the falling period of the reset period, and thus, the false discharge in the sustain period can be prevented.

In FIG. 9, the A electrode is biased to a constant voltage during the rising period. Alternatively, the A electrode may be biased to the constant voltage only at the beginning of the rising period. As described above, in order to prevent the strong discharge from occurring in the rising period, it is necessary to prevent the voltage between the A and Y electrodes from exceeding the discharge start voltage before the voltage between the X and Y electrodes. It can also be biased at a constant voltage. That is, after weak discharge occurs between the A electrode and the Y electrode, the voltage of the A electrode can be set back to the reference voltage.

In FIG. 9, the A electrode is biased to a constant voltage in the rising period. Alternatively, the voltage of the A electrode may be gradually increased. If the voltage of the A electrode increases as the voltage of the Y electrode increases in the rising period, the voltage between the A electrode and the Y electrode is lower than when the A electrode voltage is biased to the reference voltage. Weak discharge may occur first. The period for increasing the voltage of the A electrode may be part of the rising period or the whole of the rising period.

It is also possible to float the A electrode without increasing the voltage of the A electrode. Since the capacitance component is formed by the A electrode and the Y electrode, when the A electrode is floated when the voltage of the Y electrode increases, the voltage of the A electrode also increases along with the voltage of the Y electrode. Therefore, the same effect as in FIG. 9 can be achieved. The floating period of the A electrode may be part of the rising period or the whole of the rising period.

As described above, according to the exemplary embodiment of the present invention, since the driving waveform is applied only to the Y electrode while the X electrode is biased to a predetermined voltage, the reset operation, the address operation, and the sustain discharge operation can be performed. The board can be removed. In addition, since the pulse for sustain discharge is supplied only from the scan driving board 300, the impedance in the path to which the sustain discharge pulse is applied may be constant.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan drive board, the impedance is always constant.

In addition, by lowering the start voltage of the falling slope of the scan electrode in the reset period and setting the falling slope gently, the strong discharge in the reset period can be prevented and the reset period can be shortened.

Claims (9)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In a state in which the voltage of the first electrode is biased to the first voltage, Changing a voltage of the second electrode to a second voltage which is equal to or less than a ground voltage in a reset period of a second subfield of the plurality of subfields; In the reset period of the second subfield, gradually decreasing the voltage of the second electrode from the second voltage to a third voltage, Gradually increasing a voltage of the second electrode from a fourth voltage to a fifth voltage in a reset period of a first subfield of the plurality of subfields, and Gradually decreasing a voltage of the second electrode from a sixth voltage to a seventh voltage in the reset period of the first subfield, And driving the voltage of the third electrode to a positive voltage state during at least part of a period in which the voltage of the second electrode increases to the fifth voltage. The method of claim 1, And the second voltage is higher than a low voltage applied to the second electrode for sustain discharge in a sustain period. The method of claim 2, And the second voltage is a ground voltage. The method of claim 1, And a ground voltage is applied to the third electrode while the voltage of the second electrode is reduced to the third voltage. delete The method according to any one of claims 1 to 4, And the first electrode is biased to the first voltage in an address period and a sustain period. The method of claim 6, And the first voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode; A control unit configured to drive one frame divided into a plurality of subfields, and And a driving board configured to apply a driving waveform for displaying an image by the plasma display panel to the second electrode and the third electrode and to bias the first electrode to a first voltage while the image is displayed. Chassis base facing display panel Including; The drive board, In a reset period of a second subfield of the plurality of subfields, the voltage of the second electrode is gradually decreased from a second voltage to a third voltage which is less than or equal to a ground voltage, In the reset period of the first subfield of the plurality of subfields, the voltage of the second electrode is gradually increased from the fourth voltage to the fifth voltage during the first period, and the voltage of the second electrode is increased during the second period. Gradually decrease from the sixth voltage to the seventh voltage, And applying a positive voltage to the third electrode in at least part of the first period. The method of claim 8, And the first voltage is a ground voltage.

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