KR100585052B1 - Apparatus and method for detecting frame synchronizing signal of compact disk system - Google Patents

Abstract

Disclosed are a frame synchronization signal detecting apparatus and method for a compact disc system. The apparatus comprises NRZI demodulation means for NRZI demodulation and serial output of an EFM signal, serial / parallel conversion means for converting and outputting NRZI demodulated signals output in parallel, and data decoded in parallel. Detects whether the pattern is a frame sync pattern, measures the width between the frame sync pattern detecting means for outputting a frame sync signal and the rising or falling edges of the EFM signal according to the detected result, and detects whether the measured width is 22T. And width measuring means for outputting a frame synchronization signal corresponding to the detected result, wherein the width measuring means includes first and second edge detection means for detecting rising and falling edges of the EFM signal, respectively, and the detected rising edge. First counting means for counting in response to and outputting a predetermined bit among the bits of the counted value in response to the detected rising edge, and the detected falling edge Counting in response, and re-joining the outputs of the second counting means and the first and second counting means outputting a predetermined bit among the bits of the counted value in response to the detected falling edge, and the result of the logical sum is a frame synchronization signal. A first logical sum means for outputting is provided, and the frame synchronizing signal can be accurately detected even with an EFM signal having a wrong level of slicing the RF signal.

Description

Apparatus and method for detecting frame synchronizing signal of compact disk system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal detection in compact disk (CD) systems, and more particularly, to an apparatus and method for detecting frame synchronization signals in a CD system.

Hereinafter, the structure and operation of a conventional frame synchronization signal detection apparatus will be described with reference to the accompanying drawings.

1 is a diagram illustrating a frame synchronization pattern, in which a bit string represents a Non Return to Zero Inverted (NRZI) representation.

2 is a block diagram of a conventional frame synchronizing signal detecting apparatus, which is composed of an NRZI demodulation unit 10, a shift register 12, and a frame synchronizing pattern detecting unit 14. As shown in FIG.

3A to 3E are waveform diagrams of respective parts shown in FIG. 2.

The NRZI demodulator 10 shown in FIG. 2 inputs an EFM: Eight to Fourteen Modulation (EFM) signal shown in FIG. 1 through an input terminal IN to demodulate NRZI and shift the NRZI demodulated signal. Output to register 12. The shift register 12 inputs 1-bit serial data output from the NRZI demodulation section 10, converts the serial data into 23 bits, and outputs the converted parallel data to the frame sync pattern detection section 14. The frame sync pattern detector 14 inputs and decodes 23 bits of parallel data, determines whether the decoded data pattern is a frame sync pattern, and outputs the frame sync signal enabled according to the determined result to the output terminal OUT. Is output via

In the above-described conventional frame synchronizing signal detecting apparatus, since the level 16 for slicing the RF signal is normal as shown in FIG. 3 (a), the normal EFM signal shown in FIG. ), The frame synchronization signal shown in FIG. 3C can be detected without error.

However, defects such as pin holes and interruptions caused by disc manufacturing defects do not accurately maintain the slicing level of the assembling circuit that distorts the digital optical signal and converts the RF signal into an EFM signal. Slicing the RF signal to the wrong level can result in unwanted EFM signals. In this case, since the level 18 for slicing the RF signal is abnormal as shown in FIG. 3 (b), an abnormal EFM signal is input to the NRZI demodulator 10 as shown in FIG. 3 (d). In this case, there is a problem in that an incorrect frame synchronization signal is detected as shown in FIG. That is, the conventional frame synchronizing signal detecting apparatus has a problem that the frame synchronizing signal cannot be properly detected due to a defect on the disk, a malfunction of the servo control, or a drop out.

An object of the present invention is to provide an apparatus for detecting a frame synchronization signal of a compact disc system capable of detecting a normal frame synchronization signal even with an abnormal EFM signal.

Another object of the present invention is to provide a frame synchronization signal detection method of a compact disc system performed by the frame synchronization signal detection apparatus.

A frame synchronization signal detection apparatus of a compact disc system according to the present invention for achieving the above object is NRZI demodulating the E.F.M. (EFM) signal, and outputs the NRZI demodulated signal in series. Demodulation means, serial / parallel conversion means for converting the NRZI demodulated signal output in series and outputting in parallel, decoding the parallel converted signal, and detecting whether a pattern of the decoded data is a frame synchronization pattern; And measuring the width between the frame sync pattern detecting means for outputting the frame sync signal according to the detected result and the rising edges or the falling edges of the EFM signal, wherein the measured width is 22T (where T is the width of the reference clock signal). And width measuring means for detecting the period of time) and outputting the frame synchronizing signal in accordance with the detected result,

The width measuring means counts in response to the first edge detecting means for detecting the rising edge of the EFM signal, the second edge detecting means for detecting the falling edge of the EFM signal, and the detected rising edge, First counting means for outputting a predetermined bit among the bits of the counted value in response to the detected rising edge, a value counted in response to the detected falling edge, and counted in response to the detected falling edge again. And a second counting means for outputting a predetermined bit among the bits of? desirable.

In order to achieve the above another object, the frame synchronization signal detection method according to the present invention for detecting the frame synchronization signal in the frame synchronization signal detection apparatus of the compact disc system, the frame synchronization signal of the E.F. Determining whether to detect using the width, and if the frame synchronization signal is to be detected using the width, obtaining a frame synchronization signal according to whether the width of the EFM signal is 22T, and obtaining the frame synchronization signal. In the case where it is not desired to detect using the width, the frame synchronization signal is preferably obtained according to whether the data decoded by demodulating the EFM signal is a frame synchronization pattern.

Hereinafter, the structure and operation of the apparatus for detecting frame synchronization signal of a compact disc system according to the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of a frame synchronization signal detection apparatus according to the present invention, wherein the NRZI demodulation unit 50, the serial / parallel conversion unit 52, the frame synchronization pattern detection unit 54, the first and second edge detection units ( 32 and 34, first and second counters 36 and 38, and an OR gate 40, a width measuring unit 30, an AND gate 56, and an OR gate 58.

5A to 5G are waveform diagrams of respective parts of the apparatus shown in FIG. 4, and FIGS. 5A and 5B show waveform diagrams of an EFM signal, and FIG. An output waveform diagram of the second edge detector 32 or 34 is shown, and FIG. 5 (d) illustrates a waveform diagram of the output WFsync of the width measurement unit 30, and FIG. 5E illustrates the NRZI demodulator 50. Fig. 5 (f) shows an output waveform diagram of the frame synchronizing pattern detection unit 54, and Fig. 5 (g) shows a waveform diagram of the final frame synchronizing signal output from the OR gate 58. Represent each.

The NRZI demodulator 50 shown in FIG. 4 performs the same role as the NRZI demodulator 10 shown in FIG. 2. That is, the NRZI demodulation is performed by inputting the EFM signal shown in FIG. 5 (a) or FIG. 5 (b) through the input terminal IN, and the serial / parallel conversion unit 52 converts the signal shown in FIG. ) The serial / parallel conversion unit 52 plays a role corresponding to the shift register 12 shown in FIG. 2. That is, the serial data output from the NRZI demodulator 50 by one bit is converted into parallel data and stored, and the converted parallel data is output to the frame sync pattern detector 54. The frame sync pattern detector 54 corresponds to the frame sync pattern detector 14 shown in FIG. 2 and may be implemented with 23 registers. The 23-bit parallel data output from the serial / parallel converter 52 is used. Decode the frame synchronization signal, detect whether or not the decoded parallel data pattern is a frame synchronization pattern, and enable the OR gate 58 with the frame synchronization signal PFsync shown in FIG. Output

The above is the same as the conventional apparatus shown in FIG. 2, and as described above, when the EFM slicing level is wrong and the phase difference of the EFM signal is changed, the frame synchronization signal cannot be detected accurately. Therefore, the frame synchronization signal detection apparatus according to the present invention shown in Fig. 4 solves this problem by using a unique property in which the sections of the "high" and "low" logic levels of the EFM signal are each 11T. That is, the total width of the "high" and "low" logic levels of the EFM signal needed to obtain the frame sync signal is 22T (where T is 1 / 4.3218MHz or 231.39 as the reference clock signal, regardless of the level of slicing the RF signal). Use the nature of For example, if the EFM slicing level is operating normally, the EFM signal will have the "high"-"low" logic level or "low"-"high" logic level of 11T-11T, but if the slicing level is abnormal, the EFM signal will be 10T-12T, 12T-10T, ..., etc. have a "high"-"low" or "low"-"high" logic level. However, the total width of the "low" and "high" levels of the EFM signal does not change as 22T.

The width measuring unit 30 shown in FIG. 4 using this property measures the width between rising edges or falling edges of the EFM signal input through the input terminal IN, and detects whether the measured width is 22T, and detects the detected width. The frame sync signal WFsync is output according to the result.

To this end, the first edge detector 32 of the width measurement unit 30 detects the rising edges 60 and 62 of the EFM signal shown in FIG. 5 (a) input through the input terminal IN, and is detected. The edge signals 68 and 69 shown in FIG. 5C are output to the first counter 36. The second edge detector 34 detects the falling edges 64 and 66 of the EFM signal shown in FIG. 5B input through the input terminal IN, and detects the edge signal shown in FIG. 5C. Fields 68 and 69 are output to the second counter 38. Meanwhile, the first counter 36 counts in response to the edge signal 68 shown in FIG. 5C output from the first edge detector 32 and counts in response to the edge signal 69. A predetermined bit of the bits of the value is output to the OR gate 40. Similarly, the second counter 38 counts in response to the edge signal 68 shown in FIG. 5C output from the second edge detector 34 and counts in response to the edge signal 69. A predetermined bit of the bits of the value is output to the OR gate 40. The OR gate 40 performs an OR on the bits output from the first counter 36 and the second counter 38, and uses the AND result 56 as the frame synchronization signal WFsync as the result of the OR shown in FIG. 5D. )

On the other hand, when the system operating state is unstable, the frame synchronization signal PFsync should be used instead of the frame synchronization signal WFsync. This is because the 11T component is correctly detected when the disk rotation speed is normal, but any component other than the 11T component (values between 3T and 11T when the servo system is unlocked due to an abnormality in the disk rotation speed). ) May appear as an 11T component.

To this end, the AND gate 56 and the OR gate 58 perform the following operations. At this time, the controller (not shown) checks whether the compact disc rotates at a normal speed, and outputs a "high" logic level lock signal when the disc rotates normally, otherwise the "low" logic level Outputs the lock signal (LOCK). The AND gate 56 logically multiplies the lock signal LOCK and the frame synchronization signal WFsync shown in FIG. 5D, and outputs the result of the logical multiplication to the OR gate 58, and the OR gate 58 is ANDed. The output of the gate 56 is ORed together with the frame synchronization signal PFsync shown in FIG. 5 (f), and the result shown in FIG.

That is, when the disk rotation speed is normal, one of the frame synchronization signals FWsync and PFsync is used as the final frame synchronization signal. When the disk rotation speed is not normal, the frame synchronization signal PFsync is used as the final frame synchronization. Used as a signal.

FIG. 6 is a flowchart for explaining a method for detecting a frame sync signal according to the present invention, which is performed by the apparatus shown in FIG. 4, and determining whether the system is normal and how to obtain the frame sync signal. Step 72), obtaining the frame synchronization signal using the frame synchronization pattern (steps 74 to 84), and obtaining the frame synchronization signal using the width of the EFM signal (steps 84 to 90).

In the frame synchronizing signal detection method according to the present invention, first, it is judged whether the disk rotates at a predetermined speed, for example, 1.2 to 1.4 kHz (step 70). If the disk rotates at a predetermined speed, it is assumed that the operating state of the system is stable. Therefore, the frame synchronization signal SY is obtained using the width of the EFM signal or the frame synchronization signal SY using the frame synchronization pattern. (Step 72).

If the frame synchronization signal is to be obtained using the frame synchronization pattern, the frame synchronization signal SY is obtained as follows (steps 74 to 84). That is, the NRZI demodulates the EFM signal (step 74). After step 74, the NRZI demodulated serial signal is converted into a parallel signal (step 76). After operation 76, the transformed parallel signal is decoded (operation 78). After operation 78, it is determined whether the pattern of decoded data is a frame synchronization pattern (operation 80). If the pattern of the decoded data is the frame synchronization pattern, the frame synchronization signal is enabled (step 82). However, if the pattern of data is not a frame synchronizing pattern, the frame synchronizing signal is disabled (step 84).

However, when the frame synchronization signal is to be obtained using the width of the EFM signal, the frame synchronization signal is obtained as follows (steps 84 to 90). That is, the width between the rising edges or the falling edges of the EFM signal is measured as described above (step 86). After step 86, it is determined whether the measured width is 22T (step 88). If the width is 22T, the frame synchronization signal is enabled (step 90). However, if the width is not 22T, the frame synchronization signal is disabled (step 84).

Hereinafter, the configuration and operation of a preferred modified embodiment according to the present invention of the width measuring unit 30 shown in FIG. 4 will be described with reference to the accompanying drawings.

FIG. 7 is a circuit diagram of a modified embodiment of the width measuring unit 30 shown in FIG. 4 according to the present invention, and includes first and second edge detectors 100 and 102 and first and second counters 104. And a signal selector 108.

The first edge detector 100 illustrated in FIG. 7 includes D flip-flops 110 and 112, a buffer 124, and a NAND gate 114, and the rising edge of the EFM signal input through the input terminal IN. The detected edge signal is output to the first counter 104. Here, RSTB means an inverted reset signal, CLK represents a reference clock signal and the period is T. On the other hand, the second edge detector 102 is composed of the D flip-flops 116 and 118, the buffer 122 and the OR gate 120, detects the falling edge of the EFM signal input through the input terminal IN, The detected edge signal is output to the second counter 106.

The first counter 104 includes inverters 126 and 144, first through fifth logic combinations 128, 130, 132, 134 and 136, NAND gates 138 and 140, NOR gate 142 and AND gate 146. Each of the first to fifth logic combination units 128, 130, 132, 134, and 136 inputs an edge signal output from the first edge detector 100 to the data enable terminal DEN, and then, from the inverter 126. Input the inverted supply power VDD outputted to the data input terminal D, input the power supply to the trigger terminal T, and in response to the inverted reset signal RSTB input to the reset terminal RN. It is reset. That is, the first to fifth logic combination units 128, 130, 132, 134, and 136 perform a counting operation, and output the counted value to the NAND gates 138 and 140. The second counter 106 includes inverters 150 and 168, sixth through tenth logic combinations 152, 154, 156, 158 and 160, NAND gates 162 and 164, a NOR gate 166 and And gate 170, and performs the same operation as the first counter (104).

Meanwhile, the signal selector 108 includes an OR gate 172, a NAND gate 174, D flip-flops 178 and 180, and a buffer 176. The OR gate 172 ORs the signals A and B output from the first and second counters 104 and 106, respectively, and outputs the OR result as the frame synchronization signal WFsync to the NAND gate 174. do. The NAND gate 174 inverts ANDs the output of the lock signal LOCK and the OR gate 172, and outputs the result of the inverse AND to the D flip-flop 178. Therefore, the frame synchronization signal corresponding to the output of the AND gate 56 shown in FIG. 4 is output through the positive output terminal Q of the D flip-flop 180.

FIG. 8 is a circuit diagram of an exemplary embodiment of each of the logic combination units shown in FIG. 7 according to the present invention, including AND gates 200 and 202, NOR gates 204 and 208, inverter 210, and eleventh logic. Combination unit 206 is configured.

The AND gate 200 illustrated in FIG. 8 performs a logical AND operation on a signal input through the trigger terminal T and a signal input through the data input terminal D, and the AND gate 202 is output from the inverter 210. The input of the inverted trigger terminal T and the negative output QN of the eleventh logic combination unit 206 are logically output. The NOR gate 204 inverts and outputs the outputs of the AND gates 200 and 202. The eleventh logic combination unit 206 inputs an output of the NOR gate 204 to the trigger input terminal TI, inputs an input of the data enable terminal DEN to the trigger enable terminal TE, and a clock terminal. The signal input to (CK) is clocked in and reset in response to the signal input to the reset terminal RN.

FIG. 9 is a circuit diagram of an exemplary embodiment of the eleventh logic combination unit 206 shown in FIG. 8 according to the present invention, including inverters 220, 222, 230, 236, 246, 248 and 250, and transmission gates ( 232, 234, 240 and 242, AND gates 224 and 226, NOR gate 228 and NAND gates 238 and 244.

The transmission gates 232, 234, 240, and 242 shown in FIG. 9 are an output of the NOR gate 228, an output of the transmission gate 232, and an inverter 236 in response to a clock signal output from the inverter 230. And the output of the inverter 222 is output to the next stage. Therefore, the inverter 248 inverts the signal output from the NAND gate 244 and outputs it as the positive output signal Q, and the inverter 250 inverts the signal output from the inverter 246 to output the negative output signal QN. Output as

As described above, the apparatus and method for detecting a frame synchronization signal of a compact disc system according to the present invention have an effect of accurately detecting a frame synchronization signal even with an incorrect EFM signal due to an incorrect slicing level of an RF signal.

1 is a diagram illustrating a frame sync pattern.

2 is a block diagram of a conventional frame synchronization signal detection apparatus.

3A to 3E are waveform diagrams of respective parts shown in FIG. 2.

4 is a block diagram of a frame synchronization signal detection apparatus according to the present invention.

5A to 5G are waveform diagrams of respective parts of the apparatus shown in FIG. 4.

FIG. 6 is a flowchart for explaining a method for detecting a frame sync signal according to the present invention, which is performed in the apparatus shown in FIG. 4.

7 is a circuit diagram of a modified embodiment according to the present invention of the width measuring part shown in FIG. 4.

FIG. 8 is a circuit diagram of one preferred embodiment of the present invention for each of the logical combinations shown in FIG.

9 is a circuit diagram of one preferred embodiment of the present invention of the eleventh logical combination portion 206 shown in FIG.

Claims (7)

NRZI demodulation means for non-return zero inversion (NRZI) demodulation of the E. F. (EFM) signal and outputting the NRZI demodulated signal in series; Serial / parallel conversion means for converting and outputting the NRZI demodulated signals output in series in parallel; Frame synchronization pattern detecting means for decoding the parallel converted signal, detecting whether the decoded data pattern is a frame synchronization pattern, and outputting a frame synchronization signal in accordance with the detected result; And Measure the width between the rising edges or the falling edges of the EFM signal, detect whether the measured width is 22T (where T is the period of the reference clock signal), and output the frame sync signal according to the detected result With width measuring means to do The width measuring means First edge detecting means for detecting the rising edge of the EFM signal; Second edge detecting means for detecting the falling edge of the EFM signal; First counting means for counting in response to the detected rising edge and outputting a predetermined bit among bits of a value counted in response to the detected rising edge; Second counting means for counting in response to the detected falling edge and outputting a predetermined bit among bits of a value counted in response to the detected falling edge; And And a first logical sum means for ORing the outputs of the first counting means and the second counting means and outputting the result of the logical sum as the frame synchronizing signal. The apparatus of claim 1, wherein the apparatus for detecting a frame sync signal of the compact disk system having a compact disk includes: Logical multiplication means for logically multiplying the frame synchronization signal and the locking signal output from the width measuring means; And And second logical sum means for logically summing the frame synchronizing signal output from the frame synchronizing pattern detecting means and the output of the logical product, and outputting the result of the logical sum as a final frame synchronizing signal, And the locking signal is generated according to whether the rotational speed of the compact disc is a predetermined speed. A frame synchronization signal detection method for detecting a frame synchronization signal in a frame synchronization signal detection apparatus of a compact disc system, (a) determining whether to detect the frame synchronization signal using a width of an E. F. signal; (b) when the frame synchronization signal is to be detected using the width, obtaining a frame synchronization signal according to whether the width of the EFM signal is 22T (where T is a period of a reference clock signal); And and (c) when the frame synchronization signal is not to be detected using the width, obtaining the frame synchronization signal according to whether the data decoded by demodulating the EFM signal is a frame synchronization pattern. Method of detecting frame synchronization signal of disk system. The method of claim 3, wherein step (b) Measuring the width between rising or falling edges of the EFM signal; Determining whether the measured width is 22T; When the width is 22T, enabling the frame sync signal; And And disabling the frame synchronizing signal when the width is not the 22T. The method of claim 3, wherein step (c) Non-return zero inversion (NRZI) demodulation of the EFM signal: Converting the NRZI demodulated serial signal to a parallel signal; Decoding the parallel converted signal; Determining whether a pattern of decoded data is the frame synchronization pattern; Enabling the frame sync signal if the pattern of decoded data is the frame sync pattern; And And disabling the frame synchronizing signal if the pattern of the data is not the frame synchronizing pattern. The method of claim 3, wherein the frame synchronization signal detection method of the compact disc system having the compact disc Determining whether the compact disc rotates at a predetermined speed; If the compact disc does not rotate at the predetermined speed, the process proceeds to the step (c); if the compact disc rotates at the predetermined speed, the process proceeds to the step (a). Way. The method of claim 3, wherein the frame synchronization signal detection method of the compact disc system having the compact disc Determining whether the compact disc rotates at a predetermined speed; And If the compact disc does not rotate at the predetermined speed, the frame synchronizing signal obtained in the step (c) is determined as the final frame synchronizing signal, and if the compact disc rotates at the predetermined speed, the step (b) or (c) And determining the frame synchronization signal obtained in step) as the final frame synchronization signal.

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