KR100552906B1 - Mehtod and apparatus for driving data of liquid crystal display - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a data driving apparatus and method for a liquid crystal display device capable of preventing image degradation.

A data driving device of a liquid crystal display according to the present invention includes a shift register unit for generating a first sampling signal supplied sequentially and a second sampling signal supplied simultaneously, and sequentially latching the image data in response to a first sampling signal. And a latch unit for simultaneously outputting and simultaneously latching and outputting the black data in response to the second sampling signal.

Description

METHOD AND APPARATUS FOR DRIVING DATA OF LIQUID CRYSTAL DISPLAY}             

1 is a view schematically showing a data driving device of a conventional liquid crystal display.

FIG. 2 is a block diagram showing a detailed configuration of the data driver integrated circuit shown in FIG.

3A and 3B show details of the shift register and latch shown in FIG.

FIG. 4 shows pixel data supplied to the latch shown in FIG. 3B during one horizontal period; FIG.

FIG. 5 illustrates a problem in which synchronization is inconsistent when using the pixel data shown in FIG. 4. FIG.

6A and 6B illustrate a shift register and a latch of a data driving device of a liquid crystal display according to an exemplary embodiment of the present invention in detail.

FIG. 7 shows pixel data supplied to the latch shown in FIG. 6B during one horizontal period; FIG.

FIG. 8 shows pixel data supplied to the latch shown in FIG. 6B to synchronize synchronization; FIG.

<Description of main parts of drawing>

2: liquid crystal panel 4: data driving integrated circuit (IC)

6: Tape Carrier Package (TCP) 8: Data Printed Circuit Board (PCB)

10 signal control unit 12 gamma voltage unit

14: shift register portion 16: latch portion

15,115: shift register 17,117: latch

18: digital-to-analog conversion (DAC) section 20: P decoding section

22: N decoding section 24: multiplexer (MUX) section

26: output buffer unit 30,130: flip-flop

32,132: path providing unit 50,150: first flip-flop

52,152: second flip-flop 54,154: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a data driving device and a method of a liquid crystal display device capable of preventing deterioration in image quality.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to one of the data lines via source and drain terminals of a thin film transistor (hereinafter, referred to as a TFT) as a switching element. The gate terminal of the TFT is connected to any one of the gate lines for causing the pixel voltage signal to be applied to the pixel electrodes for one line. The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell. The data driver and the gate driver are integrated into a plurality of integrated circuits (hereinafter, referred to as ICs). Each of the integrated data driver IC and the gate driver IC is mounted on a tape carrier package (hereinafter referred to as TCP) and connected to a liquid crystal panel using a tape automated bonding (TAB) method, or a chip on glass ) Is mounted on the liquid crystal panel.

FIG. 1 schematically illustrates a data driving device of a conventional liquid crystal display device. The data driving device includes data driving ICs 4 and TCP 6 connected to the liquid crystal panel 2 through TCP 6. A data printed circuit board (hereinafter referred to as a PCB) 8 connected to the data driving ICs 4 is provided.

The data PCB 8 inputs various control signals and data signals supplied from a timing controller (not shown) and drive voltage signals from a power unit (not shown) to relay to the data driver ICs 4. Play a role. The TCP 6 is electrically connected to the data pads provided at the upper end of the liquid crystal panel 2 and also to the output pads provided at the data PCB 8. The data driving ICs 4 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines on the liquid crystal panel 2.

To this end, each of the data driver ICs 4 includes a shift register 14 for supplying a sequential sampling signal as shown in FIG. 2, and sequentially latches pixel data VD in response to the sampling signal. A latch unit 16 for outputting, a digital-to-analog converter (hereinafter referred to as a DAC unit) 18 for converting pixel data VD from the latch unit 16 into a pixel voltage signal, and a DAC 18. And an output buffer unit 26 for buffering and outputting the pixel voltage signal. In addition, the data driver IC 4 includes a signal controller 10 for relaying various control signals supplied from a timing controller (not shown) and pixel data VD, and a positive polarity required by the DAC unit 18. And a gamma voltage unit 12 for supplying negative gamma voltages. Each of the data driving ICs 4 having such a configuration drives n data lines DL1 to DLn.

The signal controller 10 controls various control signals (SSP, SSC, SOE, REV, POL, etc.) and pixel data VD from the timing controller (not shown) to be output to the corresponding components.

The gamma voltage unit 12 subdivides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The n / 6 shift registers included in the shift register unit 14 sequentially shift the source start pulse SSP from the signal controller 10 according to the source sampling clock signal SSC and output the sampling signal.

The latch unit 16 sequentially samples and latches the pixel data VD from the signal control unit 10 in predetermined units in response to a sampling signal from the shift register unit 14. To this end, the latch unit 16 is composed of n latches for latching n pixel data VD, each of which corresponds to the number of bits (3 or 6 bits) of the pixel data VD. Has a size. In particular, the timing controller (not shown) divides the pixel data VD into even pixel data VDeven and odd pixel data VDodd to simultaneously output them through respective transmission lines in order to reduce the transmission frequency. The even pixel data VDeven and the odd pixel data VDodd each include red (R), green (G), and blue (B) pixel data. Accordingly, the latch unit 16 simultaneously latches even pixel data VDeven and odd pixel data VDodd, that is, six pixel data, supplied through the signal controller 10 for each sampling signal. Subsequently, the latch unit 16 simultaneously outputs the n pixel data VD latched in response to the source output enable signal SOE from the signal controller 10. In this case, the latch unit 16 restores and outputs the modulated pixel data VD to reduce the number of transition bits in response to the data inversion selection signal REV. This is because the timing control unit modulates and supplies the pixel data VD whose transition bit number exceeds a reference value in order to minimize electromagnetic interference (EMI) during data transmission.

The DAC unit 18 simultaneously converts the pixel data VD from the latch unit 16 into positive and negative pixel voltage signals and outputs the same. To this end, the DAC unit 18 is a P (Positive) decoding unit 20 and a N (Negative) decoding unit 22 commonly connected to the latch unit 16, a P decoding unit 20 and an N decoding unit ( And a multiplexer (MUX) 24 for selecting an output signal of 22).

The n P decoders included in the P decoding unit 20 convert n pixel data simultaneously input from the latch unit 16 into the positive pixel voltage signal using the positive gamma voltages from the gamma voltage unit 12. Done. The n N decoders included in the N decoding unit 22 convert the n pixel data simultaneously input from the latch unit 16 into the negative pixel voltage signal using the negative gamma voltages from the gamma voltage unit 12. Done. The n multiplexers included in the multiplexer section 24 have a positive pixel voltage signal from the P decoder 20 or a negative polarity from the N decoder 22 in response to the polarity control signal POL from the signal controller 10. The pixel voltage signal is selected and output.

The n output buffers included in the output buffer unit 26 are composed of a voltage follower connected to the n data lines D1 to Dn in series. These output buffers buffer the pixel voltage signals from the DAC unit 18 and supply them to the data lines DL1 to DLn.

3A and 3B show details of the shift register 15 and the latch 17 in the data driver IC 4 shown in FIG.

Referring to FIG. 3A, the conventional shift register 15 is supplied to the flip-flop 30 and the flip-flop 30 for sequentially sampling the source start pulse SSP corresponding to the source sampling clock SSC. A plurality of shift stages SST1 to SSTn including a path providing unit 32 for providing a path of a sampling signal is provided.

The flip-flop 30 generates a sampling signal in response to the source sampling clock SSC and the source start pulse SSP (or sampling signal) supplied thereto. The path providing unit 32 supplies the source start pulse SSP or the sampling signal supplied to the path supply unit 32 to the flip-flop 30 to which it is connected.

Meanwhile, the shift register 15 includes a first terminal 40, a second terminal 42, a third terminal 44, a fourth terminal 46, and a fifth terminal 48.

The first terminal 40 determines the shift direction of the shift register 15. For example, when a high signal is input to the first terminal 40, the shift direction of the shift register 15 is set to the right, and in other cases, the shift direction is set to the left. At this time, the shift direction is set to the left by the inverter INT in which the first terminal 40 is connected to the input terminal and the output terminal is connected to the path providing unit 32.

The second terminal 42 receives a source sampling clock (SSC) signal from the signal controller 10.

The third terminal 44 receives a source start pulse SSP signal from the signal controller 10 when a high signal is input to the first terminal 40. Otherwise, the third terminal 44 receives the source start pulse SSP signal from the shift register 15. The generated carry signal is supplied to the next stage D-IC.

The fourth terminal 46 supplies a carry signal Carry generated from the shift register 15 to the next stage D-IC when a high signal is input to the first terminal 40. Receives a source start pulse (SSP) signal from the signal controller 10.

The fifth terminals SP1 to SPn sequentially supply the sampling signal to the latch 17.

Here, the sampling signal of the first shift stage SST1 is supplied to the input terminal, the first buffer BF1 to which the output terminal is connected to the third terminal 44, and the sampling signal of the nth stage STn The role of the third and fourth terminals 44 and 46 is changed by the second buffer BF2 which is supplied to the input terminal and the output terminal is connected to the fourth terminal 46. That is, when a high signal is input to the first terminal 40, the first buffer BF1 does not operate and the second buffer BF2 operates, so that the third terminal 44 starts the source. The pulse SSP is supplied to the first shift stage SST1, and the fourth terminal 46 receives a carry signal from the n th shift stage SSTn. When the low signal is input to the first terminal 40, the first buffer BF1 is operated and the second buffer BF2 is not operated, so the third terminal 44 is the nth stage. The carry signal is input from STn, and the fourth terminal 46 supplies the source start pulse SSP to the first shift stage SST1.

In addition, the shift register 15 may supply the source start pulse SSP to the first shift stage SST1 or the nth shift stage SSTn according to the shift direction of the shift register. And a second AND gate AND2.

In the first AND gate AND1, the output of the first terminal 40 and the output of the third terminal 44 are supplied as input terminals, and the output terminal is supplied to the first shift stage SST1. The first AND gate AND1 receives the data of "1" from the first terminal 40 and the source start pulse SSP having the data of "1" supplied from the third terminal 44. It outputs 1 "and supplies the source start pulse SSP to the 1st shift stage SST1. At this time, the shift register 15 shifts to the right from the first shift stage SST1. Meanwhile, the first AND gate AND1 does not supply the source start pulse SSP to the first shift stage SST1 unless the first terminal 40 receives the data of “1” from the first terminal 40.

In the second AND gate AND2, the output of the inverter INT and the output of the fourth terminal 46 are supplied to the input terminal, and the output terminal is supplied to the nth shift stage SSTn. When the data of " 0 " is input to the first terminal 40, the second AND gate AND2 receives the data of " 1 " by the inverter INT and " 1 supplied from the fourth terminal 46 ". "1" is output by the source start pulse SSP having the data of "", and the source start pulse SSP is supplied to the nth shift stage SSTn. At this time, the shift register 15 shifts to the left from the n th shift stage SSTn. On the other hand, the second AND gate AND2 does not supply the source start pulse SSP to the nth shift stage SSTn unless the data of "1" is supplied from the inverter INT.

Meanwhile, the i (i is a natural number) th shift stage (SSTi) path providing unit 32 may be connected to the third terminal 44 or the fourth terminal 46 at which one terminal outputs the source start pulse SSP. A third end gate AND3 connected to the i-th fifth terminal SPi-1, the other terminal connected to the first terminal 40, and one terminal connected to the inverter INT, A fourth end gate AND4 having the other terminal connected to the fifth terminal SPi + 1 of the i + 1th shift stage SSTi + 1, and an input terminal having a third end gate AND3 and a fourth end; The OR gate is connected to the gate AND4 and the output terminal is connected to the input terminal of the flip-flop 30.

The third AND gate AND3 receives the source start pulse SSP having the data of "1" from the third terminal 44 when the shift register 15 shifts to the right, or from the fifth terminal 48. When the sampling signal of the previous stage having the data of 1 "is supplied and the data of" 1 "is supplied from the first terminal 40, the data of" 1 "is output.

The fourth AND gate AND4 receives the source start pulse SSP having data of "1" from the fourth terminal 46 or moves from the fifth terminal 48 when the shift register 15 shifts to the left. When the sampling signal of the previous stage having the data of 1 "is supplied and the data of" 1 "is supplied from the inverter INT, the data of" 1 "is output.

The OR gate OR receives one of the outputs of the third and fourth AND gates AND3 and AND4 and supplies it to the flip-flop 30.

Herein, the operation of the shift stage will be described in detail. First, the source sampling clock SSC and the source start pulse SSP are input from the signal controller 10. At this time, it is assumed that the shift direction of the shift register 15 is set to the right. The source sampling clock SSC input from the signal controller 10 is input to the clock terminal of the flip-flop 30 included in the first shift stage SST1. The source start pulse SSP input from the signal controller 10 is supplied to one terminal of the first AND gate AND1. Here, because the data of "1" is supplied to the other terminal of the first AND gate AND1 (that is, shifted to the right), the first AND gate AND1 shifts the data of "1" to the first shift. It is supplied to the path control part 32 included in the stage SST1.

In fact, the data of "1" supplied from the first AND gate AND1 is input to one terminal of the third AND gate AND3. At this time, since the data of " 1 " of the first terminal 40 is input to the other terminal of the third AND gate AND3, the third AND gate AND3 receives the data of " 1 " Will output The OR gate OR, which receives data of “1” from the third AND gate AND3, supplies a data signal of “1” to an input terminal of the flip-flop 30.

Meanwhile, the source sampling clock SSC signal input to the second terminal 42 is supplied to the flip-flop 30 of the first shift stage SST1. At this time, since the data of "1" is input to the input terminal of the flip-flop 30 of the first shift stage SST1, the flip-flop 30 of the first shift stage SST1 is "1". Data is output to the first fifth terminal SP1 terminal. Here, the sampling signal of "1" output to the first fifth terminal SP1 is input to the path control unit 32 of the second shift stage SST2.

A sampling signal of "1" input to the path controller 32 of the second shift stage SST2 is input to one terminal of the third AND gate AND3. At this time, since the data of " 1 " of the first terminal 40 is input to the other terminal of the third AND gate AND3, the third AND gate AND3 receives the data of " 1 " Will output The OR gate OR, which receives data of “1” from the third AND gate AND3, supplies a data signal of “1” to an input terminal of the flip-flop 30.

On the other hand, the source sampling clock SSC signal input to the second terminal 42 is supplied to the flip-flop 30 of the second shift stage SST2. At this time, since the data "1" is input to the input terminal of the flip-flop 30 of the second shift stage SST2, the flip-flop 30 of the second shift stage SST2 is the data of "1". Is output to the second fifth terminal SP2 terminal. Here, the sampling signal of "1" output to the second fifth terminal SP2 is input to the path controller 32 of the third shift stage SST3.

In practice, the shift register 15 repeats this operation and sequentially supplies the sampling signal (ie, data of "1") to the first fifth terminal SP1 to the nth fifth terminal SPn.

Referring to FIG. 3B, the latch 17 includes a first flip-flop 50 and a first flip-flop 50 for sequentially outputting data latched according to a sampling signal sequentially sampled by the shift register 15. The second flip-flop 52 and the data inversion selection signal REV which sequentially latch the data outputted from the N-th output and simultaneously output the n pixel data latched in correspondence to the source output enable signal SOE. A plurality of latch stages RST1 to RSTn including a multiplexer 54 for restoring, time-dividing and outputting the modulated pixel data VD so as to reduce the number of transition bits.

The first flip-flop 50 supplies the pixel data VD latched to the second flip-flop 52 in response to the sampling signal and the pixel data VD supplied to the first flip-flop 50. The second flip-flop 52 latches the n pixel data VD supplied to the second flip-flop 52 and simultaneously supplies the multiplexer 54 to the multiplexer 54 in response to the source output enable signal SOE. The multiplexer 54 recovers and time-divisions the pixel data VD modulated to reduce the number of transition bits in response to the data inversion selection signal REV supplied from the signal controller 10.

The latch 17 includes a sixth terminal 60, a seventh terminal 62, and an eighth terminal 64.

The sixth terminal 60 receives n pixel data VD from the signal controller 10. The seventh terminal 62 receives a source output enable signal SOE for simultaneously outputting the n pixel data VD latched from the signal controller 10. The eighth terminal 64 receives a data inversion selection signal REV for restoring the pixel data VD modulated such that the number of transition bits is reduced from the signal controller 10.

Herein, the operation of the latch stage will be described in detail. First, the sampling signal output from the shift register 15 is input and the n pixel data VD is input from the signal controller 10. The sampling signal output from the shift register 15 is input to the clock terminal of the first flip-flop 50 included in the first latch stage RST1. The pixel data VD input from the signal controller 10 is supplied to an input terminal of the first flip-flop 50 included in the first latch stage RST1. Then, the pixel data VD latched on the first flip-flop 50 included in the first latch stage RST1 is input to the second flip-flop 52 included in the first latch stage RST1. The new pixel data VD is latched to the first flip-flop 50 included in the first latch stage RST1. Thereafter, the sampling signal output from the shift register 15 is input to the clock terminal of the first flip-flop 50 included in the second latch stage RST2. The pixel data VD input from the signal controller 10 is supplied to an input terminal of the first flip-flop 50 included in the second latch stage RST2. Then, the pixel data VD latched on the first flip-flop 50 included in the second latch stage RST2 is input to the second flip-flop 52 included in the second latch stage RST2. The new pixel data VD is latched to the first flip-flop 50 which is supplied to the second latch stage RST2.

In practice, the latch 17 receives the sampling signals sequentially from the shift register 15 and respectively stores the pixel data VD latched in the first flip-flop 50 included in each latch stage RST1 to RSTn. The second flip-flop 52 included in the latch stages RST1 to RSSTn may be sequentially latched. That is, the second flip-flop included in the first to n-1 latch stages RST1 to RSTn-1 until the pixel data VD is latched to the second flip-flop 52 of the last latch stage RSSTn. At 52, pixel data VD is latched.

Thereafter, a source output enable (SOE) signal is input from the signal controller 10 to the clock terminal of the second flip-flop 52. Accordingly, all the pixel data VDs of one line latched in the second flip-flop 52 are simultaneously output to the multiplexer 54. At this time, in response to the data inversion selection signal REV input from the signal controller 10 to the multiplexer 54, the pixel data VD modulated so as to reduce the number of transition bits is recovered and time-divided.

On the other hand, in the liquid crystal display device, the pixel data VD is supplied to the liquid crystal cell during the scanning period in which the gate high voltage Vgh is supplied, and the pixel data voltage supplied to the liquid crystal cell is maintained in the remaining frame period except for the scanning period. Is displayed during the frame period. Accordingly, the liquid crystal display device blurs the display image in the moving image due to the retention characteristics. This difference in perceptual image is due to the integral effect of the image which is temporarily persisted in the eye following the movement. Therefore, even if the response speed of the liquid crystal display is fast, the viewer may blur the display image in the moving image due to the inconsistency between the eye movement and the static image of each frame. In order to prevent this, as shown in FIG. 4, the pixel supplied to the latch 17 during one horizontal period 1 Hsync (that is, the period when the gate is turned on) in which one line of pixel data VD is outputted is shown. The data VD uses impulse driving in which black data is inserted together with image data.

However, such black data only prevents the display image from being blurred in a moving image, and is not data for displaying an actual image, which can be a waste of time in transmission. In other words, although black data is not data representing an actual image, black data is sequentially sampled according to the source sampling clock SSP like image data, and black data is flipped onto a flip-flop. All of them are latched and output at the same time, which can be a waste of time in transmission. In addition, as shown in FIG. 5, after the image data is supplied and before the black data is supplied, the TFT is turned off. In this case, the TFT is turned after maintaining some time. Since the synchronization is off, the black data is supplied to the TFT, and the charging characteristic is lowered, thereby degrading the image quality.

Accordingly, it is an object of the present invention to provide a data driving apparatus and method for a liquid crystal display device capable of preventing image degradation.

In order to achieve the above object, the data driving device of the liquid crystal display according to the embodiment of the present invention includes a shift register section for generating a first sampling signal supplied sequentially and a second sampling signal supplied simultaneously, and a first sampling signal. And a latch unit for sequentially latching and outputting the image data in correspondence to the second data and simultaneously latching and outputting the black data in response to the second sampling signal.

In the data driving device of the liquid crystal display, the first sampling signal is sequentially output by a source start pulse supplied to the shift register unit.

In the data driving device of the liquid crystal display, the second sampling signal may be simultaneously output by the black enable signal supplied to the shift register unit.

In the data driving device of the liquid crystal display, the shift register unit provides a flip-flop for sequentially sampling a source start pulse in response to a source sampling clock, and a path of the first and second sampling signals supplied to the flip-flop. It includes a plurality of shift stages including a path providing unit for.

In the data driving device of the liquid crystal display, the flip-flop is configured to sample the first and second sampling signals corresponding to any one of a source sampling clock supplied to the liquid crystal display and a first and second sampling signals of the source start pulse and the front shift stage. And generating a signal.

In the data driving device of the liquid crystal display, the path providing unit supplies any one of the source start pulse and the black enable signal supplied thereto to the flip-flop connected thereto.

According to an embodiment of the present invention, a data driving method of a liquid crystal display includes supplying one of a source start pulse and a black enable signal to a shift register, and sequentially performing a first sampling signal during a period during which the source start pulse is supplied. Outputting and simultaneously outputting a second sampling signal during a period during which the black enable signal is supplied.

The data driving method of the liquid crystal display device is characterized in that the image data for displaying an image in response to the first sampling signal is sequentially latched.

The data driving method of the liquid crystal display device is characterized in that black data for non-displaying an image corresponding to the second sampling signal is simultaneously latched.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6A to 8.

6A and 6B illustrate the shift register 115 and the latch 117 in detail in the data driving device of the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to FIG. 6A, the shift register 115 according to an exemplary embodiment of the present invention may include a flip-flop 130 and a flip-flop for sequentially sampling a source start pulse SSP in response to a source sampling clock SSC. A plurality of shift stages SST1 to SSTn including a path providing unit 132 for providing a path of a sampling signal supplied to 130 is provided.

The flip-flop 130 generates a sampling signal in response to the source sampling clock SSC and the source start pulse SSP (or the sampling signal) supplied thereto. The path providing unit 132 supplies a source start pulse SSP or a sampling signal supplied to the path provider 132 to the flip-flop 130 to which it is connected.

Meanwhile, the shift register 115 may include the first terminal 140, the second terminal 142, the third terminal 144, the fourth terminal 146, the fifth terminals SP1 to SPn, and the sixth terminal ( 148).

The first terminal 140 determines the shift direction of the shift register 115. For example, when a high signal is input to the first terminal 140, the shift direction of the shift register 115 is set to the right, and in other cases, the shift direction is set to the left. At this time, the shift direction is set to the left by an inverter INT in which the first terminal 140 is connected to the input terminal and the output terminal is connected to the path providing unit 132.

The second terminal 142 receives a source sampling clock (SSC) signal from a signal controller (not shown).

The third terminal 144 receives a source start pulse (SSP) signal from the signal controller when a high signal is input to the first terminal 40, and in other cases, a carry generated from the shift register 115. Supply signal Carry to D-IC of next stage.

The fourth terminal 146 supplies a carry signal Carry generated from the shift register 115 to the next stage D-IC when a high signal is input to the first terminal 140. Receives a source start pulse (SSP) signal from the signal controller.

The fifth terminals SP1 to SPn sequentially supply the sampling signal to the latch 117.

The sixth terminal 148 receives a black enable (BEO) signal from the signal controller.

Here, the sampling signal of the first buffer BF1 and the n-th shift stage SSTn, in which the sampling signal of the first shift stage SST1 is supplied to the input terminal and the output terminal is connected to the third terminal 144. Is supplied to the input terminal, and the role of the third and fourth terminals 144 and 146 is changed by the second buffer BF2 having the output terminal connected to the fourth terminal 146. That is, when a high signal is input to the first terminal 140, the first buffer BF1 does not operate and the second buffer BF2 operates so that the third terminal 144 starts the source. The pulse SSP is supplied to the first shift stage SST1, and the fourth terminal 146 receives a carry signal from the n th shift stage SSTn. When the low signal is input to the first terminal 140, the first buffer BF1 operates and the second buffer BF2 does not operate. The carry signal is input from the shift stage SSTn, and the fourth terminal 146 supplies the source start pulse SSP to the first shift stage SST1.

In addition, the shift register 115 may supply the source start pulse SSP to the first shift stage SST1 or the n th shift stage SSTn according to the shift direction of the shift register. And a second AND gate AND2.

In the first AND gate AND1, the output of the first terminal 140 and the output of the third terminal 144 are supplied as input terminals, and the output terminal is supplied to the first shift stage SST1. The first AND gate AND1 receives the data of "1" from the first terminal 40 and the source start pulse SSP having the data of "1" supplied from the third terminal 144. 1 " is output to supply the source start pulse SSP to the first shift stage SST1. At this time, the shift register 115 shifts to the right from the first shift stage SST1. On the other hand, the first AND gate AND1 does not supply the source start pulse SSP to the first shift stage SST1 unless the first terminal 140 receives the data of “1” from the first terminal 140.

In the second AND gate AND2, the output of the inverter INT and the output of the fourth terminal 146 are supplied to the input terminal, and the output terminal is supplied to the nth shift stage SSTn. When the data of " 0 " is input to the first terminal 140, the second AND gate AND2 receives data of " 1 " by the inverter INT and " 1 " supplied from the fourth terminal 146. "1" is output by the source start pulse SSP having the data of "", and the source start pulse SSP is supplied to the nth shift stage SSTn. At this time, the shift register 115 shifts to the left from the n th shift stage SSTn. On the other hand, the second AND gate AND2 does not supply the source start pulse SSP to the nth shift stage SSTn unless the data of "1" is supplied from the inverter INT.

On the other hand, the i (i is a natural number) th shift stage (SSTi) path providing unit 132 is connected to the third terminal 144 or the fourth terminal 146 where one terminal outputs the source start pulse (SSP). The third AND gate AND3 and one terminal connected to the i-th fifth terminal SPi-1, the other terminal connected to the first terminal 140, and one terminal connected to the inverter INT. A fourth AND gate AND4 having the other terminal connected to the fifth terminal SPi + 1 of the i + 1th shift stage SSTi + 1, and an input terminal of the third AND gate AND3 and the first terminal; The OR gate is connected to the 4 AND gate AND4 and the output terminal is connected to the input terminal of the flip-flop 130.

The third AND gate AND3 receives the source start pulse SSP having the data of "1" from the third terminal 144 when the shift register 115 shifts to the right, or the "5" terminal AND3 from the fifth terminal SP. When the sampling signal of the previous stage having the data of 1 "is supplied and the data of" 1 "is supplied from the first terminal 140, the data of" 1 "is output.

The fourth AND gate AND4 receives the source start pulse SSP having data of "1" from the fourth terminal 146 when the shift register 115 shifts to the left, or the fifth terminals SP1 to SPn. When the sampling signal of the previous stage having the data of "1" is supplied from &lt; RTI ID = 0.0 &gt; 1, &lt; / RTI &gt; and the data of &quot; 1 &quot;

The OR gate OR receives one of the outputs of the third and gate AND3, the fourth and gate AND4, and the sixth terminal 148 to supply the flip-flop 30.

Herein, the operation of the shift stage will be described in detail. First, the source sampling clock SSC and the source start pulse SSP are input from the signal controller 10. At this time, it is assumed that the shift direction of the shift register 115 is set to the right. The source sampling clock SSC input from the signal controller 10 is input to the clock terminal of the flip-flop 130 included in the first shift stage SST1. The source start pulse SSP input from the signal controller is supplied to one terminal of the first AND gate AND1. Here, because the data of "1" is supplied to the other terminal of the first AND gate AND1 (that is, shifted to the right), the first AND gate AND1 shifts the data of "1" to the first shift. It is supplied to the path controller 132 included in the stage SST1.

In fact, the data of "1" supplied from the first AND gate AND1 is input to one terminal of the third AND gate AND3. At this time, since the data of " 1 " of the first terminal 140 is input to the other terminal of the third AND gate AND3, the third AND gate AND3 receives the data of " 1 " Will output The OR gate OR, which receives data of “1” from the third AND gate AND3, supplies a data signal of “1” to an input terminal of the flip-flop 130.

The source sampling clock SSC signal input to the second terminal 142 is supplied to the flip-flop 130 of the first shift stage SST1. At this time, since the data "1" is input to the input terminal of the flip-flop 130 of the first shift stage SST1, the flip-flop 30 of the first stage ST1 removes the data of "1". Outputs to the first fifth terminal SP1 terminal. Here, the sampling signal of "1" output to the first fifth terminal SP1 is input to the path controller 132 of the second shift stage SST2.

The sampling signal of "1" input to the path control unit 132 of the second shift stage SST2 is input to one terminal of the third AND gate AND3. At this time, since the data of " 1 " of the first terminal 140 is input to the other terminal of the third AND gate AND3, the third AND gate AND3 receives the data of " 1 " Will output The OR gate OR, which receives data of “1” from the third AND gate AND3, supplies a data signal of “1” to an input terminal of the flip-flop 130.

Meanwhile, the source sampling clock SSC signal input to the second terminal 142 is supplied to the flip-flop 130 of the second shift stage SST2. At this time, since the data "1" is input to the input terminal of the flip-flop 130 of the second shift stage SST2, the flip-flop 130 of the second shift stage SST2 is the data of "1". Is output to the second fifth terminal SP2 terminal. Here, the sampling signal of "1" output to the second fifth terminal SP2 is input to the path controller 132 of the third shift stage SST3.

In practice, the shift register 115 repeats this operation and sequentially supplies the sampling signal (that is, data of "1") to the first fifth terminal SP1 to the nth fifth terminal SPn.

Thereafter, a black enable BOE signal is input from the signal controller to the or gate OR of each shift stage. The black enable signal generates a sampling signal for supplying black data after supplying image data. Here, since black data is continuously transmitted with the same value (00000000 or 11111111), sampling for supplying black data by supplying a BOE signal when supplying black data The signal is supplied to the latch 117 at the same time.

Referring to FIG. 6B, the latch 117 includes a first flip-flop 150 and a first flip-flop 150 for sequentially outputting latched data according to a sampling signal sequentially sampled by the shift register 115. The second flip-flop 152 and the data inversion selection signal REV which sequentially latch data outputted from the N-th output signal and simultaneously output n pixel data latched in correspondence to the source output enable signal SOE. A plurality of latch stages RST1 to RSTn including a multiplexer 154 for restoring, time-dividing and outputting the modulated pixel data VD so as to reduce the number of transition bits.

The first flip-flop 150 supplies the pixel data VD latched to the second flip-flop 152 in response to the sampling signal and the pixel data VD supplied to the first flip-flop 150. The second flip-flop 152 latches n pixel data VDs supplied to the second flip-flop 152 and simultaneously supplies them to the multiplexer 154 in response to the source output enable signal SOE. The multiplexer 154 restores and time-divisions the pixel data VD modulated to reduce the number of transition bits in response to the data inversion selection signal REV supplied from the signal controller.

The latch 117 includes a sixth terminal 160, a seventh terminal 162, and an eighth terminal 164.

The sixth terminal 160 receives n pixel data VDs from the signal controller. The seventh terminal 162 receives a source output enable signal SOE for simultaneously outputting the n pixel data VD latched from the signal controller. The eighth terminal 164 receives a data inversion selection signal REV for restoring the pixel data VD modulated to reduce the number of transition bits from the signal controller.

On the other hand, the pixel data VD is divided into image data for displaying an actual image and black data for preventing the display image from being blurred in a moving image. The black data does not display the actual image here.

Here, the operation of the latch stage will be described in detail. First, the sampling signal output from the shift register 115 is input, and image data of the pixel data VD is input from the signal controller. The sampling signal output from the shift register 115 is input to the clock terminal of the first flip-flop 150 included in the first latch stage RST1. Image data of the pixel data VD input from the signal controller is supplied to an input terminal of the first flip-flop 150 included in the first latch stage RST1. Then, the second flip including the image data among the pixel data VD latched in the first flip flop 150 included in the first latch stage RST1 is included in the first latch stage RST1. The new image data of the pixel data VD is latched to the first flip-flop 150 which is supplied to the input terminal of the flop 152 and included in the first latch stage RST1. Thereafter, the sampling signal output from the shift register 115 is input to the clock terminal of the first flip-flop 150 included in the second latch stage RST2. Image data of the pixel data VD input from the signal controller is supplied to an input terminal of the first flip-flop 150 included in the second latch stage RST2. Then, the second flip including the image data among the pixel data VD latched in the first flip flop 150 included in the second latch stage RST2 is included in the second latch stage RST2. New image data of the pixel data VD is latched to the first flip-flop 150 which is supplied to the input terminal of the flop 152 and included in the second latch stage RST2.

In fact, the latch 117 receives the sampling signal sequentially from the shift register 115 and the image of the pixel data VD latched in the first flip-flop 150 included in each latch stage RST1 to RSTn. Image data is sequentially latched to the second flip-flop 152 included in each of the latch stages RST1 to RSTn. That is, the first to n-th latch stages RST1 to RSTn-1 until the image data of the pixel data VD is latched on the second flip-flop 152 of the last latch stage RSTn. ), The image data of the pixel data VD is latched in the second flip-flop 152 included in.

Thereafter, a source output enable (SOE) signal is input from the signal controller to the clock terminal of the second flip-flop 152. Accordingly, image data of all the pixel data VDs of one line latched in the second flip-flop 152 is simultaneously output to the multiplexer 154. At this time, in response to the data inversion selection signal REV input from the signal controller to the multiplexer 154, the image data of the pixel data VD modulated so that the number of transition bits is enjoyed is time-divisionally outputted. do.

Thereafter, a sampling signal sampled simultaneously from the shift register 115 is inputted by the black enable BOE signal, and black data of the pixel data VD is input from the signal controller. The sampling signal output from the shift register 115 is simultaneously input to the clock terminals of the first flip-flop 150 included in all the latch stages RST1 to RSTn. Black data of the pixel data VD input from the signal controller is supplied to the input terminal of the first flip-flop 150 included in all the latch stages RST1 to RSTn. Then, the second flip including black data among the pixel data VD latched in the first flip-flop 150 included in all the latch stages RST1 to RSTn is included in all the latch stages RST1 to RSTn. It is supplied to the input terminal of the flop 152.

Thereafter, the source output enable signal SOE is input from the signal controller to the clock terminal of the second flip-flop 152 included in all the latch stages RST1 to RSTn. Accordingly, black data of all pixel data VDs of one line latched in the second flip-flop 152 is simultaneously output to the multiplexer 154. At this time, the black data of the modulated pixel data VD is reduced and time-divided so as to reduce the number of transition bits in response to the data inversion selection signal REV input from the signal controller to the multiplexer 154. .

Therefore, since black data that does not display an actual image can be output during one clock, the transmission time of black data can be reduced as shown in FIG. The longer the time it can be supplied, the better the image quality can be.

In addition, as shown in FIG. 8, after the image data of the pixel data VD is supplied, the data is not supplied for a predetermined period A, and then black data is supplied to thereby charge the TFT. Image quality can be improved by improving Charging).

In detail, the TFT is turned off after the image data is supplied and before the black data is supplied, since the TFT is turned off after maintaining a certain time. Since the black data is supplied to the TFT due to mismatch, the charging characteristic is deteriorated, thereby degrading the image quality. Accordingly, since the data is not supplied during the time that the TFT is turned off, even if black data is supplied later, the TFT does not affect the image quality, thereby preventing the image quality from being lowered.

As described above, the data driving device and method of the liquid crystal display according to the present invention supply the black enable signal to the shift register to simultaneously output black data that does not display an actual image during one clock, thereby outputting black data. By reducing the time can be prevented from deteriorating the image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A data driving device of a liquid crystal display device driven using pixel data including image data and black data, A shift for generating first sampling signals by a source start pulse, sequentially supplying the first sampling signals to a latch unit, and generating second sampling signals by a black enable signal and simultaneously supplying the second sampling signals to the latch unit. Register section, And a latch unit for sequentially latching and simultaneously outputting the image data corresponding to the first sampling signals and simultaneously latching and outputting the black data corresponding to the second sampling signals. Data drive of the device. delete delete The method of claim 1, The shift register unit includes a plurality of flip flops for sequentially sampling a source start pulse in response to a source sampling clock, and a path providing unit for providing paths of the first and second sampling signals supplied to the flip flops. A data driving device of a liquid crystal display device comprising a shift stage. The method of claim 4, wherein The flip-flop generates the first and second sampling signals in response to a source sampling clock supplied to the flip flop and any one of the first and second sampling signals of the source start pulse and the front shift stage. Data drive device of display device. The method of claim 4, wherein And the path providing unit supplies one of the source start pulse and the black enable signal supplied thereto to the flip-flop connected thereto. Supplying one of a source start pulse and a black enable signal to the shift register; Sequentially outputting a first sampling signal during a period during which the source start pulse is supplied; And simultaneously outputting a second sampling signal during the period in which the black enable signal is supplied. The method of claim 7, wherein And image data displaying an image in response to the first sampling signal is sequentially latched. The method of claim 7, wherein And black data for non-displaying an image corresponding to the second sampling signal are simultaneously latched.

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