KR100537631B1 - Driving method of plasma display panel - Google Patents

Abstract

The present invention includes a barrier rib formed with a dielectric and defining discharge cells together with a first substrate and a second substrate opposite thereto; Common-address electrode lines disposed in the first partition wall to surround the discharge cells and extending across the discharge cells; Scan electrode lines spaced apart from the common-address electrode lines in the partition wall to surround the discharge cells, and extended to cross the common-address electrode lines in each discharge cell; A phosphor layer disposed in the discharge cell; And a discharge gas in the discharge cell. In the reset period, a first initialization discharge by applying a ramp-up pulse to the scan electrode lines and a second initialization discharge by applying a ramp-down pulse to the scan electrode lines. In the address period, scan low-level scan pulses are sequentially applied to the plurality of scan electrode lines maintaining the scan high level, and to the common-address electrode lines crossing the scan electrode lines to which the scan pulses are applied. Optionally, a display data signal is applied, alternating sustain pulses are applied to scan electrode lines in a sustain discharge period, and ramp-down pulses are applied to the scan electrode lines in a reset period, when the common-address electrode lines are applied. Is applied to the bias voltage, and the voltage magnitude Vnf of the lowest voltage of the ramp-down pulse is Provides a method of driving a plasma display panel, it characterized in that the same size and voltage (Vs) of the sustain pulse groups alternately.

Description

Driving method of plasma display panel {Driving Method of plasma display panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel and a driving method thereof, and more particularly, to a plasma display panel having improved light emission efficiency and reduced permanent image retention, and a driving method of the plasma display panel.

The device employing the plasma display panel has a large screen, high quality, ultra-thin, light weight, and excellent characteristics of wide viewing angle, and is simpler to manufacture than other flat panel display devices and is easy to be enlarged. It has been in the spotlight as a flat panel display device.

The plasma display panel may be classified into a direct current (DC) type, an alternating current (AC) type, and a hybrid type according to an applied discharge voltage, and may be classified into a counter discharge type and a surface discharge type according to a discharge structure.

Initially, research on two-electrode opposing discharge plasma display panels has been actively conducted. However, in the plasma display panel, a discharge is generated between the first substrate and the second substrate on which the phosphor layer is applied, so that deterioration of the phosphor layer by ion sputtering occurs very seriously. In order to overcome this problem, an AC plasma display panel having an AC three-electrode surface discharge structure has recently been generally adopted.

FIG. 1 is a perspective view showing the structure of a conventional three-electrode surface discharge plasma display panel 1, and FIG. 2 is a block diagram of the plasma display apparatus 100 including the plasma display panel 1 of FIG. . 1 and 2, between the first and second substrates 10 and 13 of a conventional three-electrode surface discharge plasma display panel 1, common-address electrode lines A _R1,. A _Bm ), dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor layer 16, partition wall (17) and MgO layer 12 as a protective layer are provided.

The common-address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the second substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . The barrier ribs 17 are formed in the direction parallel to the address electrode lines A _R1 ,..., And A _Bm in front of the first dielectric layer 15. These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The phosphor layer 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) intersect the address electrode lines (A _R1 , ..., A _Bm ). It is formed in a constant pattern on the back of the front glass substrate 10. Each intersection sets a corresponding discharge cell. The second dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, an MgO layer, is formed by applying the entire surface to the back of the second dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In addition, the plasma display apparatus 100 includes an image processor 56, a logic controller 62, an address driver 3, an X driver 4, and a Y driver 5. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 56. The address driver 3, the X driver 4, and the Y driver 5 respectively include the address signals S _A , X from the driving control signals S _A , S _Y , and S _X from the logic controller 62. The driving control signal S _X and the Y driving control signal S _Y are processed and applied to the Y electrode lines.

3 illustrates driving signals applied to electrodes of the plasma display panel in each unit subfield according to a waveform diagram illustrating the plasma display panel driving signal. The conventional resetting method included in the driving method of FIG. 3 is taught in Japanese Laid-Open Patent Publications No. 214,823 and No. 242,224.

Referring to FIG. 3, in the rising period of the resetting time PR of the unit subfield SF, the potential increases from the Y electrodes X ₁ ,..., X _n to the second potential V _T1 . The voltage is continuously raised to the first potential V _T1 + V _{SET which} is higher by the fifth potential V _SET than the next second potential V _T1 . Here, the ground potential V _G is applied to the X electrodes X ₁ ,..., X _n and the address electrodes A ₁ ..., A _m . Accordingly, a weak discharge occurs between the Y electrodes and the X electrodes, while a weaker discharge occurs between the Y electrodes and the address electrodes. As a result, many negative wall charges are formed around the Y electrodes, positive wall charges are formed around the X electrodes, and less positive wall charges are formed around the address electrodes.

In the falling period of the reset time PR, while the potential applied to the X electrodes is maintained at the bias potential Ve, the potential applied to the Y electrodes is changed from the third potential V _T2 to the fourth potential ( V _nf ) is continuously lowered. Here, the ground potential V _G is applied to the address electrodes. Thus, due to the weak discharge between the X electrodes and the Y electrodes, some of the negative wall charges around the Y electrodes move around the X electrodes. Accordingly, the wall electric-potential of the X electrodes X ₁ ,..., X _n is lower than the wall potential of the address electrodes and higher than the wall potential of the Y electrodes. Accordingly, the addressing voltage V _A -V _SC-L required for the counter discharge between the selected address electrodes and the Y electrode line in the subsequent addressing period PA may be lowered. Meanwhile, since the ground potential V _G is applied to all the address electrodes, the address electrodes discharge the X electrodes and the Y electrodes, and the positive wall charges around the address electrodes disappear due to the discharge. .

In the subsequent addressing period PA, in the state in which the bias voltage Ve is applied to the X electrodes, the display data signal is applied to the address electrodes, and the sixth potential V _{SC− which} is lower than the second potential V _T1 . _As the scan pulses of the low level potential V _SC-L are sequentially applied to the Y electrodes biased with _H ), smooth addressing may be performed. As for the display data signal applied to each address electrode, the positive addressing potential V _A is applied when the display cell is selected, and the ground potential V _G is applied when the display cell is not selected. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the low level potential V _SC-L is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges are not formed in the display cell.

In the subsequent sustain discharge period PS, sustain pulses of the sustain voltage V _S are alternately applied to all the Y electrodes and the X electrodes so that the display cells are formed in the display cells in which the wall charges are formed at the corresponding addressing time PA. It causes a discharge for maintenance.

Meanwhile, even in the case of the plasma display panel 1, due to the structure in which electrode lines, the second dielectric layer 11, and the protective layer 12 are sequentially formed from the lower side of the first substrate 10, the phosphor layer is formed. As the visible light emitted from (16) is absorbed by approximately 40%, there is a limit in increasing the luminous efficiency. In the case where the same image is displayed for a long time, the charged particles of the discharge gas are discharged from the phosphor layer ( 16) there is a problem that the ion sputtering (ion sputtering) causes a permanent afterimage to shorten the life. In addition, since three driving units for driving the plasma display panel 1, that is, the X driving unit 4, the Y driving unit 5, and the address driving unit 3 are required, the overall structure becomes complicated, so that the driving apparatus and power supply circuit There is a problem in that the manufacturing cost of is high.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a plasma display panel having improved light emission efficiency and reduced permanent image retention, and a method of driving the plasma display panel.

Another object of the present invention is to reduce the manufacturing cost of the panel driving circuit by simplifying the type of power level applied to the plasma display panel.

The present invention devised to achieve the above and other objects, the present invention is a method for driving a plasma display panel by a drive waveform consisting of a reset period, an address period, and a sustain discharge period,

The plasma display panel includes: a barrier rib formed with a dielectric and defining discharge cells together with a transparent first substrate and a second substrate opposite thereto; Common-address electrode lines disposed in the first partition wall to surround the discharge cells and extending across the discharge cells; Scan electrode lines spaced apart from the common-address electrode lines in the partition wall to surround the discharge cell, and extended to cross the common-address electrode lines in each discharge cell; A phosphor layer disposed in the discharge cell; And a discharge gas in the discharge cell;

The driving method,

In the reset period, a first initialization discharge by applying a ramp-up pulse and a second initialization discharge by applying a ramp-down pulse to the scan electrode lines,

In the address period, a scan pulse of scan low level V _SC-L is sequentially applied to the plurality of scan electrode lines maintaining scan high level V _{SC -H} , and a scan to which the scan pulse is applied A display data signal is selectively applied to the common-address electrode lines crossing the electrode lines.

In the sustain discharge period, alternate sustain pulses are applied to the scan electrode lines,

In the reset period, when a rampdown pulse is applied to the scan electrode lines, a bias voltage Vx is applied to the common-address electrode lines, and the voltage magnitude Vnf2 of the lowest voltage of the rampdown pulse is maintained. A method of driving a plasma display panel is provided which is equal to the voltage magnitude Vs of the alternating sustain pulses in a discharge period.

In addition, the discharge cell of the plasma display panel has a sum of a wall voltage due to wall charge accumulated in the partition wall and a voltage difference between signals applied to the common-address electrode and the scan electrode. Strong discharge occurs when Vf) is exceeded,

The natural discharge start voltage of the reset period, the natural discharge start voltage of the address discharge period, and the natural discharge start voltage of the sustain discharge period are the same.

In the sustain discharge period, the voltage size Vs of the alternate sustain pulses applied to the scan electrode lines is preferably greater than half of the intrinsic discharge start voltage Vf.

The ramp-down pulse applied to the scan electrode in the reset period preferably has a slope at which the second initialization discharge occurs while maintaining the wall voltage higher than the voltage of the ramp-down pulse by the natural discharge start voltage.

According to another feature of the present invention, after the application of the rampdown pulse is completed, the reset wall voltage Vw higher than the lowest voltage of the rampdown pulse in the discharge cell by the intrinsic discharge start voltage Vf. ) Is maintained.

Further, according to another feature of the present invention, the magnitude of the wall voltage Vw after the reset in the discharge cell is formed to be smaller than half of the intrinsic discharge starting voltage Vf.

According to still another aspect of the present invention, the sum of the post-reset wall voltage Vw and the voltage magnitude Vs of the alternate sustain pulse in the discharge cell is smaller than the intrinsic discharge start voltage Vf.

Preferably, the common-address electrode lines and the scan electrode lines of the plasma display panel may be formed of a conductive electrode and have a ladder shape extending in one direction.

On the other hand, the method of driving the plasma display panel may be stored as a program in a recording medium on which a program for execution in a computer is stored and then called and executed by the central processing unit.

Next, the preferred embodiment of the present invention will be described in detail with reference to FIGS. 4 to 12.

As shown in FIGS. 4 to 7, the plasma display panel 200 according to an exemplary embodiment of the present invention may include a transparent first substrate 201 and a second substrate disposed to face the first substrate 201. 202 and between the first substrate 201 and the second substrate 202 and together with the first substrate 201 and the second substrate 202 define the discharge cells 220 and formed of a dielectric material. Common-address electrode lines A ₁ ,... Disposed in the first partition 205 so as to surround the discharge cell 220 and extending across the discharge cells 220. A _n ) and spaced apart from the common-address electrode lines A ₁ ,..., A _{n in} the first partition 205 so as to surround the discharge cell 220, and each discharge cell 220. Scan electrode lines S ₁ , ..., S _m extending to intersect the common-address electrode lines A ₁ , ..., A _n , and a phosphor layer disposed in the discharge cell 220. And a discharge gas in the discharge cell 220.

The transparent first substrate 201 is made of a material having good light transmittance such as glass. In the first substrate 201, since the electrode lines X ₁ , ..., X _n (Y ₁ , ..., Y _n ) that existed on the front substrate of the conventional plasma display panel do not exist, The front transmittance of visible light is remarkably improved. Therefore, if the image is realized with the luminance of the conventional level, the electrode lines X ₁ , ..., X _n ) (Y ₁ , ..., Y _n ) are driven at a relatively low voltage, thus the luminous efficiency is reduced. Is improved.

The second substrate 202 is disposed parallel to the first substrate 201 and is usually made of a material mainly composed of glass.

A first partition 205 is disposed between the second substrate 202 and the first substrate 201 to define the plurality of discharge cells 220 together with the substrates 201 and 202. The first partition 205 partitions the discharge cells 220 corresponding to one of the red light emitting pixel, the green light emitting subpixel, and the blue light emitting subpixel constituting one pixel, and the discharge cells 220 Prevent the liver from discharging.

The first partition wall 205 prevents the common-address electrode lines A ₁ ,..., A _n and the scan electrode lines S ₁ ,..., S _m from being directly energized during discharge. It prevents the charged particles from directly colliding with the electrodes and damages them, and is formed as a dielectric that can induce charged particles to accumulate wall charges. Such dielectrics include PbO, B ₂ O ₃ , and SiO ₂ . .

In the first partition 205, common-address electrode lines A ₁ ,..., A _n and scan electrode lines S ₁ , ..., S _m surrounding the discharge cell 220 are formed. The electrode lines are arranged to be spaced apart from each other in a vertical direction, and the electrode lines are formed of a conductive metal such as aluminum, copper, or the like. The common-address electrode lines A ₁ ,..., And A _n serve as common and address electrodes, and the scan electrode lines S ₁ , ..., S _m serve as scan electrodes.

In addition, the common-address electrode lines A ₁ , ..., A _n and the scan electrode lines S ₁ , ..., S _m have a ladder shape extending in one direction.

At least the side surfaces of the first partition wall 205 are preferably covered by the MgO film 209 as the protective film 209. Although the MgO film 209 is not an essential component, it prevents the charged particles from colliding with the first barrier rib 205 formed of the dielectric material and damaging the first barrier rib 205 and emitting a large amount of secondary electrons upon discharge. .

The plasma display panel 200 according to the present invention is disposed between the first partition wall 205 and the back substrate 202, and the second partition wall 208 defining the discharge cells 220 together with the first partition wall 205. ) May be further provided. In FIG. 4, the second partition 208 is partitioned into a matrix, but the present invention is not limited thereto. For example, the barrier ribs of various patterns may be formed into closed partitions such as waffles, matrices, deltas, and the like. Can be. In addition, the closed partition wall may be formed such that the cross section of the discharge space becomes a polygon such as a triangle, a pentagon, or a circle, an ellipse, or the like, in addition to the quadrangle as in the present embodiment. As shown in FIG. 4, the first partition 205 and the second partition 208 may be formed to have the same shape, but may be formed to have different shapes.

As shown in FIG. 5, the phosphor layer 210 is formed at the same level as the second partition wall 208, and is preferably disposed between the side surfaces of the second partition wall 208 and the second partition walls 208. It is applied on the second substrate 202.

The phosphor layer 210 has a component for generating visible light by receiving ultraviolet rays. The phosphor layer formed on the red light emitting subpixel includes phosphors such as Y (V, P) O ₄ : Eu, and the like. The formed phosphor layer includes phosphors such as Zn ₂ SiO ₄ : Mn, YBO ₃ : Tb, and the like, and the phosphor layer formed on the blue light emitting subpixel includes phosphors such as BAM: Eu.

The discharge cell 220 is filled with a discharge gas such as Ne, Xe, and the like and a mixed gas thereof. In the case of the present invention including this embodiment, the discharge surface can be increased and the discharge region can be enlarged, so that the amount of plasma formed is increased, thereby enabling low voltage driving. Therefore, in the case of the present invention, even when a high concentration of Xe gas is used as the discharge gas, low voltage driving is possible, thereby significantly improving the luminous efficiency. This solves the problem of low voltage driving when using a high concentration of Xe gas as a discharge gas in a conventional plasma display panel.

Meanwhile, the common-address electrode lines and the scan electrode lines may be formed of conductive electrodes and have a ladder shape extending in one direction. For example, FIG. 6 is a layout view showing the arrangement of common-address electrode lines A1 to An taken along the line V-V of FIG. 5, and has a ladder shape extending in one direction. For example, FIG. 7 is a layout view showing the arrangement of the scan electrode lines S1 to Sm taken along the VI-VI line of FIG. 5, and has a ladder shape extending in one direction.

As illustrated in FIG. 8, the plasma display apparatus 300 according to an exemplary embodiment of the present invention includes the plasma display panel 200, the image processor 156, the logic controller 162, the A driver 154, and the like. S driver 155 is included.

In addition, the plasma display apparatus may further include an image processor 156. The image processing unit 156 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. The logic controller 162 generates the driving control signals S _A and S _S according to the internal image signal from the image processor 156.

The A driver 154 processes the A drive signal S _A among the drive control signals S _A and S _S from the logic controller 162 to generate display data signals, and to generate the display data signals in common. -Applied to the address electrode lines A ₁ , ..., A _n . The S driver 155 processes the S driving control signal S _S among the driving control signals S _A and S _S from the logic controller 162 to scan electrode lines S _{1 ,.} ) Is applied.

In the plasma display apparatus 300 according to the exemplary embodiment of the present invention, since only two driving units, the S driving unit 155 and the A driving unit 154, are required to drive the plasma display panel 200, According to the plasma display apparatus 100, the number of driving units is reduced, thereby simplifying the overall structure.

9 illustrates a driving method in the plasma display device 300 according to an embodiment of the present invention. Referring to the drawings, each unit frame is divided into _eight subfields SF ₁ , SF 8 to realize time division gray scale display. In addition, each subfield SF ₁ , ..., SF ₈ has a reset time R ₁ , ..., R ₈ , an addressing time AD ₁ , ..., AD ₈ , and sustain-discharge It is divided by time (SD ₁ , ..., SD ₈ ).

The discharge conditions of all the display cells are made uniform at each reset time PR ₁ , ..., PR ₈ while being adapted to the addressing to be performed in the next step.

At each addressing time PA ₁ ,..., And PA ₈ , display data signals are applied to the common-address electrode lines A ₁ ,..., And A _n , and each scan electrode lines S ₁ ,. ..., S _m ) are sequentially applied. Accordingly, when high level display data signals are applied while the scan pulse is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

At each sustain-discharge time PS ₁ ,..., PS ₈ , all common-address electrode lines A ₁ , ..., A _n maintain the ground potential V _G and all scan electrodes The sustain-discharge pulses are alternately applied to the lines S ₁ , ..., S _m , so that the sustain discharges are discharged in the discharge cells in which wall charges are formed at the corresponding addressing times PA ₁ , ..., PA ₈ . Causes Therefore, the luminance of the plasma display panel is proportional to the length of the sustain-discharge times PS ₁ ,..., PS ₈ occupied in the unit frame. The length of the sustain-discharge time PS ₁ ,..., PS ₈ occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ is the sustain-discharge time PS ₁ of the first subfield SF ₁ , and the time 1T corresponding to the sustain-discharge time PS ₂ of the second subfield SF ₂ is 2. ^The time 2T corresponding to ¹ is the holding-discharge time PS ₃ of the third subfield SF ₃ , and the time 4T corresponding to 2 ² is the holding of the eighth subfield SF ₈ . In the discharge time PS ₈ , a time 128T corresponding to 2 ⁷ is set. Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

FIG. 10 shows signals applied to electrode lines of the plasma display panel 200 in the unit sub-field SF of FIG. 9. In FIG. 10, reference numerals A1: An denote driving signals applied to the common-address electrode lines, and S1, ..., Sm denote driving signals applied to the respective scan electrode lines.

Referring to the discharging process, the reset period PR initializes the wall charge state of the cell by applying a reset signal to the scan electrode lines S1 to Sm and forcibly performing a write discharge. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. The cells initialized by the reset period PR have similar wall charge conditions inside the cells. In the rising lamps t2 to t3 of the scan electrode lines S1 to Sm during the reset period PR, the first weak discharge occurs and a large amount of negative charges are accumulated on the scan electrode lines S1 to Sm, Positive charges accumulate on the and X electrode lines.

Subsequently, in the falling lamps t3 to t4 of the scan electrode lines S1 to Sm, the voltages of the scan electrode lines S1 to Sm gradually decrease while the second weak discharge occurs, and thus the scan electrode lines S1 to Sm. The negative charge of Sm) is gradually erased and discharged to the discharge space. Due to the weak discharge in the discharge space, the inside of the discharge cell is initialized.

In the reset period PR, the ramp-up pulses t2 to t3 causing the first weak discharge are applied to the Y electrodes Y1 to Yn from a voltage higher than the reference potential by a predetermined voltage V _T1 . In this case, when the ramp-up pulses t2 to t3 start to be applied from a voltage higher than the reference potential by the pulse size Vs of the scan pulse, a circuit for applying the ramp-up pulse in addition to the power supply circuit and the switching circuit used for the scan pulse, The increase in manufacturing costs due to the installation can be reduced. The ramp-down pulses t3 to t4 causing the second weak discharge are applied to the Y electrodes Y1 to Yn from a voltage higher by a predetermined voltage V _T2 than the reference potential. In this case, when the ramp-down pulses t3 to t4 start to be applied from a voltage higher than the reference potential by the pulse size Vs of the scan pulse, the circuit for applying the ramp-down pulse in addition to the power supply circuit and the switching circuit used for the scan pulse are separately provided. The increase in manufacturing costs due to the installation can be reduced.

In the address period PA, while the scan high level V _SC-H is applied to the plurality of Y electrodes, the scan low level V _SC-L lower than the scan high level is applied to each Y electrode. When the pulses are sequentially applied, the address electrodes are turned on at the same time, so that a large amount of negative charge is emitted near the Y electrode and a large amount of positive charge is emitted near the address electrode in the selected display cell, thereby generating a large amount of positive charge near the Y electrode. Piles up and becomes ready for maintenance discharge.

After the address period PA is performed, alternate sustain pulses in which the positive sustain voltage Vs + and the negative sustain voltage Vs− are alternately applied to the scan electrode lines S1 to Sm are performed. The sustain discharge period PS is performed.

At the time when the sustain pulse is applied, positive charges accumulated in the address period are accumulated on the scan electrode lines S1 to Sm and negative charges are accumulated on the common-address electrode lines A1 to An. On the other hand, the scan electrode is being applied to the scan electrode lines S1 to Sm toward the positive sustain voltage Vs + among the alternate sustain pulses composed of the positive sustain voltage Vs + and the negative sustain voltage Vs-. Positive charges accumulated in the lines S1 to Sm are discharged to space charges, and negative charges are also discharged to the space charges in the common-address electrode lines A1 to An, and weak discharge is started by the influence of the space charges. When the voltage Vs + is applied, more positive charges are discharged from the scan electrode lines S1 to Sm, and more negative charges are discharged to the space charges from the common-address electrode lines A1 to An and based on the weak discharge. Fast and strong sustain discharge is performed. The primary sustain discharge is the sum of the positive charges accumulated near the scan electrode lines S1 to Sm and the difference of the negative charges accumulated on the common-address electrode lines A1 to An (ie, all potential values). Sum of absolute values) is exceeding the discharge start voltage. When the primary sustain discharge occurs, negative charges accumulate near the scan electrode lines S1 to Sm, and positive charges accumulate near the X electrode lines.

Subsequently, when the negative sustain voltage Vs- starts to be applied to the scan electrode lines S1 to Sm, the positive charge starts to be discharged to the space charge in the common-address electrode lines A1 to An and the scan electrode lines In S1 to Sm, the negative charge starts to be discharged into the space charge, and when the minimum voltage value Vs- is reached, the secondary sustain discharge is performed. The secondary sustain discharge is obtained by subtracting the sum of the negative charge and the Vs-voltage accumulated near the scan electrode lines S1 to Sm from the potential due to the positive charge accumulated near the common-address electrode lines A1 to An. (Ie, the sum of the absolute values of all potential values) is made while exceeding the discharge start voltage. When the secondary sustain discharge occurs, positive charges are accumulated near the scan electrode lines S1 to Sm, just like the first sustain discharge, and negative charges are accumulated near the X electrode lines. After that, the third sustain discharge occurs by the same action as the first sustain discharge, and then the fourth sustain discharge occurs by the same action as the second sustain discharge. The alternate sustain pulses last for a predetermined time for each subfield, and such sustain discharge is continued.

FIG. 11 is a signal waveform diagram applied to the common-address electrode line Sm of the plasma display panel 200 according to the present invention in a unit sub-field, and is formed by wall charges in on-cell and off-cell. It is a distribution chart showing wall voltages V (ON) and V (OFF).

Hereinafter, according to the feature of the present invention, it is intended to limit the slope and magnitude of the drive signal waveform in consideration of the wall voltage formed by the wall charge.

11 shows a state in which a display data signal having a data voltage Va is applied to the common-address electrode lines A1 to An, and a second waveform diagram is applied to the m th scan electrode line Sm. Shows the signal waveform. Reference numeral V (SA) in the third waveform diagram of FIG. 11 denotes a voltage difference V _S -V _A of a signal applied to the scan electrode and the common-address electrode, and V (ON) denotes the m-th scan electrode line. A display data signal having a data voltage Va is applied to the common-address electrode lines A1 to An intersecting Sm to represent a wall voltage when the corresponding discharge cell is turned on. Reference numeral V (SA) in the fourth waveform diagram of FIG. 11 denotes a voltage difference V _S -V _A of a signal applied to the scan electrode and the common-address electrode, and V (OFF) denotes the m-th scan electrode line. Since the display data signal is not applied to the common-address electrode lines A1 to An crossing the sm, the wall voltage when the corresponding discharge cell is turned off.

In the reset period PR of the present invention, the first initialization discharge and the ramp-down pulses t3 to t4 are applied to the scan electrode lines S1 to Sm by the ramp-up pulses t2 to t3. 2 It goes through initializing discharge. The first initialization discharge is applied to the scan electrode lines S1 to Sm with a ramp-up pulse t2 to t3 having an insignificant slope, so that a weak discharge occurs and at the same time near the scan electrodes (that is, on the scan electrodes). Negative charge is accumulated in the dielectric layer). In order to reduce the time t2 to t3 required for the first initialization discharge, the ramp-up pulse is preferably applied from the second potential V _T1 . Thereafter, the ramp-up pulse rises to the first potential (V _SET + V _T1 ).

In the second initialization discharge, while a ramp-down pulse is applied to the scan electrode lines S1 to Sm, negative charges accumulated near the scan electrode lines S1 to Sm (that is, the dielectric layers on the scan electrodes) are emitted. Weak discharge occurs. In this case, the ramp-down pulses applied to the scan electrode lines S1 to Sm should have an inclined slope that does not cause strong discharge. Specifically, the intrinsic discharge starting voltage Vf is higher than the voltage of the ramp-down pulse. It is preferable to have a slope in which the second initialization discharge occurs while maintaining the wall voltage as high as that will be described later. The ramp-down pulse is preferably applied after the voltage is lowered from the first potential V _SET + V _T1 to the third potential V _T2 to shorten the second initialization discharge periods t3 to t4.

In the address period PA, scan pulses having the scan low level V _SC-L are sequentially applied to the plurality of scan electrode lines S1 to Sm that maintain the scan high level V _SC-H . The display data signal is selectively applied to the common-address electrode lines A1 to An crossing the scan electrode lines S1 to Sm to which the scan pulse is applied. The address discharge is generated in the discharge cells to which the display data signal having the data voltage Va is applied, but the address discharge is not generated in the discharge cells to which the display data signal is not applied.

In the sustain discharge period PS, alternate sustain pulses are applied to the scan electrode lines S1 to Sm. In the address period PA, the discharge cells to which the display data signal having the data voltage Va was applied are turned on due to the address discharge and sustain discharge occurs, but the discharge cells to which the display data signal is not applied are discharged. Does not occur, so it is turned off and no sustain discharge occurs.

On the other hand, in the discharge cell of the plasma display panel 200, strong discharge occurs only when a predetermined threshold voltage is generated between the electrodes in the discharge cell, and the predetermined threshold voltage is referred to as the intrinsic discharge starting voltage Vf. Within the discharge cell, the sum of the wall voltage V (ON) due to the wall charge accumulated in the partition wall and the voltage difference between the signals applied to the common-address electrode and the scan electrode is the intrinsic discharge start voltage (Vf) of the discharge cell. When it exceeds), strong discharge occurs.

However, since one scan signal and one address signal are applied to the unit discharge cell of the plasma display panel 200 according to the present invention, only a voltage difference between two electrodes is a problem. Therefore, in the two-electrode plasma display panel as in the present invention, the intrinsic discharge start voltage of the reset period, the intrinsic discharge start voltage of the address discharge period, and the intrinsic discharge start voltage of the sustain discharge period are the same.

Meanwhile, referring to V (ON) in the third waveform diagram of FIG. 11, in the selected discharge cell, the alternate sustain pulse applied to the scan electrode lines S1 to Sm in the sustain discharge period PS. The voltage size Vs is preferably applied to be greater than half of the natural discharge starting voltage Vf, that is, Vf / 2, for stable sustain discharge generation.

Vs> Vf / 2 ----- (Equation 1)

On the other hand, as already mentioned above, since the ramp-down pulse applied to the scan electrode lines (S1 ~ Sm) has an inclined slope such that strong discharge does not occur, while the ramp-down pulse is applied In the discharge cell, while maintaining the wall voltage higher than the lowest voltage Vnf of the ramp-down pulse by the intrinsic discharge start voltage Vf, the voltage falls with a similar slope.

After the ramp down pulse is applied, the reset wall voltage Vw higher than the lowest voltage Vnf of the ramp down pulse is maintained by the intrinsic discharge starting voltage Vf. After the reset, the wall voltage Vw is maintained even until the sustain discharge period PS when the corresponding discharge cell is not selected (i.e., no address discharge occurs).

Here, the wall voltage immediately after the rampdown pulse is applied, that is, the wall voltage Vw after reset,

Vw = Vf-Vnf ----- (Equation 2)

On the other hand, in the discharge cells not selected, in order to prevent erroneous discharge from occurring during the sustain discharge period due to the wall voltage Vw after the reset, the magnitude of the wall voltage Vw after reset is half of the intrinsic discharge starting voltage Vf. Should be smaller than

Therefore, after reset, the magnitude of the wall voltage Vw,

| Vw | <Vf / 2 ----- (Equation 3)

On the other hand, in the discharge cells that are not selected, the sum of the wall voltage Vw after the reset and the voltage magnitude Vs of the alternate sustain pulse should be smaller than the intrinsic discharge start voltage Vf. therefore,

| Vs | + Vw <Vf ----- (Equation 4)

For example, in the second sustain pulse applied to the unselected discharge cells, erroneous discharge does not occur when Vs + Vw <Vf. In Equation 2, since Vw = Vf-Vnf, and substituting it into Equation 4, Vs + (Vf-Vnf) <Vf.

Therefore, Vnf> Vs ----- (Equation 5)

Is obtained.

Therefore, it can be seen that the voltage size Vnf of the minimum voltage of the ramp-down pulse in the reset period PR is preferably larger than the voltage size Vs of the alternate sustain pulse in the sustain discharge period PS.

However, since the voltage magnitude Vnf of the minimum voltage of the ramp-down pulse in the reset period PR is a high voltage, not only does it increase the manufacturing cost of the driving circuit, but also causes the occurrence of electromagnetic interference.

Therefore, it is desirable to reduce the voltage magnitude Vnf of the lowest voltage of the ramp-down pulse in the reset period PR while maintaining the voltage difference V _S -V _A of the signal applied to the scan electrode and the common-address electrode. Do.

Therefore, as shown in FIG. 12, in the method of driving the plasma display panel according to the present invention, when the ramp down pulses t3 to t4 are applied, the ramp down is applied by applying the bias voltage Vx to the common-address electrode lines. The voltage magnitude (Vnf) of the lowest voltage of the pulse can be reduced.

In addition, when the ramp-down pulses t3 to t4 are applied, when the reset bias voltage Vx is applied to the common-address electrode lines, positive charges are emitted from the common-address electrode lines to scan electrode lines S1. The second weak discharge can be performed smoothly by acting with the negative charge emitted from ~ Sm).

In particular, in the driving method of the plasma display panel according to the present invention, the magnitude of the bias voltage Vx applied to the common-address electrode lines A1 to An is the voltage magnitude Vnf of the lowest voltage of the ramp-down pulse. And the voltage magnitude (Vs) of the alternate sustain pulse in the sustain discharge period is driven to have the same size. Therefore, since the power supply circuit required for the manufacture of the scan driving circuit is simplified, the manufacturing cost can be reduced.

In the waveform diagram shown in FIG. 12, the voltage magnitude of the lowest voltage of the rampdown pulse is Vs, where the lowest voltage Vs of the rampdown pulse applied to the scan electrode lines S1 to Sm and the common-address electrode lines. The voltage difference Vs-Vx between the bias voltages Vx applied to A1 to An is the same as Vnf when driven by the waveform diagram of FIG. Accordingly, as can be seen in the third and fourth waveform diagrams of FIG. 11, at the time when the lowest voltage of the ramp-down pulse is applied, the voltage difference V (SA) of the signal applied to the scan electrode and the common-address electrode. Is the same as Vnf.

Therefore, when the bias voltage Vx is applied to the common-address electrode lines A1 to An, the lowest voltage of the ramp-down pulse applied to the scan electrode lines S1 to Sm is Vnf2.

Equation 5 is modified to Vnf2 = Vs ----- (Equation 5 '),

Vnf = Vnf2-Vx = Vs-Vx, and the magnitude of Vnf identified in FIG. 11 is

| Vnf | = | Vs | + | Vx | ----- (Equation 6)

Becomes

Meanwhile, the display panel driving method according to the present invention described above may be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage, and the like. Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Thus, the term computer is used to mean all devices having an information processing capability for performing a specific function by a program, including a memory, an input / output device, and an arithmetic device, regardless of the name actually used. Even in the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the display panel driving method according to the present invention is an integrated circuit, for example, a field programmable gate array (FPGA), which is prepared by a schematic or ultra high-speed integrated circuit hardware description language (VHDL) on a computer, and connected to a computer. It can be implemented by. The recording medium includes such a programmable integrated circuit.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the plasma display panel and the driving method thereof according to the present invention have the following effects.

First, according to the plasma display panel and its driving method of the present invention, first, since the sustain discharge is made only at the portion defined by the partition wall, ion sputtering of the phosphor by the charged particles, which is a problem of the conventional plasma display panel, is prevented, Therefore, even after displaying the same image for a long time, there is no permanent afterimage.

Second, since the surface discharge can be generated in all aspects forming the discharge space, the discharge area can be greatly enlarged.

Third, since the discharge is generated in terms of forming the discharge cell and diffused to the center portion of the discharge cell, the discharge area is remarkably improved compared to the conventional one, so that the entire discharge cell can be efficiently used. Therefore, the driving can be performed even at a low voltage, thereby significantly improving the luminous efficiency.

Fourth, the plasma display panel of the present invention and the driving apparatus for performing the driving method require only the scan driver for driving the scan electrode lines and the address driver for driving the common-address electrode lines. There is no need to provide the X driver and the address driver separately. Therefore, there is an effect that the manufacturing cost of the drive device is significantly reduced.

Fifth, the kind of power supply level applied to the plasma display panel is simplified by making the magnitude of the voltage Vs of the sustain pulse and the minimum voltage Vnf2 of the ramp-down pulse the same. Therefore, the manufacturing cost of the driving circuit of the plasma display panel is reduced.

The invention is not limited to the examples described above and represented in the drawings. Those skilled in the art taught by the above-described embodiments, many modifications to the above-described embodiments are possible by substitution, erasure, merging, etc. within the scope and object of the present invention described in the following claims.

1 is a perspective view showing the internal structure of a three-electrode surface discharge plasma display panel according to the prior art.

FIG. 2 is a block diagram illustrating a plasma display device including the plasma display panel of FIG. 1.

3 is a waveform diagram illustrating a waveform of a signal for driving the plasma display panel of FIG. 1.

4 is a partial cutaway perspective view illustrating a plasma display panel according to an embodiment of the present invention;

5 is a cross-sectional view taken along line IV-IV of FIG. 5,

FIG. 6 is a layout view illustrating the arrangement of common-address electrode lines A1 to An taken along the line VV of FIG. 5;

FIG. 7 is a layout view illustrating an arrangement of scan electrode lines S1 to Sm taken along the VI-VI line of FIG. 5.

FIG. 8 is a block diagram illustrating a plasma display device including the plasma display panel of FIG. 4.

9 is a timing diagram illustrating a driving method in a plasma display device according to an embodiment of the present invention.

FIG. 10 is a waveform diagram of signals applied to electrode lines of the plasma display panel of FIG. 4 in a unit sub-field of FIG. 9.

FIG. 11 is a waveform diagram illustrating waveforms of signals applied to electrode lines of a plasma display panel in a unit sub-field and wall voltages formed by wall charges in on-cells and off-cells.

12 is a waveform diagram illustrating waveforms of signals applied to electrode lines of a plasma display panel in a unit sub-field and wall voltages formed by wall charges in on-cells and off-cells.

Explanation of symbols on the main parts of the drawings

200: plasma display panel 201: front substrate

202: rear substrate 205: first bulkhead

208: second bulkhead 209: protective film

210: phosphor layer 220: discharge cell

300: plasma display device

A ₁ , ..., A _n: common-address electrode lines

S ₁ , ..., S _m : scan electrode lines

Vnf, Vnf2: voltage level of the minimum voltage of the rampdown pulse

Vf: Intrinsic Discharge Starting Voltage

Vs: voltage of sustain pulse

V _SC-H : Scan High Level Voltage

V _SC-L : Scan Low-Level Voltage

V (S-A): Voltage difference between the signal applied to the scan electrode and the common-address electrode

V (ON): Wall voltage when the discharge cell is on

V (OFF): Wall voltage when the discharge cell is off

Vx: Reset bias voltage

Claims (8)

A method of driving a plasma display panel by a drive waveform consisting of a reset period, an address period, and a sustain discharge period, The plasma display panel includes: a barrier rib formed with a dielectric and defining discharge cells together with a transparent first substrate and a second substrate opposite thereto; Common-address electrode lines disposed in the first partition wall to surround the discharge cells and extending across the discharge cells; Scan electrode lines spaced apart from the common-address electrode lines in the partition wall to surround the discharge cell, and extended to cross the common-address electrode lines in each discharge cell; A phosphor layer disposed in the discharge cell; And a discharge gas in the discharge cell; The driving method, In the reset period, a first initialization discharge by applying a ramp-up pulse and a second initialization discharge by applying a ramp-down pulse to the scan electrode lines, In the address period, a scan pulse of scan low level V _SC-L is sequentially applied to the plurality of scan electrode lines maintaining scan high level V _{SC -H} , and a scan to which the scan pulse is applied A display data signal is selectively applied to the common-address electrode lines crossing the electrode lines. In the sustain discharge period, alternate sustain pulses are applied to the scan electrode lines, In the reset period, when a rampdown pulse is applied to the scan electrode lines, a bias voltage Vx is applied to the common-address electrode lines, and the voltage magnitude Vnf2 of the lowest voltage of the rampdown pulse is maintained. And the voltage magnitude (Vs) of said alternating sustain pulse in a discharge period. The method of claim 1, In the discharge cell of the plasma display panel, the sum of the wall voltage due to the wall charge accumulated in the partition wall and the voltage difference between the signals applied to the common-address electrode and the scan electrode, the intrinsic discharge starting voltage (Vf) of the discharge cell Generates a strong discharge when it exceeds And the natural discharge starting voltage of the reset period, the natural discharge starting voltage of the address discharge period, and the natural discharge starting voltage of the sustain discharge period are the same. The method of claim 2, And the voltage magnitude (Vs) of the alternating sustain pulses applied to the scan electrode lines in the sustain discharge period is greater than half of the intrinsic discharge start voltage (Vf). The method of claim 2, The ramp down pulse applied to the scan electrode in the reset period has a slope in which a second initialization discharge occurs while maintaining the wall voltage higher than the voltage of the ramp down pulse by the natural discharge start voltage. How to drive the panel. The method of claim 2, After the application of the ramp down pulse is finished, the plasma display maintains the reset wall voltage Vw higher than the lowest voltage of the ramp down pulse by the natural discharge start voltage Vf. How to drive the panel. The method of claim 5, And the magnitude of the wall voltage (Vw) after the reset in the discharge cell is less than half of the intrinsic discharge starting voltage (Vf). The method of claim 5, And the sum of the wall voltage (Vw) and the voltage magnitude (Vs) of the alternating sustain pulse after the reset in the discharge cell are smaller than the intrinsic discharge start voltage (Vf). A recording medium on which a program for executing the method of any one of claims 1 to 7 is recorded on a computer.