KR100502482B1 - Array substrate for LCD and method for fabricating of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a configuration of a liquid crystal display device array substrate for reducing parasitic capacitance caused by an overlap area between a drain electrode and a gate electrode.

In the array substrate for a liquid crystal display device according to the present invention, the source and drain electrodes and the gate electrode are formed, the gate electrode uses a part of the gate wiring extending in one direction, and the source electrode crosses the gate wiring perpendicularly. The gate electrode may be formed to branch to the upper portion of the gate electrode in the data line, and the drain electrode may be spaced apart from the data line and the source electrode on the gate electrode and overlap the gate electrode with a minimum area.

The structure of the source and drain electrodes can simplify the process margin, and can reduce the parasitic capacitance value generated between the gate electrode and the drain electrode, thereby manufacturing a high-quality liquid crystal display device.

Description

Array substrate for LCD and manufacturing method thereof {Array substrate for LCD and method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, comprising a configuration of an array substrate for a liquid crystal display device and a method of manufacturing the same for reducing parasitic capacitance (C _gd ) values generated by overlapping areas of the gate electrode and the drain electrode constituting the thin film transistor. It is about.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C, and a second As an electrode, an island-shaped source / drain metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the source / drain metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

In the above-described configuration, the operating characteristics of the thin film transistor (amorphous thin film transistor) are affected by the ratio of the width and length of the active channel layer existing between the source and drain electrodes, and to improve the operation of the thin film transistor. Increasing the width and reducing the length of the layers has been proposed.

2 and 3 are enlarged plan views showing an enlarged view of one pixel of an array substrate for a liquid crystal display device according to the related art to which such a configuration is applied, and a cross-sectional view taken along the line II-II`.

As shown in the drawing, the gate line 52 extending in one direction on the substrate 50 and the data line 66 defining the pixel region P are vertically intersecting with the gate insulating layer 56 interposed therebetween. It is composed.

At the intersection of the gate wiring 52 and the data wiring 66, the gate electrode 54, the gate insulating film 56, the semiconductor layer (the active layer 58 and the ohmic contact layer 60), the source and drain electrodes ( A thin film transistor T including 62 and 64 is configured. The semiconductor layers 58 and 60 extend below the data line 66.

The pixel electrode 70, which is in contact with the drain electrode 64 and the passivation layer 68, is formed in the pixel area.

In the above-described configuration, the gate electrode 54 protrudes from the gate wiring 66 to the pixel region, and the source electrode 62 is formed in a “U” shape on the gate electrode 54. The drain electrode 64 is positioned in the shape of a rod in the source electrode 62 to form an active channel CH exposed between the source and drain electrodes 62 and 64 in a U shape. When the channel layer is formed in a “U” shape, the channel CH layer between the source and drain electrodes 62 and 64 is shortened, and the width of the channel layer perpendicular to the channel layer is increased.

Therefore, since the mobility of the carrier can be increased, the operation characteristics of the thin film transistor can be improved.

However, since the above-described configuration has a structure in which the drain electrode 64 completely overlaps the gate electrode 54, the parasitic capacitance value C _gd due to the overlapping area between the two electrodes is increased to generate a flicker phenomenon. _{The p} voltage increases.

In addition, the above-described configuration is a structure in which a design change for minimizing the overlapping area of the drain electrode and the gate electrode is practically difficult in order to maintain the "U" -shaped channel structure.

Therefore, there exists a problem which causes the nonuniformity of the image quality by a flicker phenomenon.

The present invention has been proposed to solve the above problems, and in order to minimize the overlap area of the source electrode and the gate electrode, a part of the gate wiring is used as a gate electrode, and perpendicularly crosses the gate wiring. In the data wiring, a portion of the data wiring positioned above the gate wiring and a vertical branch connected thereto are configured as a source electrode, and the drain electrode spaced apart from the source electrode is at least overlapped with the gate wiring.

The above-described configuration aims at securing a wide width of the active channel and minimizing the parasitic capacitance value (C _gd value) generated between the drain electrode and the gate electrode.

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display device comprising: a gate wiring extending in one direction on a substrate; A data line defining a pixel area crossing the gate line perpendicularly; A source electrode positioned at an intersection point of the gate wiring and the data wiring, the gate electrode being a part of the gate wiring, a semiconductor layer on the gate electrode, a portion of the data wiring on the gate electrode, and a branch extending to the gate electrode; A thin film transistor configured to be spaced apart from the source electrode above the gate wiring by a predetermined distance, the thin film transistor including a drain electrode configured to have a minimum overlapping area with the gate electrode; And a transparent pixel electrode formed on the pixel area while in contact with the drain electrode.

An auxiliary capacitor portion further configured to form an island-shaped metal layer in contact with the pixel electrode on the upper portion of the gate wiring, and to serve as a first electrode and a second electrode of the gate wiring below.

The semiconductor layer includes an active layer and an ohmic contact layer, and extends below the data line.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate wiring extending in one direction on the substrate; Forming a data line crossing the gate line to define a pixel area; A source electrode positioned at an intersection point of the gate wiring and the data wiring, the gate electrode being a part of the gate wiring, a semiconductor layer on the gate electrode, a portion of the data wiring on the gate electrode, and a branch extending to the gate electrode; Forming a thin film transistor comprising a drain electrode configured to be spaced apart from the source electrode by a predetermined distance, the drain electrode configured to have a minimum overlapping area with the gate electrode; Forming a transparent pixel electrode formed on the pixel region while being in contact with the drain electrode.

An island-shaped metal layer in contact with the pixel electrode is further formed on the gate wiring, so that the auxiliary capacitor portion is formed as a first electrode and the gate wiring below the second electrode is further formed.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

4 is an enlarged plan view of an enlarged view of one pixel of an array substrate for a liquid crystal display according to the present invention.

As shown in the drawing, the extension gate line 102 and the data line 118 defining the pixel region P are formed on the substrate 100 so as to intersect the gate line 102 perpendicularly to the get line 102.

The thin film transistor T including the gate electrode 104, the active layer 108, the source electrode 112, and the drain electrode 114 is formed at the point where the two wires 102 and 118 intersect.

The pixel region P includes a transparent pixel electrode 126 in contact with the drain electrode 114, and a storage capacitor C _ST connected in parallel with the drain electrode 114 is formed on the gate line 102. do.

The storage capacitor C _ST has an island-shaped metal layer 116 positioned above the gate wiring 102 and in contact with the pixel electrode 126 as a first electrode, and a lower portion thereof has the gate wiring 102 as a second electrode. It is an electrode.

In the above-described configuration, unlike the related art, the gate electrode 104 constituting the thin film transistor T is part of the gate wiring 102, and the source electrode 112 crosses the gate wiring 102 vertically. A portion of the wiring 118 and the data wiring 118 branched above the gate electrode 104.

The drain electrode 114 is configured to be spaced apart from the source electrode 112 in parallel with a predetermined interval, and is configured to have a minimum overlapping area with the gate wiring 102.

This configuration is a configuration that can minimize the overlap area between the drain electrode 114 and the gate electrode 102, it is a configuration that can induce a sufficient reduction of parasitic capacitance.

In addition, since the configuration of the source and drain electrodes is simple, a process margin can be secured.

Hereinafter, a manufacturing process of an array substrate for liquid crystal display autonomous according to the present invention will be described with reference to FIGS. 5A to 5D. FIG. 5A to FIG. 5D are a plan view according to a process sequence and cut along the line VV ′. The cross-sectional view will be displayed at the same time.)

As shown in FIG. 5A, the switching region T and the pixel region P are defined on the substrate 100.

Aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), tungsten (W), chromium (Cr), and copper (C) on the entire surface of the substrate 100 where the switching region T and the pixel region P are defined. One selected from the group of conductive metals including Cu) is deposited and patterned to form the gate wiring 102 passing through the pixel region P and the switching region T.

At this time, a part of the gate wiring 102 passing through the switching region is used as the gate electrode (convenience 104).

Next, the gate insulating layer 106 as the first insulating layer is deposited by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate on which the gate wiring is formed. Form.

As illustrated in FIG. 5B, pure amorphous silicon (a-Si: H) and amorphous silicon (n + a-Si: H) containing impurities are deposited and patterned on the gate insulating layer 106 to form a gate electrode. An active layer 108 and an ohmic contact layer 110 are formed on the gate insulating film 106 above.

In this case, as shown in the drawing, the active layer 108 and the ohmic contact layer 110 extend to a region where a data line is to be formed.

Since the semiconductor layer has excellent interfacial properties with the metal, there is an advantage of improving the contact characteristics of data lines to be formed later.

Next, as shown in FIG. 5C, chromium (Cr), molybdenum (Mo), tungsten (W), and titanium (Ti) are formed on the entire surface of the substrate 100 on which the active layer 108 and the ohmic contact layer 110 are formed. ) And a selected one of the conductive metal groups including copper (Cu) is deposited and patterned to intersect the gate wiring 102 perpendicularly to the data wiring 118 and the gate wiring 102 at the data wiring 118. The drain electrode 114 is configured to be spaced apart from the source electrode 112 and the source electrode 112 by a predetermined interval, and overlap the gate wiring 102 with a minimum area. At the same time, the metal layer 116 having an island shape is formed on the gate wiring.

Next, a protective film is coated by applying one selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin (resin) to the entire surface of the substrate 100 on which the source and drain electrodes 112 and 114 are formed. Form 120.

Subsequently, the passivation layer 120 is patterned to form a drain contact hole 122 exposing a part of the drain electrode 114 and a storage contact hole 124 exposing the island-shaped metal layer 116. .

Next, as shown in FIG. 5D, one selected from a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the passivation layer 120. The pixel electrode 126 located in the pixel region P is formed while contacting the drain electrode 114 and the island-shaped metal layer 116.

At this time, the storage capacitor (auxiliary capacitor) C _ST having the island-shaped metal layer 116 in contact with the pixel electrode 126 as the first electrode and the lower gate wiring 102 as the second electrode. Is formed.

Through the process as described above it can be produced an array substrate for a liquid crystal display device according to the present invention.

Unlike the related art, the thin film transistor according to the present invention has an advantage in that the gate electrode and the drain electrode can be easily changed in design so that the overlap area between the two electrodes can be sufficiently controlled.

Therefore, since the array substrate for the liquid crystal display device according to the present invention can minimize the overlap area between the gate electrode and the source electrode, parasitic capacitance caused by the overlap area of the two electrodes can be minimized. Therefore, it is possible to fabricate a high-quality liquid crystal display device. In addition, since the source and drain electrodes are formed on the gate wiring, the area where the thin film transistor occupies the pixel area can be minimized, thereby improving the aperture ratio. It has an effect.

1 is a diagram schematically illustrating a configuration of a general liquid crystal display device.

2 is an enlarged plan view illustrating an enlarged view of one pixel of an array substrate for a liquid crystal display device;

3 is a cross-sectional view taken along the line II-II ′ of FIG. 2;

4 is an enlarged plan view of an enlarged view of one pixel of an array substrate for a liquid crystal display device according to the present invention;

5A to 5D are process plan views and process cross-sectional views cut along the line VV ′ according to the process sequence of the present invention.

<Brief description of the main parts of the drawing>

100: substrate 102: gate wiring

104: gate electrode 108: active layer

112 source electrode 114 drain electrode

116: island-shaped metal layer 118: data wiring

126: pixel electrode

Claims (8)

A gate wiring extending in one direction on the substrate; A data line defining a pixel area crossing the gate line perpendicularly; A source electrode positioned at an intersection of the gate wiring and the data wiring, the gate electrode being a part of the gate wiring, a semiconductor layer on the gate electrode, a portion of the data wiring on the gate electrode, and a branch extending vertically to the gate electrode; A thin film transistor configured to be spaced apart from the source electrode above the gate wiring by a predetermined distance, the thin film transistor including a drain electrode configured to have a minimum overlapping area with the gate electrode; A transparent pixel electrode formed on the pixel region while in contact with the drain electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1, And an auxiliary capacitor portion further configured to form an island-shaped metal layer in contact with the pixel electrode on the upper portion of the gate wiring, the first electrode being a first electrode, and a second electrode on the lower gate wiring. The method of claim 1, And the semiconductor layer comprises an active layer and an ohmic contact layer and extends below the data line. Forming a gate wiring extending in one direction on the substrate; Forming a data line crossing the gate line to define a pixel area; A source electrode positioned at an intersection of the gate wiring and the data wiring, the gate electrode being a part of the gate wiring, a semiconductor layer on the gate electrode, a portion of the data wiring on the gate electrode, and a branch extending vertically to the gate electrode; Forming a thin film transistor, the thin film transistor comprising a drain electrode configured to be spaced apart from the source electrode by a predetermined interval and configured to have a minimum overlapping area with the gate electrode; A transparent pixel electrode formed on the pixel region while in contact with the drain electrode Array substrate manufacturing method for a liquid crystal display device comprising the step of forming a. The method of claim 4, wherein Forming an island-shaped metal layer in contact with the pixel electrode on the upper portion of the gate wiring to form a first electrode and a second capacitor portion for forming a second electrode on the lower gate wiring further manufactured array substrate for a liquid crystal display device Way. The method of claim 4, wherein And the semiconductor layer comprises an active layer and an ohmic contact layer, and extends below the data line. The method of claim 6, And the active layer is pure amorphous silicon (a-Si: H), and the ohmic contact layer (n + a-Si: H) is amorphous silicon containing impurities. The method of claim 4, wherein And the transparent pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).