KR20080062551A - The liquid crystal display device of a storage on common type and the method for fabricating thereof - Google Patents

Abstract

A storage on common LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to reduce the thickness of a dielectric layer by forming data lines and storage lines using the same material. A storage on common LCD includes a substrate(300), gate lines formed on the substrate in one direction, data lines(330) intersecting the gate line to define pixel regions(P), a TFT(Thin Film Transistor)(T) formed at each of intersections of the gate lines and the data lines, a pixel electrode(370) connected to the TFT, and a storage line(350) arranged in parallel with the data lines. The longer side of the pixel electrode is parallel with the gate lines and the shorter side thereof is parallel with the data lines. The data lines and the storage line are formed of the same material and a gate insulating layer(345) is formed between the gate lines and the storage line.

Description

The liquid crystal display device of a storage on common type and the method for fabricating according to the present invention.

1 is a plan view showing an array substrate for a general liquid crystal display device.

FIG. 2 is a plan view illustrating unit pixels of an array substrate for a general storage on common type liquid crystal display device; FIG.

3 is a cross-sectional view taken along line III-III of FIG. 2;

4A and 4B are respective plan views schematically showing unit pixels of a conventional array substrate for a liquid crystal display device having sufficient storage capacity.

5 is a plan view showing an array substrate for a liquid crystal display device according to the present invention.

6 is a plan view illustrating unit pixels of an array substrate for a storage on common liquid crystal display device according to an exemplary embodiment of the present invention.

7A to 7C are cross-sectional views taken along the line VII-VII of FIG. 6 according to the process sequence.

* Explanation of symbols for the main parts of the drawings *

300 substrate 325 gate electrode

330 data wiring 332 source electrode

334 drain electrode 340 active layer

341: ohmic contact layer 345: gate insulating film

350: storage wiring 355: protective film

370 pixel electrode CH2 drain contact hole

The present invention relates to a liquid crystal display device, and more particularly, to a high capacity liquid crystal display device and a method for manufacturing the liquid crystal display device without reducing the aperture ratio.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the liquid crystal may be artificially applied to control the direction of the molecular arrangement.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

In addition, the LCD includes a color filter substrate having a common electrode, an array substrate having pixel electrodes, and a liquid crystal filled between the two substrates. It is a system driven by it, and it is excellent in characteristics, such as transmittance | permeability and aperture ratio.

In general, the pixel electrode of the array substrate forms a liquid crystal capacitor together with the common electrode of the color filter substrate, and the voltage applied to the liquid crystal capacitor is not maintained until the next signal comes in and leaks away.

Therefore, in order to maintain the applied voltage, the storage capacitor must be connected to the liquid crystal capacitor.

In general, the storage capacitor may be formed in two ways, in which electrodes for the storage capacitor are separately formed and connected to the common electrode, and a portion of the n-1th gate wiring is used as the electrode of the storage capacitor of the nth pixel. There is a way.

The former is called a storage on common method or an independent storage capacitor method, and the latter is called a storage on gate or a prior gate method.

The storage-on-gate method has an advantage of not requiring external storage wiring since the storage signal is applied using a gate wiring, but has a disadvantage of receiving interference due to coupling with the gate signal.

On the other hand, the storage-on-common method has an advantage of ensuring sufficient storage capacity without interfering with the gate signal, but it is necessary to prepare for this because high-definition TV products require more storage capacity.

Hereinafter, a liquid crystal display of a general storage on common type will be described with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating an array substrate for a liquid crystal display of a general storage on common type, which will be described with reference to the drawings.

As shown in the figure, a plurality of gate lines 20 are formed to be spaced apart in parallel in the first direction on the transparent substrate 10, and the pixel regions P cross each other perpendicularly to the plurality of gate lines 20. A plurality of data wires 30 defining a) are spaced apart from each other in parallel in the second direction.

In this case, the storage wirings 50 spaced apart from each other in parallel between the plurality of gate wirings 20 are configured.

At one end of each storage line 50, a storage common line 90 for applying a voltage to the storage line 50 is configured.

An antistatic circuit 80 is formed at a portion where the storage wiring 50 and the storage common wiring 90 abut.

Thin film transistors T serving as a switch are respectively formed at portions where the gate lines 20 and the data lines 30 cross each other, so that the thin film transistors T and the pixel electrodes 70 correspond one to one.

However, in the conventional liquid crystal display device, the storage wirings are made of the same material as the gate wirings. In this configuration, the gate insulating film and the protective film interposed between the gate wirings and the storage wirings are composed of double layers, Difficulty in securing sufficient storage capacity.

This will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view illustrating unit pixels of a general storage on common type liquid crystal display array substrate, and FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2, and will be described with reference to FIGS. 1 and 2. .

As illustrated, the gate line 120 and the gate electrode 125 extending from the gate line 120 are formed in one direction on the substrate 100. The storage wiring 150 is formed of the same material as the gate wiring 120 to serve as the first electrode of the storage capacitor Cst in the same process.

The gate insulating layer 145 is formed on one of the inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the upper surfaces of the gate wirings and the electrodes 120 and 125 and the storage wiring 150.

In addition, an active layer 140 made of island-shaped pure amorphous silicon and an ohmic contact layer 141 made of impurity amorphous silicon are stacked on the substrate 100 on which the gate insulating layer 145 is formed.

A data line 130 is formed on the substrate 100 on which the active layer 140 and the ohmic contact layer 141 are formed to cross the gate line 120 to define the pixel region P. In this case, the source electrode 132 extending from the data line 130 overlaps a portion of the gate electrode 125, and the drain electrode 134 is formed to be spaced apart from the source electrode 132.

In addition, the ohmic contact layer 141 exposed between the source and drain electrodes 132 and 134 is removed to expose the active layer 140.

One selected from the group of inorganic insulating materials, such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ), on the entire upper surface of the substrate 100 on which the source and drain electrodes 132 and 134 and the data line 130 are formed. The protective film 155 is formed of one selected from the group of organic insulating materials including (benzocyclobutene: BCB) and acrylic resin.

In this case, the drain contact hole CH1 is formed by removing the passivation layer 155 corresponding to a part of the drain electrode 134, and the indium tin oxide is formed on the passivation layer 155 on which the drain contact hole CH1 is formed. The pixel electrode 170 is formed in the pixel region P as one selected from a group of transparent conductive metals including ITO and indium zinc oxide (IZO).

Here, the storage wiring 150 is used as the first electrode, and the pixel electrode 170 of the portion overlapping with the storage wiring 150 is used as the second electrode, and the gate insulating layer 145 and the passivation layer interposed therebetween. A storage capacitor (Cst) of a storage common common type (storage common) including 155 is configured.

However, in the conventional storage on common storage capacitor Cst, the gate insulating layer 145 and the passivation layer 155, which are dielectric layers interposed between the first electrode and the second electrode, are continuously formed, so that the overall thickness of the dielectric layer is increased. Due to its size, it was not able to secure enough storage capacity, so it could not actively cope with problems such as signal delay in high-definition liquid crystal displays.

As a countermeasure, there is a method of increasing the storage capacity by increasing the area of the first electrode and the second electrode.

This will be described below with reference to the accompanying drawings.

4A and 4B are plan views schematically illustrating unit pixels of a conventional array substrate for a liquid crystal display device having sufficient storage capacity, and the same reference numerals are given to the same names as in FIG. .

First, as shown in FIG. 4A, the storage wiring 150 is formed on the substrate 100 in parallel with the gate wiring (120 of FIG. 2), and the gate wiring and the storage wiring 150 are the same layer. Consists of matter.

In addition, the pixel electrode 170 is formed to overlap the storage line 150. In this case, unlike the above-described configuration, the long side of the pixel electrode 170 is configured to be parallel to the storage wiring 150, and the short side is configured to be parallel to the data wiring (130 of FIG. 2).

Therefore, when the long side of the pixel electrode 170 is configured in parallel with the storage wiring 150, the overlapping area of the storage wiring 150 and the pixel electrode 170 is widened, thereby sufficiently securing the storage capacity.

In addition, as shown in FIG. 4B, the storage electrode 150 is configured to bypass the storage wiring 150 to the outer side along the long side of the pixel electrode 170 in a configuration capable of securing a larger storage capacity than the above-described FIG. 4A. The storage capacity may be further secured by further expanding the overlapping area with the 170.

However, in the above-described two configurations, a sufficient storage capacity can be secured by securing a large overlap area between the storage wiring and the pixel electrode. However, since the storage wiring is formed of an opaque metal, the aperture ratio is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to fabricate a liquid crystal display device having sufficient storage capacity and improved aperture ratio.

To this end, in the present invention, the long side of the pixel electrode is configured to be in parallel with the gate wiring, and the data line and the storage wiring which intersect with each other perpendicularly are configured to be parallel to the short side of the pixel electrode.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a substrate, a gate wiring formed in one direction on the substrate, a data wiring defining a pixel region vertically crossing the gate wiring, and the gate wiring; A thin film transistor configured at a portion where the data lines cross each other;

Each of the thin film transistors is connected to each other, and a long side includes a pixel electrode configured to be parallel to the gate line and a short side to the data line, and a storage line configured to be parallel to the data line.

In this case, the data line and the storage line are made of the same material, and a gate insulating layer is formed between the gate line and the storage line.

A protective film is formed between the storage wiring and the pixel electrode. In this case, the storage capacitor Cst is configured such that the storage wiring is the first electrode, a part of the pixel electrode overlapping the storage wiring is the second electrode, and only the passivation layer interposed therebetween is a dielectric layer. It features.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a substrate, a plurality of gate wires formed in a first direction on the substrate, and a plurality of gate wires arranged in a second direction perpendicular to the gate wires. A plurality of thin film transistors configured to intersect a data line and the gate line and the data line;

A plurality of pixel electrodes connected to the thin film transistor, short sides of which are parallel to the data lines, and long sides of which are parallel to the gate lines, and a plurality of storages that pass through the short sides of the pixel electrodes and are parallel to the data lines. It includes wiring.

A storage layer may further include a passivation layer between the storage line and the pixel electrode. The storage line may be a first electrode, the pixel electrode overlapping the second electrode may be a second electrode, and the passivation layer may be a dielectric layer. The capacitor Cst is configured.

According to an aspect of the present invention, there is provided a method of fabricating an array substrate for a liquid crystal display device, the method including preparing a substrate, forming a gate wiring in one direction on the substrate, and a gate electrode extending from the gate wiring. Forming a gate insulating film on the substrate on which the gate electrode and the gate wiring are formed;

Forming a semiconductor layer over the gate insulating layer, depositing a source and a drain metal layer over the semiconductor layer, and patterning the semiconductor layer to form a data line, a source and a drain electrode, and a storage line; Forming a passivation layer on the substrate on which the source and drain electrodes and the storage wiring are formed;

Forming a drain contact hole by removing the passivation layer corresponding to a portion of the drain electrode, and a long side parallel to the gate line and a short side parallel to the storage line on the passivation layer on which the drain contact hole is formed Forming a pixel electrode to be formed.

In this case, the data line and the storage line are spaced apart in parallel. And a storage capacitor Cst having the storage wiring as the first electrode, a part of the pixel electrode overlapping the storage wiring as the second electrode, and the protective layer interposed therebetween as the dielectric layer. It features.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

5 is a plan view illustrating an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6 is a plan view illustrating a unit pixel of FIG. 5 and will be described with reference to FIGS. 5 and 6.

As illustrated, a plurality of gate wires 320 are spaced apart in parallel in the first direction on the substrate 300, and a plurality of gate wires 320 are perpendicularly intersected with the plurality of gate wires 320. The data lines 330 are spaced apart in parallel.

In this case, an area defined by the gate line 320 and the data line 330 intersecting with each other is called a pixel area P. FIG.

In addition, the storage wiring 350 spaced apart in parallel between the plurality of data lines 330 is configured.

A storage common line 390 for applying a voltage to the storage line 350 is formed at one end of each storage line 350.

An antistatic circuit 380 is formed at a portion where the storage wiring 350 and the storage common wiring 390 abut.

Each of the gate lines 320 and the data lines 330 intersect with the thin film transistor T serving as a switch, and the thin film transistor T and the pixel electrode 370 correspond one to one.

The thin film transistor T includes a gate electrode 325, source and drain electrodes 332 and 334, an active layer 340, and an ohmic contact layer (not shown).

In this case, the long side of the pixel electrode 370 is configured to be parallel to the gate line 320, and the short side thereof is configured to be parallel to the data line 330 and the storage line 350.

Therefore, in the present invention, since the storage wiring 350 is formed of the same material as the data wiring 330, only a protective film (not shown) interposed between the storage wiring 350 and the pixel electrode 370 can be used as the dielectric layer. Therefore, a high capacity storage capacitor (Cst) can be manufactured.

In addition, since the storage wiring 350 overlaps the short side of the pixel electrode 370, the overlapping area is small, thereby improving the aperture ratio.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

7A to 7C are cross-sectional views taken along the line VII-VII of FIG. 6 according to the process sequence.

As shown in FIG. 7A, a gate metal layer (not shown) is deposited on the substrate 300 with one selected from a group of conductive metals such as aluminum (Al), aluminum alloy (AlNd), and chromium (Cr). In one direction, the gate line 320 (in FIG. 6) and the gate electrode 325 extending from the gate line are formed.

Next, the gate insulating layer is selected from a group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the entire upper surface of the substrate 300 on which the gate wiring (320 of FIG. 6) and the gate electrode 325 are formed. 345 is formed.

Pure amorphous silicon and impurity amorphous silicon are successively deposited on the substrate 300 on which the gate insulating layer 345 is formed, and then patterned to form the island-shaped active layer 340 and the ohmic contact layer 341 as the gate electrode 325. To overlap with).

As shown in FIG. 7B, molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) are formed on the entire upper surface of the substrate 300 on which the active and ohmic contact layers 340 and 341 are formed. A data line 330 for depositing a source and a drain metal layer (not shown) with one selected from the group of conductive metals and patterning the source and drain metal layers to cross the gate line 320 in FIG. 6 to define a pixel region P; A source electrode 332 extending from the data line 330 and a drain electrode 334 spaced apart from each other are formed.

At the same time, the storage wiring 350 spaced in parallel with the data wiring 330 is configured to pass through the central portion of the pixel region P. Referring to FIG.

Next, inorganic insulation such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed on the entire upper surface of the substrate 300 on which the source and drain electrodes 332 and 334, the data wire 330, and the storage wire 350 are formed. The protective layer 355 is formed by one selected from the group of materials or one selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin.

As shown in FIG. 7C, the protective layer 355 corresponding to a part of the drain electrode 334 is removed to form the drain contact hole CH2.

Next, a selected one of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the passivation layer 355 on which the drain contact hole CH2 is formed. The pixel electrode 370 is formed in the pixel region P by patterning.

In this case, when the long side of the pixel electrode 370 is configured to be parallel to the gate wiring 320, and the short side of the pixel electrode 370 is configured to be parallel to the data wiring 330 and the storage wiring 350, the pixel electrode 370 is connected to the pixel electrode 370. The overlap area between the storage lines 350 may be reduced to improve the aperture ratio.

In addition, the storage wiring 350 is a first electrode, a part of the pixel electrode 370 overlapping the storage wiring 350 is a second electrode, and only the passivation layer 355 interposed therebetween is a dielectric layer. The storage on common storage capacitor Cst may be configured.

As described above, the array substrate for the liquid crystal display device according to the present invention can be manufactured through the above-described process.

Therefore, in the liquid crystal display according to the present invention, since only the protective film is used as the dielectric layer of the storage capacitor, the storage capacity can be sufficiently secured in proportion to the thickness reduction of the dielectric layer.

In addition, since the storage wiring overlaps the short side of the pixel electrode, the aperture ratio can be improved.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

In the liquid crystal display and the method of manufacturing the same according to the present invention, the thickness of the dielectric layer can be reduced by forming the storage wiring with the same material as the data wiring. In addition, the long side of the pixel electrode is configured in parallel with the gate wiring, and the short side thereof is configured in parallel with the storage wiring, whereby the aperture ratio can be reduced.

Through this, it is possible to solve problems such as signal delay, thereby producing a high-quality liquid crystal display device.

Claims (10)

A substrate; A gate wiring formed in one direction on the substrate; A data line crossing the gate line perpendicularly to define a pixel area; A thin film transistor configured at a portion where the gate line and the data line cross each other; A pixel electrode connected to each of the thin film transistors, a long side of which is parallel to a gate line, and a short side of which is parallel to the data line; Storage wiring configured in parallel with the data wiring Liquid crystal display comprising a. The method of claim 1, And the data line and the storage line are made of the same material as the same layer. The method of claim 1, And a gate insulating film formed between the gate line and the storage line. The method of claim 1, And a passivation layer between the storage line and the pixel electrode. The method of claim 3, wherein A liquid crystal display device comprising a storage capacitor Cst having the storage wiring as a first electrode, a portion of the pixel electrode overlapping the storage wiring as a second electrode, and a protective layer interposed therebetween as a dielectric layer. . Preparing a substrate; Forming a gate wiring on the substrate in one direction and a gate electrode extending from the gate wiring; Forming a gate insulating film on the substrate on which the gate electrode and the gate wiring are formed; Forming a semiconductor layer on the gate insulating film; Depositing a source and a drain metal layer on the semiconductor layer, and patterning the source and drain metal layers to form a data line, a source and a drain electrode, and a storage line; Forming a passivation layer on the substrate on which the data line, the source and drain electrodes and the storage line are formed; Removing the passivation layer corresponding to a portion of the drain electrode to form a drain contact hole; Forming a pixel electrode on the passivation layer on which the drain contact hole is formed, the long side of which is parallel to the gate line and the short side of the pixel electrode which is formed to be parallel to the storage line; Liquid crystal display device manufacturing method comprising a. The method of claim 6, And the data line and the storage line are spaced apart in parallel. The method of claim 6, A liquid crystal display comprising a storage capacitor (Cst) having the storage wiring as a first electrode, a portion of the pixel electrode overlapping the storage wiring as a second electrode, and a protective layer interposed therebetween as a dielectric layer. Manufacturing method. A substrate; A plurality of gate wirings arranged in a first direction on the substrate; A plurality of data lines configured in a second direction perpendicular to the gate lines; A plurality of thin film transistors formed at portions where the gate lines and the data lines cross each other; A plurality of pixel electrodes connected to the thin film transistor, the short sides of which are parallel to the data lines, and the long sides of which are parallel to the gate lines; A plurality of storage lines penetrating the short sides of the pixel electrodes and configured to be parallel to the data lines; Liquid crystal display comprising a. The method of claim 9, A storage capacitor further includes a protective film between the storage wiring and the pixel electrode, wherein the storage wiring is a first electrode, the pixel electrode overlapping the second electrode is a second electrode, and the storage capacitor interposed therebetween is a storage layer. A liquid crystal display device in which a emitter Cst is configured.

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