KR100492545B1 - Data transfer path decision apparatus for asynchronous transfer mode system - Google Patents

Abstract

The present invention relates to an apparatus for determining a data transmission path of an ATM system. In particular, the present invention relates to a virtual path (VP) / virtual channel (VC) for a currently input ATM cell and includes a table for determining a virtual path in a header of an ATM cell. The purpose of the present invention is to determine a processor to communicate by using a virtual path / virtual channel table by inserting and transmitting virtual channel information. For this purpose, the present invention provides a table for storing the virtual channel (VC) and the virtual path (VP) values, and outputting the corresponding tag signal by comparing the VP / VC information included in the ATM cell received from the cell bus. VC table 312, first-in first-out memory (FIFO) 313-315 connected to the front end of each of the processors 316-318, and buffering data, and VP / VC information in an ATM cell transmitted from the cell bus. Extracts and transmits the data to the VP / VC table 312, receives a tag signal according to the comparison result from the VP / VC table 312, and determines a processor to communicate with. 3 to 315, the router 311 stores the memory.

Description

DATA TRANSFER PATH DECISION APPARATUS FOR ASYNCHRONOUS TRANSFER MODE SYSTEM}

The present invention relates to a mobile communication system, and more particularly, to an apparatus for determining a data transmission path of an ATM system.

In general, an Asynchronous Transfer Mode (ATM) system using a 155 Mbps Synchronous Transport Module level-1 (STM-1) link uses multiple processors within a single board. It is configured to select a desired processor using a virtual channel (VC).

1 is a block diagram of a conventional ATM system. As shown in FIG. 1, a master board 110 and a plurality of slab boards 1201 to 1220 are connected in parallel to a cell bus 100.

The master board 110 includes an MCC 111 and an NCC 112 to which a processor 113 is connected.

The slab boards 1201 to 1220 include the NCC 121 and a plurality of processors 122 to 124 connected in parallel to the NCC 121.

Referring to the operation of the conventional system as follows.

When an external 53-byte ATM cell comes in, a slot recognition name (SLOT_ID) indicating SLOT information and a processor recognition name (SLOT_ID) indicating information of a processor in the Master Cell Converter (MCC) block 111 of the master card 110 ( 3 bytes of headers with information such as PROC_ID) are added to make 56 bytes.

Subsequently, when the MCC 111 transmits the ATM cell converted to the format as shown in FIG. 2 to the cell bus, each slab card 1201 to 1220 receives 3 bytes of information from the NCC block 121. If it is checked, it is determined that the ATM cell is transmitted to itself, and if it is determined that the ATM cell is transmitted to itself, it is determined which processor among the processors 122 to 124 is transmitted.

That is, the prior art is to transfer the normalized ATM cell to the desired processor using the three bytes of information added in the MCC block 111 in the NCC block 112 or 121.

Here, the 56-byte cell format adds 3 bytes of information not found in the standardized 53-byte ATM cell, as shown in the example of FIG. 2, and includes a SID and a multi-processor indicating a slot recognition name (SLOT_ID). In this case, the processor identification name PROC_ID representing the processor information is included.

In the format of FIG. 2, GFC represents Generic Flow Control, CLP represents Cell Loss Priority, PT represents Payload Type, HEC represents Header Error Control, VPI represents Virtual Path Identifier, and VCI represents Virtual Channel Identifier.

However, conventionally, when using various standardized ATM components or equipment, there are components that do not support the ATM cell format as shown in FIG. 2, which causes inconveniences in using the ATM cell format as shown in FIG. 2.

That is, in the prior art, since an ATM cell structure of 56 bytes by adding 3 bytes is not a standard method, there is a problem that UTOPA (Universal Operations Physical Layer Interface for ATM), which is an interface between an ATM and a physical layer, cannot be executed.

Accordingly, the present invention has a table for determining the virtual path (VP) / virtual channel (VC) for the ATM cell currently input to improve the conventional problem, and the virtual path / virtual channel information in the header portion of the ATM cell It is an object of the present invention to provide an apparatus for determining a data transmission path of an ATM system, which is designed to determine a processor for communication by using a virtual path / virtual channel table by inserting and transmitting it.

In order to achieve the above object, in the parallel connection of a plurality of slab cards each having a master card and a plurality of processors on an ATM bus, the virtual channel VC and the virtual path VP are stored in a table. And a VP / VC table for outputting a corresponding tag signal in comparison with the received VP / VC information, a plurality of first-in first-out memory (FIFO) respectively connected to the front end of the plurality of processors, and the ATM cell transmitted from the ATM cell bus. The extracted VP / VC information is transmitted to the VP / VC table and the tag signal according to the comparison result is received in the VP / VC table to determine which processor to communicate among the plurality of processors. The first-in, first-out of the memory is characterized in that configured as a router (ACR; ATM Cell Router) to be stored in the memory connected to the processor determined above. The router includes a latch for separating four bytes of header information from an ATM cell transmitted to an ATM cell bus, and a table for transmitting the four bytes of header information to a VP / VC table and receiving a comparison result from the VP / VC table. The demultiplexer (DEMUX) which transfers the ATM cell in the latch to the first-in first-out memory connected to the processor according to the interface unit, the comparison result received by this table interface unit, and the ATM cell to which the header information is added in any processor are provided. When the transmission is characterized by consisting of a multiplexer (MUX) to transmit to the ATM cell bus.

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Hereinafter, the present invention will be described in detail with reference to the drawings.

3 is a block diagram of a slab card for an embodiment of the present invention, as shown here, a VP / VC table 312 for storing and storing the virtual channels VC and virtual paths VP, respectively. Receive first-in first-out memory (FIFO) 313-315 connected to the front end of processors 316-318 and ATM cells transmitted from the cell bus to compare VP / VC information in the VP / VC table 312. The tag signal of the comparison result is used to determine a processor to communicate with, and the router 311 stores the ATM cell in the first-in first-out memory 313 to 315 to the corresponding memory.

The router 311 is an ACR (ATM Cell Router), as shown in the block diagram of FIG. 4, a latch 411 for latching a receiving cell to separate four bytes of header information, and the four bytes of header information. The table interface unit 412 which transmits to the VP / VC table 312 and receives the comparison result at that time, and the ATM cell at the latch 411 based on the comparison result received by the table interface unit 412. When the header information is inserted into an ATM cell from any of the processors 316 to 318, the demultiplexer 413 to be transmitted to the processor side is selected.

The VP / VC table 312 also inserts header information into the ATM cell when the ATM cell is transmitted to the ATM bus using the switched virtual circuit (SVC). Configure to update the contents of the.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

First, when using PVC (Permanent Virtual Circuit), the virtual path / virtual channel (VP / VC) is also assigned to each processor included in the master card or the slab card. After inserting the / virtual channel (VP / VC) value into the header portion of the ATM cell, the 53-byte ATM cell of the format shown in FIG. 5 is transmitted through the STM-1 Link.

Here, the format of the ATM cell transmitted through the STM-1 Link is as shown in Figure 5, the three-byte virtual channel identifier (VPI), virtual channel identifier (VCI) and the beginning and end PT (Payload Type) indicating and a HEC (Header Error Control) that informs the error of this ATM cell.

At this time, in each slab card, the router 311 separates the header information of 4 bytes and compares them in the VP / VC table 312 and converts them into a routing tag (TAG) value as a result of the comparison in the VP / VC table 312. The router 311 analyzes this to determine which processor among the processors 313 to 315 is the ATM cell to be transmitted.

Accordingly, the router 311 transmits the ATM cell to the corresponding processor determined above by transmitting the ATM cell to the first-in first-out memory among the first-in first-out memory 316 to 318 based on the determination result.

Since the router 311 is configured as shown in the block diagram of FIG. 4, when a 53-byte ATM cell is loaded from the master card to the cell bus, the latch 411 separates the 4-byte header information through the table interface 412. Simultaneously with the VP / VC table 312, the 53-byte ATM cell is transmitted to the demultiplexer 413. In the VP / VC table 312, the 4-byte header information separated by the latch 411 is preliminary. Compared to the stored information, the demultiplexer 413 transmits 53 bytes of ATM cells to the corresponding ones of the processors 313 to 315 based on the routing tag (TAG) value.

Here, the structure of the VP / VC table 312 is configured as shown in FIG.

Therefore, when the data of VP / VC is '00 / 20 ', for example, the contents of the VP / VC table 312 and the header information of 4 bytes separated from the latch 411 are compared. TAG) is output as '00 / 00 ', and when this '00 / 00' value is input to the router 311, the demultiplexer 413 is assumed to be processor 0, for example, the processor 316. The demultiplexing operation is performed so that the 53 bytes of the ATM cell in the latch 411 are stored in the first-in, first-out memory 313.

If there is no tag signal as a result of the comparison in the VP / VC table 312, the router 311 determines that the data is not transmitted to itself.

In addition, in case of using Switched Virtual Circuit (SVC) (VC; Virtual Channel, Virtual Channel), the same method as the PVC method is used, but information is inserted into the header and the VP / VC table ( Update the contents of 312).

That is, when using the SVC, if any of the processors 316 to 318 inserts header information into an ATM cell and stores it in the first-in first-out memory connected to the first-in first-out memory 313 to 315, the router 311 is a VP. In addition to updating the stored contents in the / VC table 312, the multiplexer 414 selects an ATM cell of the processor and transmits the selected ATM cell to the ATM bus.

As described in detail above, the present invention extracts VP / VC information from a standard ATM cell and compares it in a pre-stored table to determine a processor to communicate with, thereby eliminating inefficiency even when using an unstandardized ATM cell. There is an effect that can improve the performance of the system.

Therefore, the present invention can be effectively used in the design of a multi-processor (High-Processor) requiring high performance has an effect that can be applied to IS-95C, IMT-2000 system in the future.

1 is a block diagram of a conventional ATM system.

Figure 2 is an exemplary view showing a conventional ATM cell format.

Figure 3 is a schematic diagram of a slab card in the embodiment of the present invention.

4 is a block diagram of a router in FIG.

5 shows an exemplary format of a standard ATM cell.

6 is an exemplary view showing the structure of a VP / VC table in FIG.

Explanation of symbols on the main parts of the drawings

311: Router 312: VP / VC Table

313 to 315: first-in, first-out memory (FIFO) 316 to 318: processor

Claims (2)

In an ATM system configured by connecting a plurality of slab cards each including a master card and a plurality of processors to an ATM bus in parallel, A VP / VC table that stores the virtual channels VC and the virtual paths in a table, and outputs corresponding tag signals by comparing with the received VP / VC information; A plurality of first-in, first-out (FIFO) devices each connected to the front end of the plurality of processors; The VP / VC information extracted from the ATM cell transmitted from the ATM cell bus is transmitted to the VP / VC table, and the tag signal according to the comparison result is received from the VP / VC table to determine the processor to communicate among the plurality of processors. And an ATM cell router (ACR) for storing an ATM cell in the plurality of first-in, first-out memories in a corresponding memory connected to the processor determined above. . 2. The router of claim 1, wherein the router further comprises: a latch that separates four bytes of header information from an ATM cell transmitted to an ATM cell bus, and transmits the four bytes of header information to a VP / VC table and a comparison in the VP / VC table. The table interface unit for receiving the result, the demultiplexer (DEMUX) for transmitting the ATM cell in the latch to the first-in, first-out memory connected to the processor according to the comparison result received from the table interface unit, and the header information in any processor An apparatus for determining a data transmission path of an ATM system, comprising a multiplexer (MUX) for transmitting an added ATM cell to an ATM cell bus.