KR100430089B1 - Apparatus Of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel to reduce the number of switch elements used for set down and scan operations in the driving circuit of the plasma display panel.

A driving apparatus of a plasma display panel according to the present invention is a driving apparatus of a plasma display panel for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining a discharge of the selected cell. And an energy recovery circuit for recovering energy from the first electrode of the panel, wherein the energy recovery circuit comprises a setup / down pulse in the reset period, a scan pulse corresponding to selective write to select the cell in the address period, and a selective erase. A first electrode driver for supplying a scan pulse to the first electrode; The first electrode driver includes a set down / selective write scan driver for selectively supplying the set down pulse and the selective write scan pulse in response to a set down control signal and a selective write scan control signal, respectively.

Description

Apparatus Of Driving Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a driving apparatus of a plasma display panel for reducing the number of switch elements used for set down and scan operations in a driving circuit of a plasma display panel.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of inert mixed gases such as He + Xe, Ne + Xe and Ne + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 30Y and a common sustain electrode 30Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The scan / sustain electrode 30Y and the common sustain electrode 30Z each have a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and are formed on one edge region of the transparent electrode. Electrodes 13Y and 13Z. The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (hereinafter, referred to as “ITO”). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, and Ne + Ne + Xe for discharging is injected into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into a reset and an address period and a sustain period. Here, the reset and address periods of each subfield are the same for each subfield, while the sustain period increases at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. do. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

Such a driving method of the PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted by the address discharge in the address period. First, the selective write driving method turns off the full screen in the reset period, and then turns on the selected discharge cells in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge.

In the selective erasing driving method, the entire screen is turned on by writing discharge in the reset period, and then the selected discharge cells are turned off in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells not selected by the address discharge.

Since the selective erasing method is a discharge for removing wall charges in the cell, the scanning pulse width is narrower than that of the selective writing method, that is, the addressing time can be reduced. The drive waveform of the selective writing method reduces the contrast as the number of lamp pulses increases, so the quality of the driving waveform becomes weaker as it is used more. Accordingly, in the driving method of the PDP, as shown in FIG. 3, one frame is composed of the selective write subfields SF1 through SF6 and the selective erase subfields SF7 through SF12 to configure the selective write and erase method. Drive in parallel.

Referring to FIG. 3, in the method of driving a three-electrode alternating surface discharge PDP, one frame includes subfields SF1 through SF6 of selective writing and subfields SF7 through SF12 of selective erasing. The first subfield SF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining discharge for the discharge cell selected by the address discharge, and an erasing period for canceling the sustain discharge. . Each of the second to fifth subfields SF2 to SF5 is divided into an optional write address period, a sustain period, and an erase period. The sixth subfield SF6 is divided into an optional write address period and a sustain period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2n in each subfield (n = 0, 1, 2, 3, 4). Is increased by 5). The seventh through twelfth subfields SF7 through SF12 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without a full surface writing period in which the full screen is lit. Divided into periods. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 25 to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must have the previous subfield turned on to turn off unnecessary discharge cells whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. To this end, the cells turned on in the sixth subfield WSF, which is the last selective write subfield WSF, must be turned on by the sustain discharge in order for the selective erase subfield ESF to be used. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off cells that are turned on in the previous subfield without front lighting.

4 is a diagram illustrating a driving waveform according to the PDP driving method illustrated in FIG. 3.

Referring to FIG. 4, in the reset period of the first selective write subfield SW1, the reset pulse RP of the ramp-up waveform is followed by the reset pulse RP of the ramp-down waveform in the scan / sustain electrode lines Y. ) Are supplied sequentially. At this time, the reset pulse (-RP) of the ramp-down waveform drops to the negative scan reference voltage (-Vw). In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period of the selective write subfield SW1, the scan / sustain electrode lines Y and the address electrode lines X are respectively supplied while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z. The negative write (-) selective write scan pulse (SWSP) and the positive write (+) selective write data pulse (SWDP) are supplied to be synchronized with each other. The address discharge is performed by the selective write scan pulse SWSP and the optional data pulse SWDP as described above.

The sustain pulses SUSPy and SUSPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z so that sustain discharge occurs for the cells turned on by the address discharge in the selective write subfield SW. Supplied by. At the end of the second selective write subfield SW2, the erase pulse EP is supplied to the scan electrode lines Y to erase the sustain discharge.

The reset period of the selective erase subfield SE is omitted. In the address period of the selective erasing subfield SE, a negative selective negative scan pulse SESP and a positive polarity (T) for turning off a cell in each of the scan / sustain electrode lines Y and the address electrode lines X are applied. The selective erase data pulses SEDP of +) are supplied to be synchronized with each other. This selective erase scan pulse (-SESP) drops to the ground (GND) voltage.

Sustain pulses SUSPy and SUSPz alternate between scan / sustain electrode lines Y and common sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by the address discharge in the selective erase subfield SE. Supplied as In the case where the next subfield is the selective erasure field SE, a sustain pulse SUSPy having a relatively large pulse width is supplied to the scan / sustain electrode lines Y at the end of the current selective erasure subfield SE. . In the last selective erase subfield in which the next subfield is the selective write subfield SW, the erase pulse EP and the ramp signal RAMP are applied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. It erases the sustain discharge of the supplied and turned on cells.

FIG. 5 schematically illustrates a driving apparatus of a general PDP, and has been described with reference to the selective write and erase scheme shown in FIG. 4.

Referring to FIG. 5, the PDP driving apparatus drives the Y driver 32 for driving the m scan / sustain electrode lines Y1 to Ym and the m common sustain electrode lines Z1 to Zm. Z driver 34 for driving and X driver 36 for driving n address pole lines X1 to Xn.

The Y driver 32 initializes the full screen by supplying the setup / down waveforms (RP, -RP) in the selective write subfield (WSF) and at the selective write subfield (WSF) and the selective erase subfield (SEF). Different scan pulses -SWSP and -SESP are sequentially supplied to the scan / sustain electrode lines Y1 to Ym. In addition, the Y driver 32 supplies sustain pulses SUSY in the selective write subfield WSF and the selective erase subfield ESF to generate sustain discharge.

The Z driver 34 is commonly connected to the common sustain electrode lines Z1 to Zm to set-down waveform (-RP), scan DC voltage, and sustain pulse (SUSPz) to the common sustain electrode lines Z1 to Zm. ) To supply sequentially.

The X driver 36 supplies the write data pulse SWD or the erase data pulse SED to the address electrode lines X1 to Xn so as to be synchronized with the scan pulses -SWSP and -SESP.

6 shows the Y driver 32 in detail to explain the configuration and operation of the Y driver 32.

Referring to FIG. 6, the Y driver 32 includes sixth switches Q6A and Q6B connected between an energy recovery circuit 41 and a driver integrated circuit (hereinafter, referred to as IC) 42. A scan reference voltage supply unit 46 and a scan voltage supply unit 44 connected between the sixth switches Q6A and Q6B and the driver IC 42 to generate scan pulses (-SWSP, -SESP); A setup supply 45 and a set down supply 43 connected between the switches Q6A and Q6B and the scan reference voltage supply 46 and the scan voltage supply 44 to generate the setup / down waveforms RP and -RP. It is provided. Also connected between the setup voltage source Vsetup and the energy recovery circuit 41, between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vs constant. A second capacitor C2 connected in series is provided.

The driver IC 42 is connected in a push-pull form and includes twelfth and thirteenth switches Q12 and Q13 to which a voltage signal is input from the energy recovery circuit 41, the scan reference voltage supply 43, and the scan voltage supply 44. It consists of

The output line between the twelfth and thirteenth switches Q12 and Q13 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 41 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q1 and Q2 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a third switch Q3 connected between the sustain voltage supply source Vs and the second node n2, and a second The fourth switch Q4 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 41 will be described below. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor CexY is supplied to the driver IC 42 via the first switch Q1, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 42. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The third switch Q3 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q3 is turned off and the second switch Q2 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the second switch Q2 is turned off and the fourth switch Q4 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

The sixth switch to form a current path between the energy recovery circuit 41 and the driver IC 42 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by this energy recovery circuit 41. (Q6A, Q6B) remain on.

In this way, the energy recovery circuit 41 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym by using the external capacitor CexY. The energy recovery circuit 41 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period.

The scan reference voltage supply unit 46 includes a tenth switch Q10 connected between the third node n3 and the selective write scan voltage source (-Vyw), and the scan node of the third node n3 and the selective erase (-). 11A and 11B switches Q11A and Q11B connected in series between Vye. The tenth switch Q10 is switched in response to the control signal yw supplied in the address period of the selective write subfield WSF to supply the selective write scan voltage -Vyw to the driver IC 42. do. The 11A and 11B switches Q11A and Q11B are switched in response to the control signal ye supplied in the address period of the selective erasing subfield ESF to convert the selective erasing scan voltage (-Vye) into the driver IC 42. To serve.

The scan voltage supply 44 is composed of a seventh switch Q7 connected in series between the scan voltage source Vsc and the fourth node n4. The seventh switch Q7 is switched in response to the control signal SC supplied in the address periods of the selective write subfield WSF and the selective erase subfield ESF to transfer the scan voltage Vsc to the driver IC 42. It serves to supply. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows different voltage levels to be created in the erase scheme.

The setup supply 45 is composed of a third diode D3, a resistor R and a fifth switch Q5 connected between the setup voltage source Vsetup and the third node n3. The third diode D3 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The fifth switch Q5 serves to supply the setup waveform RP. The slope of this setup waveform RP is determined by the RC time constant value of the control terminal of the fifth switch Q5, that is, the RC time constant circuit connected to the gate terminal. Therefore, the slope of the setup waveform RP is adjusted by adjusting the resistance value of the variable resistor R1.

The setdown supply 43 includes a ninth switch Q9 connected between the third node n3 and the selective write scan voltage source -Vyw. The ninth switch Q9 serves to supply the setdown waveform (-RP). The slope of the set-down waveform (-RP) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the ninth switch Q9, that is, the gate terminal. Therefore, the slope of the set-down waveform (-RP) is adjusted by adjusting the resistance value of the variable resistor (R2).

The Y driver 32 includes an eighth switch Q8 connected to the scan reference voltage supply section 46 and the scan voltage supply section 44 via the third node n3 and the fourth node n4, respectively. The eighth switch Q8 switches the scan voltage Vsc supplied to the driver IC 42 in response to the control signal Dic_updn.

The eleventh switches Q11A and Q11B and the sixth switches Q6A and Q6B of the scan reference voltage supply unit 46 have the same function of switching in the same path, but are used in series by connecting the source terminals of each other. This is because a negative voltage is used. In brief, the negative voltage is applied to the third node n3 in the address period of the selective write and erase subfield. At this time, a problem occurs that the ground level is short due to the internal diode of the fourth switch Q4 of the energy recovery circuit 41. In order to prevent this, the sixth switch Q6 is formed in a state in which two field effect transistors Q6A and Q6B whose polarities are changed are connected in series. In addition, since the applied voltage (-Vw) of the selective write scan pulse SWSP has a voltage value lower than the applied voltage (-Ve) of the selective erase scan pulse SESP, the eleventh switch Q11 also has two electric fields whose polarities are changed. The effect transistors Q11A and Q11B are formed in series.

FIG. 7 is a view illustrating a driving waveform and a switch control signal according to the driving unit shown in FIG. 6. FIG. 8 is a diagram illustrating in detail the driving circuits of the set-down / selective write scan driver 56 and the scan reference voltage supply unit shown in FIG. 6.

Referring to FIGS. 7 and 8, during the reset period RPD of the selective write subfield SW, the ramp-down waveform is followed by the ramp-up waveform reset pulse RP in the scan / sustain electrode lines Y. Of reset pulses (-RP) are supplied sequentially.

When the fifth switch Q5 is turned on during the setup of the reset period RPD, the setup waveform RP is supplied. At this time, the slope of the setup waveform RP is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the fifth switch Q5, that is, the gate terminal.

Thereafter, the reset pulse (-RP) of the ramp-down waveform drops to the negative scan reference voltage (-Vw) when the reset period (RPD) is set down. At this time, the reset pulse (-RP) of the ramp-down waveform is a selective write scan voltage source (-Vyw) connected to the ninth switch Q9 when the ninth switch Q9 of the setdown supply unit 43 is turned on using the setdown signal. It is supplied by In addition, the slope of the reset pulse (-RP) of the ramp-down waveform is as shown in FIG. 8 to the RC time constant value of the RC time constant circuits Rd and Cd connected to the control terminal of the ninth switch Q9, that is, the gate terminal. Is determined by

In the address period APD of the selective write subfield, the seventh switch Q7 of the scan voltage supply unit 44 and the tenth switch Q10 of the scan reference voltage supply unit 46 are turned on to scan electrode lines Y. A negative (-) selective write scan pulse (SWSP) is supplied. The negative write (-) selective write scan pulse SWSP is supplied by the selective write scan voltage source -Vyw connected to the tenth switch Q10. The selective write scan pulse SWSP discharges an address in synchronization with the positive write data pulse SWDP of positive polarity supplied to the address electrode line X. The tenth switch Q10 is switched in response to the control signal yw supplied in the address period of the selective write subfield WSF, thereby supplying the selective write scan voltage -Vyw to the driver IC 42.

As described above, the voltage at which the reset pulse (-RP) of the ramp-down waveform falls during the set-down driving and the voltage applied to the scanning pulse SP during the addressing driving are also the negative scan voltage (-Vw). Thus, in the prior art, a driving circuit as shown in Fig. 8 is used to use a different pass for the applied voltage in the set down and address periods. This is because the ninth switch Q9 and the tenth switch Q10 are connected to the same node, but have a disadvantage in that a separate switch is used due to a difference in the inclination of the driving pulses during driving.

Accordingly, an object of the present invention is to provide a driving apparatus for a plasma display panel which reduces the number of switch elements used in each of set down and scan driving.

1 is a perspective view showing a typical three-electrode alternating surface discharge plasma display panel.

2 is a diagram showing a frame structure of a conventional plasma display panel.

3 is a view showing another configuration of one frame of a conventional plasma display panel.

FIG. 4 is a diagram illustrating a driving waveform of the PDP driving method according to the selective writing and erasing scheme of FIG. 3.

5 is a view schematically showing a driving apparatus of a general PDP.

6 is a view showing in detail the scan / sustain electrode driver according to the prior art;

FIG. 7 is a view for explaining a driving waveform and a switch control signal according to the driving unit shown in FIG. 6;

FIG. 8 is a diagram showing in detail the driving circuit of the set-down / selective write scan driver 56 shown in FIG.

9 is a view showing in detail the scan / sustain electrode driver in the driving apparatus of the PDP according to the first embodiment of the present invention;

FIG. 10 is a diagram for explaining driving waveforms and switching operations of a selective write subfield in the driving circuit shown in FIG.

FIG. 11 is a view showing in detail the driving circuit of the set-down / selective write scan driver shown in FIG. 9; FIG.

12 is a view showing in detail the scan / sustain electrode driver in the driving apparatus of the PDP according to the second embodiment of the present invention;

FIG. 13 is a diagram for explaining driving waveforms and switching operations of a selective write subfield in the driving circuit shown in FIG. 12; FIG.

FIG. 14 is a view showing in detail the driving circuit of the set-down / selective write scan driver shown in FIG. 12; FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan / sustain electrode

30Z: common sustain electrode 32: Y drive part

34: Z drive unit 36: X drive unit

41, 51, 61: energy recovery circuit 42, 52, 62: driver integrated circuit

43: scan reference voltage supply 44,54: scan voltage supply

45,55: setup voltage supply 46: set-down voltage supply

53,63: set-down / selective write scan driver 56,66: selective erase scan driver

In order to achieve the above object, an apparatus for driving a plasma display panel according to an embodiment of the present invention is divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. A driving apparatus of a plasma display panel for driving a light source, the apparatus comprising: an energy recovery circuit for recovering energy from a first electrode of the panel, the apparatus including a setup / down pulse during the reset period and selective writing for selecting the cell in the address period. A first electrode driver for supplying corresponding scan pulses and scan pulses corresponding to selective erasure to the first electrode; The first electrode driver includes a set down / selective write scan driver configured to selectively supply the set down pulse and the selective write scan pulse in response to a set down control signal and a selective write scan control signal, respectively.

In the present invention, the set-down / selective write scan driver includes a first switch element connected between the first electrode of the panel and a scan voltage source for selective writing, and a series between the gate terminal of the first switch element and the set-down control signal input source. A capacitor connected to the first and second resistors connected to the first and second resistors and the drain terminals of the first switch element, and configured to configure the first resistor and the RC time constant circuit to set the slope of the setdown pulse; And a third resistor connected between the gate terminal of the first switch element and the selective write scan control signal input source.

In the present invention, the resistance of the first resistor is about 2 to 10 kΩ, the resistance of the second resistor is about 10 kΩ, and the resistance of the third resistor is about 100 kΩ.

In the present invention, the first switch element is turned on at different times by the setdown control signal and the selective write control signal.

A plasma display panel driving apparatus according to another embodiment of the present invention is a plasma display for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. An apparatus for driving a panel, comprising: an energy recovery circuit for recovering energy from a first electrode of the panel, the setup / down pulse in the reset period, the scan pulse corresponding to the selective write to select the cell in the address period, and A first electrode driver configured to supply scan pulses corresponding to selective erasing to the first electrode; the first electrode driver continuously connects the setdown pulse and the selective write scan pulse in response to a setdown / selective write scan control signal; Set-down / selective write scan driver .

In the present invention, the set down / selective write scan driver includes a first switch element connected between a first electrode of the panel and a scan voltage source for selective writing, a gate terminal of the first switch element, and a set down / selective write scan control signal input. And a capacitor connected to the circle and connected to the drain terminal of the first resistor and the first switch element, and configured to configure the first resistor and the RC time constant circuit to set the slope of the setdown pulse.

The setdown / selective write scan control signal in the present invention is characterized by rising to a predetermined slope during the setdown driving and maintaining the final signal level during the setdown driving during the address period.

The first electrode driver according to the present invention is connected in a push-pull form so as to apply a voltage signal to the first electrode, and supplying a positive waveform setup signal having a ramp waveform to the first electrode during the reset period. And a second switch element connected between the energy recovery circuit and the setup driver and the scan driver for switching the setdown pulse and the sustain pulse, and between the scan driver and the scan voltage source, for an address period of a selective erase field. And an optional erasing scan driver for supplying a scan voltage to the scan driver.

The present invention includes an energy recovery circuit for recovering energy from the second electrode of the panel alternately with the first electrode driver, and a second electrode for supplying a DC voltage to the second electrode during selective writing and selective erasing. It has a drive part.

In the present invention, data for supplying any one of selective write data for selectively turning on the cell and selective erase data for selectively turning off the cell to the third electrode orthogonal to the first and second electrodes in an address period. It further comprises a drive unit.

In the present invention, it is connected between the energy recovery circuit and the set-up voltage source to maintain a constant lamp pulse voltage level, and is connected between the first capacitor and the scan voltage source and the scan driver to generate a ramp pulse, thereby reducing the scan pulse voltage level. A second capacitor may be further provided to maintain the constant and to adjust the voltage supplied to the scan driver.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 9 to 14.

The driving apparatus of the PDP according to the present invention includes a Y driver 32 for driving m scan / sustain electrode lines Y1 to Ym and m common sustain electrode lines Z1 to Zm as shown in FIG. 5. And a Z driver 34 for driving the N-axis, and an X driver 36 for driving the n address electrode lines X1 to Xn, which will be described based on a selective write and erase method.

The Y driver 32 initializes the full screen by supplying the setup / down waveforms (RP, -RP) in the selective write subfield (WSF) and at the selective write subfield (WSF) and the selective erase subfield (SEF). Different scan pulses -SWSP and -SESP are sequentially supplied to the scan / sustain electrode lines Y1 to Ym. In addition, the Y driver 32 supplies sustain pulses SUSPy in the selective write subfield WSF and the selective erase subfield ESF to generate sustain discharge.

The Z driver 34 is commonly connected to the common sustain electrode lines Z1 to Zm to apply the setdown waveform (-RPSZ), the scan DC voltage, and the sustain pulse (SUSZ) to the Z electrode lines Z1 to Zm. It serves to supply sequentially.

The X driver 104 supplies the write data pulse SWD or the erase data pulse SED to the address electrode lines X1 to Xn to be synchronized with the scan pulses -SWSCN and -SESCN.

9 shows the Y driver 32 in detail to explain the configuration and operation of the Y driver 32 in the plasma display panel according to the first embodiment of the present invention.

Referring to FIG. 9, the Y driver 32 includes sixth switches Q6A and Q6B connected between the energy recovery circuit 51 and the driver IC 52, sixth switches Q6A and Q6B and the driver IC ( 52, an optional erase scan driver 56 and a scan voltage supply 54 for generating a selective erase scan pulse (-SESP), sixth switches Q6A and Q6B and a selective erase scan driver 56; And a setup supply 55 and a set down / selective write scan to connect between the scan voltage supply 54 and generate a setup / down waveform (RP, -RP), as well as to generate a selective write scan pulse (-SWSP). The drive part 53 is provided. Also connected between the setup voltage source Vsetup and the energy recovery circuit 51 and between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vs constant. A second capacitor C2 connected in series is provided.

The driver IC 52 is connected in a push-pull form, and the twelfth and thirteenth switches Q12 to which a voltage signal is input from the energy recovery circuit 51, the set-down / selective write scan driver 53, and the scan voltage supply 54. Q13).

The output line between the twelfth and thirteenth switches Q12 and Q13 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 51 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q1 and Q2 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a third switch Q3 connected between the sustain voltage supply source Vs and the second node n2, and a second The fourth switch Q4 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 51 will be described below. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor CexY is supplied to the driver IC 52 via the first switch Q1, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 52. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The third switch Q3 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q3 is turned off and the second switch Q2 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the second switch Q2 is turned off and the fourth switch Q4 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

The sixth switch to form a current path between the energy recovery circuit 51 and the driver IC 52 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by this energy recovery circuit 51. (Q6A, Q6B) remain on.

In the address period of the selective write and erase subfield, the negative voltage is applied to the third node n3. At this time, a problem occurs that the ground level is short due to the internal diode of the fourth switch Q4 of the energy recovery circuit 51. In order to prevent this, the sixth switch Q6 is formed in a state in which two field effect transistors Q6A and Q6B whose polarities are changed are connected in series.

In this way, the energy recovery circuit 51 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym by using an external capacitor CexY. The energy recovery circuit 51 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period.

The selective erase scan driver 56 includes tenth and eleventh switches Q10 and Q11 connected in series between the third node n3 and the selective erase scan voltage source -Vye. The tenth and eleventh switches Q10 and Q11 are switched in response to the control signal ye supplied in the address period of the selective erasing subfield ESP, thereby transferring the selective erasing scan voltage (-Vye) to the driver IC 52. It serves to supply. Since the applied voltage (-Vw) of the selective write scan pulse SWSP has a lower voltage value than the applied voltage (-Ve) of the selective erase scan pulse SESP, the tenth and eleventh switches Q10 and Q11 also have polarities. The two changed field effect transistors are formed in series.

The scan voltage supply unit 54 is composed of a seventh switch Q7 connected in series between the scan voltage source Vsc and the fourth node n4. The seventh switch Q7 is switched in response to the control signal SC supplied in the address periods of the selective write subfield WSF and the selective erase subfield ESF to transfer the scan voltage Vsc to the driver IC 52. It serves to supply. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows different voltage levels to be created in the erase scheme.

The setup supply 55 is composed of a third diode D3, a resistor R and a fifth switch Q5 connected between the setup voltage source Vsetup and the third node n3. The third diode D3 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The fifth switch Q5 serves to supply the setup waveform RP. The slope of this setup waveform RP is determined by the RC time constant value of the control terminal of the fifth switch Q5, that is, the RC time constant circuit connected to the gate terminal. Therefore, the slope of the setup waveform RP is adjusted by adjusting the resistance value of the variable resistor R1.

The set down / selective write scan driver 53 includes a ninth switch Q9 connected between the third node n3 and the selective write scan voltage source -Vyw. The ninth switch Q9 supplies the set-down waveform (-RP) and switches in response to the control signal (yw) supplied in the address period of the selective write subfield (WSF), thereby switching the selective write scan voltage (-Vyw). It serves to supply the driver IC 52. The slope of this set-down waveform (-RP) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the ninth switch Q9, that is, the gate terminal. Therefore, the slope of the set-down waveform (-RP) is adjusted by adjusting the resistance value of the variable resistor (R2).

The Y driver 32 includes an eighth switch Q8 connected to the selective erase scan driver 56 and the scan voltage supply unit 54 via the third node n3 and the fourth node n4, respectively. The eighth switch Q8 switches the scan voltage Vsc supplied to the driver IC 52 in response to the control signal Dic_updn.

FIG. 10 is a diagram illustrating a driving waveform and a switch control signal according to the driving unit shown in FIG. 9.

Referring to FIG. 10, the reset pulse (-RP) and the selective write scan pulse (SWSP) of the ramp-down waveform during the set-down driving of the reset period and the addressing driving of the address period in one subfield may set one ninth switch Q9. It is applied by controlling. At this time, when the reset pulse (-RP) of the ramp-down waveform is applied and the selective write scan pulse (SWSP) is applied, the turn-on operation of the ninth switch Q9 is driven by different control signals.

FIG. 11 is a diagram illustrating in detail a driving circuit of the set-down / selective write scan driver shown in FIG. 9.

10 and 11, the set-down / selective write scan driver 53 includes a ninth switch Q9 connected between the sustain driver 57 and the selective write scan voltage source (-Vw), and a ninth switch. Resistors and first resistors Rd and R1 connected to the gate terminals of the switch Q9 and resistors R2 connected to the gate terminals of the ninth switch Q9 and connected in parallel to the resistors and the first resistors Rd and R1. And an RC time constant circuit connected to the drain terminal of the ninth switch Q9 and the node between the resistor and the first resistor Rd and R1 to determine the slope of the reset pulse (-RP) together with the resistor Rd. Capacitor Cd is provided.

As a result, the reset pulse (-RP) of the ramp-down waveform during the set down of the reset period (RPD) falls to the negative scan reference voltage (-Vw) as shown in FIG. The reset pulse (-RP) of the rampdown waveform is supplied by the selective write scan voltage source (-Vw) connected to the ninth switch Q9 when the ninth switch Q9 is turned on using the set down signal Set_down. Lose. At this time, the set-down signal Set_down is passed through the first resistor R1 and the ninth switch Q9 is input to the gate terminal. Here, the first resistor R1 is set to a value that supplies the set down signal Set_down to the gate terminal of the ninth switch Q9 without affecting the scan driving signal. In addition, the slope of the reset pulse (-RP) of the ramp-down waveform is determined by the RC time constant value of the RC time constant circuits Rd and Cd connected to the control terminal of the ninth switch Q9, that is, the gate terminal.

In the address period APD of the selective write subfield, the ninth switch Q9 is switched in response to a control signal yw supplied from the outside to supply the selective write scan voltage (-Vw) to the driver IC 42. do. The scan control signal yw is input to the gate terminal of the ninth switch Q9 through the second resistor R2. The second resistor R2 reduces the resistance so that the square wave is input to the gate without distortion. .

In the driving circuit configured as described above, the resistance value of the resistor Rd is 2 to 10 kV, the resistance value of the first resistor R1 is 10 kV, and the resistance value of the second resistor R2 is 100 kV. Is formed.

Thus, the Y driving unit in the plasma display panel according to the first embodiment of the present invention uses only one field effect transistor Q9 to reset the reset pulse (-RP) of the ramp-down waveform during set down and the scan pulse for selective writing during addressing driving ( SWSP) can be supplied.

12 illustrates the Y driver 32 in detail to explain the configuration and operation of the Y driver 32 in the plasma display panel according to the second embodiment of the present invention.

Referring to FIG. 12, the Y driver 32 includes sixth switches Q6A and Q6B connected between the energy recovery circuit 61 and the driver IC 62, sixth switches Q6A and Q6B and the driver IC ( A scan reference voltage supply unit 66 and a scan voltage supply unit 64 connected to each other to generate the selective erase scan pulse SESP, the sixth switches Q6A and Q6B and the selective erase scan driver 66; Connected between scan voltage supplies 64 to generate setup / down waveforms (RP, -RP), as well as setup supplies 65 and set-down / selective write scan drivers for generating selective write scan pulses (SWSP). 63). Also connected between the setup voltage source Vsetup and the energy recovery circuit 61, between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vs constant. A second capacitor C2 connected in series is provided.

The driver IC 62 is connected in a push-pull form, and the twelfth and thirteenth switches Q12 to which a voltage signal is input from the energy recovery circuit 61, the set-down / selective write scan driver 63, and the scan voltage supply unit 64. Q13).

The output line between the twelfth and thirteenth switches Q12 and Q13 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 61 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q1 and Q2 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a third switch Q3 connected between the sustain voltage supply source Vs and the second node n2, and a second The fourth switch Q4 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 61 will be described as follows. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor CexY is supplied to the driver IC 62 via the first switch Q1, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 62. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The third switch Q3 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q3 is turned off and the second switch Q2 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the second switch Q2 is turned off and the fourth switch Q4 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

The sixth switch to form a current path between the energy recovery circuit 61 and the driver IC 62 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by the energy recovery circuit 61. (Q6A, Q6B) remain on.

In the address period of the selective write and erase subfield, the negative voltage is applied to the third node n3. At this time, a problem occurs that the ground level is short due to the internal diode of the fourth switch Q4 of the energy recovery circuit 61. In order to prevent this, the sixth switch Q6 is formed in a state in which two field effect transistors Q6A and Q6B whose polarities are changed are connected in series.

In this manner, the energy recovery circuit 61 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym by using the external capacitor CexY. The energy recovery circuit 61 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period.

The selective erase scan driver 66 includes tenth and eleventh switches Q10 and Q11 connected in series between the third node n3 and the selective erase scan voltage source -Vye. The tenth and eleventh switches Q10 and Q11 are switched in response to the control signal ye supplied in the address period of the selective erasing subfield ESF to convert the selective erasing scan voltage -Vye into the driver IC 52. To serve. Since the applied voltage (-Vw) of the selective write scan pulse SWSP has a lower voltage value than the applied voltage (-Ve) of the selective erase scan pulse SESP, the tenth and eleventh switches Q10 and Q11 also have polarities. The two changed field effect transistors are formed in series.

The scan voltage supply unit 64 is composed of a seventh switch Q7 connected in series between the scan voltage source Vsc and the fourth node n4. The seventh switch Q7 is switched in response to the control signal SC supplied in the address periods of the selective write subfield WSF and the selective erase subfield ESF to transfer the scan voltage Vsc to the driver IC 62. It serves to supply. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows different voltage levels to be created in the erase scheme.

The setup supply 65 is composed of a third diode D3, a resistor R and a fifth switch Q5 connected between the setup voltage source Vsetup and the third node n3. The third diode D3 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The fifth switch Q5 serves to supply the setup waveform RP. The slope of the setup waveform RP is determined by the RC time constant value of the control terminal of the fifth switch Q5, that is, the RC time constant circuit connected to the gate terminal. Therefore, the slope of the setup waveform RP is adjusted by adjusting the resistance value of the variable resistor R1.

The set down / selective write scan driver 63 includes a ninth switch Q9 connected between the third node n3 and the selective write scan voltage source -Vyw. The ninth switch Q9 is switched in response to the control signal Set_down-yw which simultaneously serves as a setdown signal Set_down supplied at the time of setdown and a control signal yw supplied at the address period, thereby setting the setdown waveform (-RP). ), And supplies a selective write scan voltage (-Vyw) to the driver IC 62. The slope of the set-down waveform (-RP) is determined by the RC time constant value of the RC time constant circuits Rd and Cd connected to the control terminal of the ninth switch Q9, that is, the gate terminal.

The Y driver 32 includes an eighth switch Q8 connected to the scan reference voltage supply 66 and the scan voltage supply 64 via the third node n3 and the fourth node n4, respectively. The eighth switch Q8 switches the scan voltage Vsc supplied to the driver IC 62 in response to the control signal Dic_updn.

FIG. 13 is a view for explaining a driving waveform and a switch control signal according to the driving unit shown in FIG. 12.

Referring to FIG. 13, the reset pulse (-RP) and the selective write scan pulse (SWSP) of the ramp-down waveform during the set-down driving of the reset period and the addressing driving of the address period in one subfield are set to one ninth switch Q9. It is applied by controlling. At this time, when the reset pulse (-RP) of the ramp-down waveform is applied and the selective write scan pulse (SWSP) is applied, the turn-on operation of the ninth switch Q9 is driven and output by the same control signal Set_down-yw.

FIG. 14 is a diagram illustrating in detail a driving circuit of the set-down / selective write scan driver shown in FIG. 12.

13 and 14, the set-down / selective write scan driver 63 includes a ninth switch Q9 connected between the sustain driver 67 and the selective write scan voltage source (-Vw), and a ninth switch. RC clock connected between the resistor Rd connected to the gate terminal of the switch Q9 and the drain terminal and the gate terminal of the ninth switch Q9 to determine the slope of the reset pulse (-RP) together with the resistor Rd. The capacitor Cd constituting the male circuit is provided.

The gate input signal for driving the ninth switch Q9 in the driving apparatus of the plasma display panel according to the present invention rises with a slope by the RC time constant value of the RC time constant circuits Rd and Cd, and then after a certain time, Keep your level. Accordingly, when the reset pulse (-RP) of the ramp-down waveform is set on the reset period (RPD), when the ninth switch Q9 is turned on by using the gate control signal Set_down-yw gradually rising by the RC time constant value. The voltage drops to the negative scan reference voltage (-Vw).

Thereafter, when the gate control signal Set_down-yw keeps the high level, the ninth switch Q9 can maintain the turn-on state, so that the ninth switch Q9 is used for selective writing in the address period APD. The scan voltage (-Vw) can be supplied. This allows a normal addressing operation to be performed.

As a result, the Y driver in the plasma display panel according to the second embodiment of the present invention is selectively selected during the reset pulse (-RP) and the addressing driving of the ramp-down waveform during set-down with only one control signal and one field effect transistor Q9. It is possible to supply the write scanning pulse SWSP.

As described above, according to the driving apparatus of the plasma display panel according to the present invention, it is possible to reduce the number of switch elements used to supply the setdown voltage and the scan voltage respectively supplied to the subfields.

In addition, when supplying the setdown voltage and the scan voltage, it is possible to perform setdown and addressing driving using an RC time constant circuit and one control signal.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (18)

A driving apparatus of a plasma display panel for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of a selected cell, An energy recovery circuit for recovering energy from the first electrode of the panel, comprising: a setup / down pulse in the reset period, a scan pulse corresponding to selective write to select the cell in the address period, and a scan pulse corresponding to selective erase. A first electrode driver for supplying the first electrode to the first electrode; The first electrode driver includes a set down / selective write scan driver configured to selectively supply the set down pulse and the selective write scan pulse in response to a set down control signal and a selective write scan control signal, respectively. Device. The method of claim 1, The set-down / selective write scan driver includes: a first switch element connected between the first electrode of the panel and the scan voltage source for selective writing; First and second resistors connected in series between a gate terminal of the first switch element and a setdown control signal input source; A capacitor connected to the first and second resistors and a drain terminal of the first switch element, the capacitor configured to set a slope of a setdown pulse by configuring a first resistor and an RC time constant circuit; And a third resistor connected between the gate terminal of the first switch element and the selective write scan control signal input source. The method of claim 2, And the second resistor has a small resistance value for supplying the setdown signal to the gate terminal of the first switch element and not affecting the scan control signal. The method of claim 2, And the third resistor is larger than the second resistor. The method of claim 2, The resistance value of the first resistor is about 2 to 10㏀, The resistance value of the second resistor is about 10 kohms, And a resistance value of the third resistor is about 100 kW. The method of claim 1, A scan driver connected to the first electrode driver in a push-pull form to apply a voltage signal to the first electrode; A setup driver for supplying a positive setup signal in the form of a ramp waveform to the first electrode during the reset period; A second switch element connected between the energy recovery circuit and the setup driver and the scan driver for switching a setdown pulse and a sustain pulse; And a selective erase scan driver connected between the scan driver and a scan voltage source to supply a scan voltage to the scan driver during an address period of a selective erase field. The method of claim 1, And an energy recovery circuit for recovering energy from the second electrode of the panel, alternating with the first electrode driver, and having a second electrode driver for supplying a DC voltage to the second electrode during selective writing and selective erasing. Driving device for a plasma display panel, characterized in that. The method of claim 1, A data driver for supplying one of selective write data for selectively turning on the cell and selective erase data for selectively turning off the cell to the third electrode orthogonal to the first and second electrodes in the address period And a plasma display panel drive device. The method of claim 6, A first capacitor connected between the energy recovery circuit and a setup voltage source to maintain a constant lamp pulse voltage level and to generate a lamp pulse; And a second capacitor connected between the scan voltage source and the scan driver to maintain a constant scan pulse voltage level and to adjust a voltage supplied to the scan driver. The method of claim 2, And the first switch element is turned on at different times by the setdown control signal and the selective write control signal. The method of claim 2, And the set down pulse has a predetermined falling slope by an RC time constant circuit composed of the first resistor and the capacitor. A driving apparatus of a plasma display panel for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of a selected cell, An energy recovery circuit for recovering energy from the first electrode of the panel, comprising: a setup / down pulse in the reset period, a scan pulse corresponding to selective write to select the cell in the address period, and a scan pulse corresponding to selective erase. A first electrode driver for supplying the first electrode to the first electrode; And the first electrode driver comprises a set down / selective write scan driver configured to continuously supply the set down pulse and the selective write scan pulse in response to a set down / selective write scan control signal. The method of claim 12, The set-down / selective write scan driver includes: a first switch element connected between the first electrode of the panel and the scan voltage source for selective writing; A first resistor connected between the gate terminal of the first switch element and a set down / selective write scan control signal input source; And a capacitor connected to the first resistor and the drain terminal of the first switch element, and configured to configure a first resistor and an RC time constant circuit to set a slope of a setdown pulse. The method of claim 13, And the set down / selective write scan control signal rises to a predetermined slope during set down driving and maintains a final signal level during set down driving during an address period. The method of claim 13, A scan driver connected to the first electrode driver in a push-pull form to apply a voltage signal to the first electrode; A setup driver for supplying a positive setup signal in the form of a ramp waveform to the first electrode during the reset period; A second switch element connected between the energy recovery circuit and the setup driver and the scan driver for switching a setdown pulse and a sustain pulse; And a selective erase scan driver connected between the scan driver and a scan voltage source to supply a scan voltage to the scan driver during an address period of a selective erase field. The method of claim 13, And an energy recovery circuit for recovering energy from the second electrode of the panel, alternating with the first electrode driver, and having a second electrode driver for supplying a DC voltage to the second electrode during selective writing and selective erasing. Driving device for a plasma display panel, characterized in that. The method of claim 13, A data driver for supplying one of selective write data for selectively turning on the cell and selective erase data for selectively turning off the cell to the third electrode orthogonal to the first and second electrodes in the address period And a plasma display panel drive device. The method of claim 15, A first capacitor connected between the energy recovery circuit and a setup voltage source to maintain a constant lamp pulse voltage level and to generate a lamp pulse; And a second capacitor connected between the scan voltage source and the scan driver to maintain a constant scan pulse voltage level and to adjust a voltage supplied to the scan driver.