KR100426188B1 - Driving apparatus of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel for stably driving in a selective writing section using a rampdown waveform in a driving method for performing both selective writing and selective erasing.

A driving apparatus of a plasma display panel according to an embodiment of the present invention is a driving apparatus of a plasma display panel which drives a selective write subfield and a selective erase subfield in parallel, wherein the first and second sustain electrodes and the address electrode for generating a discharge are provided. A plasma display panel in which pixel cells formed at the intersections are arranged in a matrix, a reset / sustain pulse generator for supplying reset pulses and sustain pulses during a reset period and a sustain period, and between the panel and the reset / sustain pulse generators A reset down waveform generator for generating a reset down waveform at the time of set down of the reset period, and connected between a reset / sustain pulse generator and the reset down waveform generator, and With a diode to stabilize the drive It features.

According to the present invention, the driving apparatus of the plasma display panel stably operates the slope down operation during the set-down of the reset period by adding a diode to the driving circuit for generating the reset-down pulse, thereby preventing the heat generation occurring during the conversion from the set-up of the reset period to the set-down. Will be implemented.

Description

Driving device of plasma display panel {DRIVING APPARATUS OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to an apparatus and method for driving a plasma display panel in which a stable driving is performed in a selective writing section using a rampdown waveform in a driving method for performing both selective writing and selective erasing.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a conventional AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 12Y and a sustain electrode 12Z formed on an upper substrate 10, and an address electrode formed on a lower substrate 18. 20X).

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

These discharge cells are arranged in a matrix form as shown in FIG. In FIG. 2, the discharge cells 11 are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. The scan electrode lines Y1 to Ym are sequentially driven, and the sustain electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

The three-electrode AC surface discharge type PDP 30 is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period.

3 is a view showing a method of driving a plasma display panel according to the prior art.

Referring to FIG. 3, in the method of driving a three-electrode alternating surface discharge PDP, one frame includes subfields SF1 through SF6 of selective writing and subfields SF7 through SF12 of selective erasing. The first subfield SF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining discharge for the discharge cell selected by the address discharge, and an erasing period for canceling the sustain discharge. . Each of the second to fifth subfields SF2 to SF5 is divided into an optional write address period, a sustain period, and an erase period. The sixth subfield SF6 is divided into an optional write address period and a sustain period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2n in each subfield (n = 0, 1, 2, 3, 4). Is increased by 5). The seventh through twelfth subfields SF7 through SF12 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without a full surface writing period in which the full screen is lit. Divided into periods. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 25 to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must turn on the previous subfield so that unnecessary discharge cells can be turned off whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. To this end, the cells turned on in the sixth subfield WSF, which is the last selective write subfield WSF, must be turned on by the sustain discharge in order for the selective erase subfield ESF to be used. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off cells that are turned on in the previous subfield without front lighting.

4A and 4B are diagrams illustrating driving waveforms according to the PDP driving method illustrated in FIG. 3.

4A and 4B, in the reset period of the first selective write subfield SW1, the reset pulse RP of the ramp-down waveform is followed by the reset pulse RP of the ramp-up waveform in the scan electrode lines Y. RP) is supplied sequentially. At this time, the reset pulse (-RP) of this ramp down falls to the ground (GND) in Figure 4a, and to the negative scan reference voltage (-Vw) in Figure 4b. In addition, the scan electrode voltage DCSC having a positive polarity is supplied to the sustain electrode lines Z.

In the address period of the selective write subfield SW1, the scan electrode lines Y and the address electrode lines X are respectively applied to the sustain electrode lines Z while the positive scan DC voltage DCSC is supplied. In 0V, a selective write scan pulse (SWSP) of 0 V and a selective write data pulse (SWDP) of positive polarity (+) are supplied in synchronization with each other. In addition, in FIG. 4B, a negative write negative scan pulse (-SWSP) and a positive write positive data pulse (SWDP) are formed on the scan electrode lines Y and the address electrode lines X, respectively. It is supplied to be synchronized with each other. The address discharge is performed by the selective write scan pulse SWSP and the optional data pulse SWDP as described above.

Sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z so that sustain discharge occurs for the cells turned on by the address discharge of the selective write subfield SW. . At the end of the second selective write subfield SW2, the erase pulse EP is supplied to the scan electrode lines Y to erase the sustain discharge.

The reset period of the selective erase subfield SE is omitted. In the address period of the selective erase subfield SE, the selective erase scan pulse SESP of the OV for turning off the cell in each of the scan electrode lines Y and the address electrode lines X and the selective erase of the positive polarity (+) are performed. The data pulses SEDP are supplied to be synchronized with each other. In addition, in FIG. 4B, the negative erase (-SESP) and the positive erase (+ DP) positive erase data pulses SEDP for turning off the cell are supplied to be synchronized with each other. The selective erase scan pulse (-SESP) drops to the selective erase scan voltage (-Ve) higher than the scan reference voltage (-Vw).

Sustain pulses SUSPy and SUSPz are alternately supplied to scan electrode lines Y and sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by the address discharge of the selective erase subfield SE. do. When the next subfield is a selective erase field SE, a sustain pulse SUSPy having a relatively large pulse width is supplied to the scan electrode lines Y at the end of the current selective erase subfield SE. The erase pulse EP and the ramp signal RAMP are supplied to the scan electrode lines Y and the sustain electrode lines Z in the last selective erase subfield in which the next subfield is the selective write subfield SW. Clear the sustain discharge of the cells.

FIG. 5 is an enlarged view of a reset pulse waveform applied to a reset period in the driving waveform of FIG. 4A. FIG. 6 is a diagram illustrating a driving circuit for driving a reset pulse at set down of FIG. 5.

5 and 6, the driving circuit for driving the reset pulse of the PDP includes a sustain / reset pulse generator 40, a reset down pulse generator 42, and a panel Cp.

The sustain / reset pulse generator 40 supplies the reset voltage and the sustain voltage to the scan electrode Y and the sustain electrode Z during the reset period and the sustain period to cause reset discharge and sustain discharge.

The reset down pulse generator 42 is derived from the first node 41 between the sustain / reset pulse generator 40 and the panel Cp. The reset down pulse generator 42 includes a switch SW for inputting a set down signal into a circuit; The switch element Q is connected between the switch SW, the first node 41 and the ground voltage source GND to act as a switch, and is connected between the switch SW and the gate of the switch element Q, The resistance element Rd for controlling the slope slope of the input pulse voltage input from SW) is connected between the gate and the drain of the switch element Q to form an RC resonance circuit together with the resistance element Rd to form a resonance waveform. Capacitor Cd is provided.

Referring to the operation thereof, when the square wave type reset down input signal SDSW is input through the switch SW, the second node 43 becomes a pulse gradually increasing by the RC integrating circuit. As the gate signal gradually increases, the driving time is gradually progressed until the switch element Q becomes saturated, resulting in a gradually decreasing waveform as shown in FIG. 5.

FIG. 7 is an enlarged view of the reset pulse waveform applied to the reset period in the driving waveform shown in FIG. 4B. FIG. 8 is a diagram illustrating a driving circuit for driving a reset pulse at set down of FIG. 7.

7 and 8, a driving circuit for driving a reset pulse of the PDP includes a sustain / reset pulse generator 44, a reset down pulse generator 46, and a panel Cp.

The sustain / reset pulse generator 44 supplies the reset voltage and the sustain voltage to the scan electrode Y and the sustain electrode Z during the reset period and the sustain period to cause reset discharge and sustain discharge.

The reset down pulse generator 46 is derived from the first node 45 between the sustain / reset pulse generator 44 and the panel Cp. The reset down pulse generator 46 includes a switch SW for inputting a set down signal into a circuit; Connected between the switch SW, the first node 45, and the scan reference voltage source (-Vw), the switch element Q acting as a switch, and the gate between the switch SW and the gate of the switch element Q. The resistor Rd for controlling the slope slope of the input pulse voltage input from the switch Q is connected between the gate and the drain of the switch element Q to form an RC resonant circuit together with the resistor Rd to resonate. Capacitor Cd is provided to generate a waveform.

Its operation is driven in the same manner as described in FIG.

However, problems occur in addition to the basic driving operation. Before the set-down operation starts, the reset voltage Vreset is applied to the first nodes 41 and 45. When the voltage applied as much as the ramp wave is turned off, the voltage directly changes from the reset voltage Vreset to the base voltage Vb. The voltage change at this time adversely affects the capacitor Cd. That is, since the capacitor Cd is charged with the reset voltage Vreset and suddenly causes a charge drop to the base voltage Vb, a heat generation phenomenon is generated to withstand this. This heating phenomenon can change the characteristics of the capacitor (Cd), and if the value of the capacitor (Cd) is changed, the RC time constant configured with the resistance element (Rd) is changed accordingly, so that the set-down slope is also linked, resulting in poor image quality. do.

Accordingly, it is an object of the present invention to provide a driving apparatus of a plasma display panel that is stably driven during set down of a reset period by adding one diode to a driving circuit for generating a reset down pulse.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a layout view of electrodes of the plasma display panel shown in FIG. 1. FIG.

3 is a frame diagram illustrating a method of driving a subfield of a plasma display panel.

4A and 4B are driving waveform diagrams of the prior art for driving the plasma display panel according to the frame configuration diagram in FIG. 3 for one frame;

FIG. 5 is an enlarged view of a reset pulse waveform applied to a reset period in the driving waveform shown in FIG. 4A; FIG.

FIG. 6 is a view showing a driving circuit for driving a reset pulse at set down in FIG. 5; FIG.

FIG. 7 is an enlarged view of a reset pulse waveform applied to a reset period in the driving waveform shown in FIG. 4B. FIG.

FIG. 8 is a view showing a driving circuit for driving a reset pulse at set down in FIG.

FIG. 9 is a view showing a driving device of a PDP for generating a reset pulse of a ramp-down type according to the first embodiment of the present invention in the driving waveform shown in FIG. 4A; FIG.

FIG. 10 is a view showing a driving device of a PDP for generating a reset pulse of a ramp-down type according to the second embodiment of the present invention in the driving waveform shown in FIG. 4A; FIG.

FIG. 11 is a view showing a driving device of a PDP for generating a reset pulse of a ramp-down type according to the third embodiment of the present invention in the driving waveform shown in FIG. 4B; FIG.

FIG. 12 is a view showing a driving device of a PDP for generating a reset pulse of a ramp-down type according to the fourth embodiment of the present invention in the driving waveform shown in FIG. 4B; FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 11: discharge cell

12Y: scan electrode 12Z: sustain electrode

14 upper dielectric layer 16 protective film

18: lower substrate 20X: address electrode

22: lower dielectric layer 24: partition wall

26 phosphor 30 PDP

40,44,50,54,60,64: sustain / reset pulse generator

41,45,51,55,61,65; First node 43,47,53,57,63,67: second node

42,46,52,56,62,66: Reset down pulse generator

In order to achieve the above objects, a driving apparatus of a plasma display panel according to the present invention is a driving apparatus of a plasma display panel which drives a selective write subfield and a selective erase subfield in parallel, the first and second for generating a discharge. A plasma display panel in which pixel cells formed at intersections of the sustain electrodes and the address electrodes are arranged in a matrix, a reset / sustain pulse generator for supplying reset pulses and sustain pulses in the reset period and the sustain period; A reset down waveform generation section derived from a reset / sustain pulse generating section for generating a reset down waveform when the reset period is set down, and connected between the reset / sustain pulse generating section and the reset down waveform generation section to reset the sustain period; The reset down waveform generator A diode is provided for stabilizing driving.

Here, the reset down waveform generator includes a switch for inputting a set down signal into the reset down pulse generator, a switch element connected between the switch and the base voltage source to act as a switch, and a reset down pulse connected between the switch and the switch element. And a capacitor connected between the gate and the drain of the switch element to form a resonance circuit to form a resonance circuit together with the resistance element.

Here, the other reset down waveform generator includes a switch for inputting a set down signal into the reset down pulse generator, a switch element connected between the switch and the scan reference voltage source to perform a switch function, and the switch and the switch. A resistance element connected between the elements to control the slope of the reset down pulse, and a capacitor connected between the gate and the drain of the switch element to form a resonance circuit together with the resistance element to generate a resonance waveform. It is done.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 9 to 12.

FIG. 9 is a diagram illustrating a driving device of a PDP for generating a reset pulse of a ramp-down type according to the first embodiment of the present invention in the driving waveform shown in FIG. 4A.

Referring to FIG. 9, the driving circuit for driving the reset pulse of the PDP includes a sustain / reset pulse generator 50, a reset down pulse generator 52, and a panel Cp. In addition, a diode Db is provided inside the reset-down pulse generator 52.

The sustain / reset pulse generator 50 supplies the reset voltage and the sustain voltage to the scan electrode Y and the sustain electrode Z during the reset period and the sustain period to cause reset discharge and sustain discharge.

The reset down pulse generator 52 is derived from the first node 51 between the sustain / reset pulse generator 50 and the panel Cp. The reset down pulse generator 52 includes a switch SW for inputting a set down signal into a circuit; The switch element Q is connected between the switch SW, the first node 51 and the ground voltage source GND to act as a switch, and is connected between the switch SW and the gate of the switch element Q, The resistance element Rd for controlling the slope slope of the input pulse voltage SDSW input from SW is connected between the gate and the drain of the switch element Q to form an RC resonance circuit together with the resistance element Rd. Capacitor Cd is provided to generate a resonance waveform. In addition, the diode Db is connected in series with the capacitor Cd between the gate and the drain of the switch element so as to block the heating of the internal circuit due to a sudden voltage drop.

Referring to the operation thereof, when the reset voltage Vreset is applied during the setup of the reset period, since the diode Db is in the on state, the capacitor Cd is charged with the reset voltage Vreset and then the first node 51. The reset voltage Vreset is maintained by the diode Cb in the capacitor Cd even when the reset voltage Vreset is turned off and only the base voltage Vb is applied. Therefore, since the constant voltage is maintained in the capacitor Cd during the set-down of the reset period, the slope slope is kept stable with a constant RC time constant. Since the slope slope is the source of the switch element Q is connected to the ground (GND), the reset down pulse of the reset period is a voltage drop to 0V in Fig. 4a.

FIG. 10 is a diagram illustrating a driving device of a PDP for generating a reset pulse of a ramp-down type according to the second embodiment of the present invention in the driving waveform shown in FIG. 4A.

Referring to FIG. 10, a driving circuit for driving a reset pulse of a PDP includes a sustain / reset pulse generator 54, a diode Db, a reset down pulse generator 56, and a panel Cp.

The sustain / reset pulse generator 54 supplies the reset voltage and the sustain voltage to the scan electrode Y and the sustain electrode Z during the reset period and the sustain period to cause reset discharge and sustain discharge.

The diode Db is connected between the first node 55 and the reset down pulse generator 56 so that heat generation occurs in the capacitor Cd in the reset down pulse generator 56 due to the voltage drop during the set down of the reset period. It prevents it from happening.

The reset down pulse generator 56 is connected to the diode Db, and has a switch SW for inputting a set down signal into the circuit; A switch element Q connected between a switch SW, a diode Db, and a ground voltage source GND, and acting as a switch, and a switch SW connected between a switch SW and a gate of the switch element Q. The resonant waveform is formed between the resistor Rd for controlling the slope slope of the input pulse voltage SDSW input from the gate and the gate and the drain of the switch element Q to form an RC resonant circuit together with the resistor Rd. And a capacitor Cd for generating

Looking at the operation thereof, when the reset voltage (Vreset) is applied during the setup of the reset period, since the diode (Db) is on (On), the capacitor (Cd) is charged with the reset voltage (Vreset), and the reset voltage (Vreset) when set down ) Is turned off, only the base voltage Vb is applied, and the switch element Q is turned on. Since the reset voltage Vreset is charged in the drain of the switch element Q, there is no voltage change at the first node while the reset voltage Vreset is down to the base voltage Vb, and the drain of the switch element Q is connected to the base. After the voltage Vb is lowered, the voltage of the first node 55 starts to slope down. Therefore, since the constant voltage is maintained in the capacitor Cd during the set-down of the reset period, the slope slope is kept stable with a constant RC time constant. Since the slope slope is the source of the switch element Q is connected to the ground, the reset down pulse in the reset period is a voltage drop to 0V in Fig. 4a.

FIG. 11 is a diagram illustrating a driving device of a PDP for generating a reset pulse of a ramp-down type according to the third embodiment of the present invention in the driving waveform shown in FIG. 4B.

Referring to FIG. 11, the driving circuit for driving the reset pulse of the PDP includes a sustain / reset pulse generator 60, a reset down pulse generator 62, and a panel Cp. In addition, a diode is provided inside the reset-down pulse generator 62.

The sustain / reset pulse generator 60 supplies the reset voltage and the sustain voltage to the scan electrode Y and the sustain electrode Z during the reset period and the sustain period to cause reset discharge and sustain discharge.

The reset down pulse generator 62 is derived from the first node 61 between the sustain / reset pulse generator 60 and the panel Cp. The reset down pulse generator 62 includes a switch SW for inputting a set down signal into a circuit; Is connected between the switch SW, the first node 61 and the scan reference voltage source (-Vw), and is connected between the switch element Q and the gate of the switch SW and the switch element Q. The resistance element Rd for controlling the slope slope of the input pulse voltage SDSW input from the switch SW is connected between the gate and the drain of the switch element Q to form an RC resonant circuit together with the resistance element Rd. And a capacitor Cd to form a resonance waveform. In addition, the diode Db is connected in series with the capacitor Cd between the gate and the drain of the switch element Q.

Referring to the operation thereof, when the reset voltage Vreset is applied during the setup of the reset period, since the diode Db is in the on state, the capacitor Cd is charged with the reset voltage Vreset and then the first node 61. The reset voltage Vreset is maintained by the diode Cb in the capacitor Cd even when the reset voltage Vreset is turned off and only the base voltage Vb is applied. Therefore, since the constant voltage is maintained in the capacitor Cd during the set-down of the reset period, the slope slope is kept stable with a constant RC time constant. Since the slope slope is connected to the scan reference voltage source (-Vw) the source of the switch element Q, the reset down pulse in the reset period is a voltage drop to the negative scan reference voltage (-Vw) in Figure 4b.

FIG. 12 is a diagram illustrating a driving device of a PDP for generating a reset pulse of a ramp-down type according to the fourth embodiment of the present invention in the driving waveform shown in FIG. 4B.

Referring to FIG. 12, the driving circuit for driving the reset pulse of the PDP includes a sustain / reset pulse generator 64, a diode Db, a reset down pulse generator 66, and a panel Cp.

The sustain / reset pulse generator 64 supplies the reset voltage and the sustain voltage to the scan electrode Y and the sustain electrode Z during the reset period and the sustain period to cause reset discharge and sustain discharge.

The diode Db is connected between the first node 65 and the reset down pulse generator 66 to generate heat in the capacitor Cd in the reset down pulse generator 66 due to the voltage drop during the set down of the reset period. Serves to prevent it from happening.

The reset down pulse generator 66 is connected to the diode Db and has a switch SW for inputting a set down signal into the circuit; The switch element Q is connected between the switch SW, the diode Db and the scan reference voltage source -Vw to act as a switch, and is connected between the switch SW and the gate of the switch element Q, The resistance element Rd for controlling the slope slope of the input pulse voltage SDSW input from SW is connected between the gate and the drain of the switch element Q to form an RC resonance circuit together with the resistance element Rd. Capacitor Cd is provided to generate a resonance waveform.

Looking at the operation thereof, when the reset voltage (Vreset) is applied during the setup of the reset period, since the diode (Db) is on (On), the capacitor (Cd) is charged with the reset voltage (Vreset), and the reset voltage (Vreset) when set down ) Is turned off, only the base voltage Vb is applied, and the switch element Q is turned on. Since the reset voltage Vreset is charged in the drain of the switch element Q, there is no voltage change at the first node 65 while the reset voltage Vreset is down to the base voltage Vb. After the drain is lowered to the base voltage Vb, the voltage of the first node 65 starts to slope down. Therefore, since the constant voltage is maintained in the capacitor Cd during the set-down of the reset period, the slope slope is kept stable with a constant RC time constant. Since the slope slope is the source of the switch element is connected to the scan reference voltage source (-Vw), the reset down pulse in the reset period is a voltage drop to the negative scan reference voltage (-Vw) in Figure 4b.

As described above, the driving apparatus of the PDP according to the present invention reliably prevents the heat generation occurring during the conversion from the set-up of the reset period to the set-down by adding a diode to the driving circuit for generating a conventional reset down pulse. We will implement the slope down operation.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A driving apparatus of a plasma display panel for driving a selective write subfield and a selective erase subfield in parallel. A plasma display panel in which pixel cells formed at intersections of first and second sustain electrodes and an address electrode for generating a discharge are arranged in a matrix form; A reset / sustain pulse generator for supplying reset pulses and sustain pulses in the reset period and the sustain period; A reset down waveform generator derived from the panel and a reset / sustain pulse generator to generate a reset down waveform when the reset period is set down; And a diode connected between the reset / sustain pulse generator and the reset down waveform generator to stabilize driving of the reset down waveform generator when set down in the setup of the reset period. Drive system. The method of claim 1, The reset down waveform generator comprises a switch for inputting a set down signal into the reset down pulse generator; A switch element connected between the switch and a ground voltage source to perform a switch action; A resistance element connected between the switch and the switch element to control the inclination of the reset down pulse; And a capacitor connected between the gate and the drain of the switch element to form a resonance circuit together with the resistance element to generate a resonance waveform. The method of claim 1, The reset down waveform generator comprises a switch for inputting a set down signal into the reset down pulse generator; A switch element connected between the switch and a scan reference voltage source to perform a switch action; A resistance element connected between the switch and the switch element to control the inclination of the reset down pulse; And a capacitor connected between the gate and the drain of the switch element to form a resonance circuit together with the resistance element to generate a resonance waveform. The method of claim 2, And the diode is connected in series with the capacitor between the gate and the drain of the switch element. The method of claim 2, And the diode is derived from between the reset / sustain pulse generating unit and the panel and is connected between the reset down pulse generating unit. The method of claim 3, wherein And the diode is connected in series with the capacitor between the gate and the drain of the switch element. The method of claim 3, wherein And the diode is derived from between the reset / sustain pulse generating unit and the panel and is connected between the reset down pulse generating unit.