KR100429869B1 - CMOS Integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same - Google Patents

Abstract

CMOS integrated circuit devices include an electrically insulating layer and an unmodified active layer on the electrically insulating layer. An insulating gate electrode is also provided on the surface of the unmodified silicon active layer. In addition, a Si _1-x Ge _x layer is disposed between the electrically insulating layer and the unmodified silicon active layer. The Si _1-x Ge _x layer forms a first junction with the unmodified silicon active layer, in which germanium has a sloped concentration that monotonously decreases from the peak level toward the surface of the unmodified silicon active layer. The peak concentration level of germanium is at least x = 0.15, and the concentration of germanium in the Si _1-x Ge _x layer varies from the peak level to a level of x = 0.1 or less at the first junction. The concentration of germanium at the first junction may be steep. The concentration of germanium in the Si _1-x Ge _x layer varies from a peak level of 0.2 <x <0.4 to a level of x = 0 at the first junction. The Si _1-x Ge _x layer also has a arsenic doping profile retrologated therein with respect to the surface. This retranslated profile results in a Si _1-x Ge _x layer having a concentration of the first conductivity type dopant therein as compared to the concentration of the first conductivity type dopant in the channel region in the unmodified silicon active layer. The total amount of dopant in the channel region and in the lower Si _1-x Ge _x layer can be carefully controlled to obtain the desired threshold voltage.

Description

CMOS integrated circuit devices and substrates having a buried silicon germanium layer and a method of manufacturing the same {COMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a MOS semiconductor device and a substrate and a method of forming the same.

Partially-depleted Silicon-On-Insulator (PDSOI) MOSFETs offer high speed and low power performance, but are typically susceptible to parasitic floating body effects (FBEs) that seriously degrade device performance. Do. Several techniques have been proposed to reduce floating body effects in SOI MOSFETs. One of the techniques is the use of a narrow gap silicon germanium (SiGe) layer adjacent to the source of a SOI NMOS field effect transistor. As will be readily appreciated by those skilled in the art, the use of a silicon germanium layer reduces the potential barrier for holes passing from the body region to the source region. Therefore, holes generated in the sea region by impact ionization can easily flow into the source region through the path of p-Si (body) / n + SiGe (source) / n + Si (source). These and other related technologies are Jay. J. Sim et al., "Elimination of Parasitic Bipolar-Induced Breakdown Effects in Ultra-Thin SOI MOSFETs Using Narrow-Bandgap-Source (NBS) Structure" (IEEE Trans.Elec. Dev., Vol. 42, No. 8, pp. 1495-1502, August 1995), "Suppression of the Floating-Body Effect in SOI MOSFETs by the Bandgap Engineering Method Using a Si _1-x Ge" by M. Yoshimi et al. _x Source Structure "(IEEE Trans. Elec. Dev., Vol. 44, No. 3, pp. 423-429, March 1997). U.S. Patent No. 5,698,869, entitled "Insulated-Gate Transistor Having Narrow-Bandgap-Source," to Yoshimi et al. Also discloses the use of a narrow bandgap material in the source region of a MOSFET.

Techniques for reducing FBE and improving channel characteristics in MOSFETs are disclosed in US Pat. No. 5,891,769, entitled "Method for Forming a Semiconductor Device Having a Heteroepitaxial Layer," to Liau et al. In particular, the '769 patent discloses the use of modified channel regions to enhance carrier mobility in MOSFETs. This strained channel region can be formed by growing a silicon layer on a relaxed or unmodified silicon germanium layer in an as-grown state. U.S. Patent No. 5,963,817, entitled "Bulk and Strained Silicon on Insulator Using Selective Oxidation," to Chu et al. Doing. Further, US Pat. Nos. 5,906,951 and 6,059,895 to Mr. Chu et al. Disclose SiGe layers modified to provide wafer bonding techniques and SOI substrates. The use of silicon germanium layers to provide wafer bonding techniques and SOI substrates is also disclosed in US Pat. Nos. 5,218,213 and 5,240,876 to Mr. Gaul et al. Conventional techniques for forming an SOI substrate are shown in FIGS. 1A-1D-2A-2D. In particular, FIG. 1A shows the formation of a handling substrate 110 having a porous silicon layer 112 therein and an epitaxial silicon layer 114 thereon. 1B shows the adhesion of the supporting substrate 120 to the surface of the epitaxial silicon layer 114. The supporting substrate 120 may be formed thereon with an oxide layer 122 directly contacting the epitaxial silicon layer 114 using conventional techniques. Subsequently, as shown in FIG. 1C, a portion of the handling substrate 110 is removed to expose the porous silicon layer 112. This removing step may be performed by grinding or etching part of the handling substrate 110 or by separating the porous silicon layer 112. As shown in FIG. 1D, a general planarization technique is then performed to remove the porous silicon layer 112 to provide an SOI substrate having an oxide layer 122 embedded therein and a silicon layer 114 polished thereon. . The prior art shown in FIGS. 1A-1D is generally known as an epi-layertransfer (ELTRAN) technique.

FIG. 2A shows the formation of a handling substrate 130 with a silicon layer 130 ′ on it by implanting hydrogen ions into the surface of the substrate to define a hydrogen implanted layer 132 embedded therein. 2B, the supporting substrate 120 is adhered to the handling substrate. A portion of the handling substrate 132 is then removed by removing the adhered substrate along the hydrogen injection layer 132, as shown in FIG. 2C. As shown in FIG. 2D, a general planarization technique is performed to remove the hydrogen injection layer 132. This conventional technique, shown in FIGS. 2A-2D, is generally known as a "smart-cut" technique.

Unfortunately, although the use of strained silicon channel regions promotes carrier mobility in both NMOS and PMOS devices, such strained regions generally degrade short channel device characteristics. Thus, improved methods and structures formed by forming substrates that do not require the use of modified channel regions to ensure enhanced channel mobility characteristics despite the foregoing techniques for forming MOSFET and SOI substrates. The demand for it continues.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and relates to a MOS-based semiconductor device, a substrate, and a method of forming the same, which do not require the use of a modified channel region to secure enhanced channel mobility characteristics. will be.

1A to 1D are cross-sectional views of an intermediate structure showing a method of forming a conventional semiconductor on-insulator (SOI) substrate.

2A-2D are cross-sectional views of an intermediate structure showing a method of forming a conventional SOI substrate.

3A-3E are cross-sectional views of an intermediate structure showing a method of forming an SOI substrate having a SiGe layer therein in accordance with one embodiment of the present invention.

4A-4E are cross-sectional views of an intermediate structure showing a method of forming an SOI substrate having a SiGe layer therein in accordance with one embodiment of the present invention.

5 is a flow diagram of process steps illustrating a preferred method of forming SOI field effect transistors in accordance with one embodiment of the present invention.

6A-6E are cross-sectional views of intermediate structures illustrating a method of forming SOI-based MOS transistors in accordance with one embodiment of the present invention.

FIG. 7A is a graph of substrate depth prior to annealing versus N-type dopant concentration for conventional SOI substrates, in which phosphorus and arsenic dopants were implanted with energy of 30 KeV and 200 KeV, respectively.

FIG. 7B is a graph of substrate depth after annealing versus N-type dopant concentration for a conventional SOI substrate, with the dopant profile before annealing shown in FIG. 7A.

FIG. 7C is a graph of substrate depth versus N-type dopant concentration for a preferred SOI substrate having a SiGe layer inserted therein, with phosphorus and arsenic dopants implanted at energies of 30 KeV and 200 KeV, respectively.

FIG. 7D is a graph of substrate depth versus N-type dopant concentration for a preferred SOI substrate having a SiGe layer inserted therein, the dopant profile before annealing is shown in FIG. 7C.

Embodiments of the present invention include a semiconductor-on-insulator (SOI) substrate having an embedded Si _1-x Ge _x layer therein. An SOI substrate according to an embodiment of the present invention includes a silicon wafer having an electrical insulating layer thereon and a Si _1-x Ge _x layer extending on the electrical insulating layer and having a concentration in which germanium is inclined therein. do. An unmodified silicon active layer is also provided in the SOI substrate. This unmodified silicon active layer extends over and bonds with the Si _1-x Ge _x layer. The unmodified silicon active layer also preferably extends to the surface of the SOI substrate so that integrated circuit devices can be formed on the surface of the silicon active layer. In order to facilitate the use of a relatively thin silicon active layer, the Si _1-x Ge _x layer is preferably epitaxially grown from an unmodified silicon active layer. This epitaxial growth step provides an unmodified silicon active layer (or initially epitaxially grows an unmodified silicon active layer on the substrate) and then slopes the germanium to be inclined until a maximum desired germanium concentration is obtained. Increasing the concentration continues the growth of the Si _1-x Ge _x layer on the active layer. Subsequently, further growth can occur by reducing the concentration of germanium in an oblique manner to x = 0. The inclination of germanium in the Si _1-x Ge _x layer may be linear inclination.

Preferred SOI substrates can be fabricated by initially forming a handling substrate having an unmodified silicon layer therein and an Si _1-x Ge _x layer extending on the silicon layer. A supporting substrate is then bonded to the handling substrate such that a Si _1-x Ge _x layer is disposed between the supporting substrate and the unmodified silicon layer. Subsequently, a portion of the handling substrate is preferably removed from the supporting substrate to expose the surface of the silicon layer and form an SOI substrate having an embedded Si _1-x Ge _x layer therein. Here, the buried Si _1-x Ge _x layer preferably has a concentration of inclined germanium having a profile that decreases in a direction extending from the supporting substrate to the surface of the silicon layer.

These methods also include a first silicon layer unmodified therein, an Si _1-x Ge _x layer extending on the first silicon layer and an unmodified or modified second silicon extending on the Si _1-x Ge _x layer. Forming a handling substrate having a layer. In addition, the step of thermally oxidizing the second silicon layer to form a thermal oxide layer on the Si _1-x Ge _x layer before the bonding step. In addition, the supporting substrate may include an oxide surface layer thereon, and the bonding may include adhering the oxide surface layer to the thermal oxide layer. Alternatively, the step of depositing an electrical insulating layer on the Si _1-x Ge _x layer may be performed prior to the bonding step, wherein the bonding step comprises adhering the oxide surface layer to the electrical insulating layer. It may include.

According to another preferred method of forming an SOI substrate, the handling substrate may comprise a porous silicon layer therein, wherein the removing step removes a portion of the handling substrate from the supporting substrate by separating the porous silicon layer. And subsequently planarizing the porous silicon layer and the silicon layer. A preferred method of forming a handling substrate is to epitaxially grow a Si _1-x Ge _x layer on a silicon layer, and then use the Si _1-x Ge _x layer and the silicon layer to form a hydrogen injection layer in the handling substrate. And implanting hydrogen ions therethrough. The removing step may be performed by separating the hydrogen injection layer and planarizing the hydrogen injection layer to expose the surface of the silicon layer. Semiconductor devices including field effect transistors may be formed on the surface of the silicon layer.

Additional embodiments of the present invention include SOI field effect transistors. Such transistors include an electrically insulating layer and an unmodified silicon active layer on the electrically insulating layer. In addition, an insulated gate electrode is provided on the surface of the unmodified silicon active layer. In addition, a Si _1-x Ge _x layer is disposed between the electrical insulating layer and the unmodified silicon active layer. The Si _1-x Ge _x layer forms a first junction with the unmodified silicon active layer, in which germanium monotonically decreases from the peak level in a first direction extending toward the surface of the unmodified silicon active layer. Have an inclined concentration. According to one form of this embodiment, the peak germanium concentration level is greater than x = 0.15 and the concentration of germanium in the Si _1-x Ge _x layer is greater than about x = 0.1 at the first junction from the peak level. Change up to a small level. The concentration of germanium in the first junction may be steep. More preferably, the concentration of germanium in the Si _1-x Ge _x layer varies from a peak level of 0.2 <x <0.4 to a level of x = 0 at the first junction.

In addition, the Si _1-x Ge _x layer forms an interface with the lower electrical insulating layer, and the concentration of the inclined germanium in the Si _1-x Ge _x layer may be different from that of the electrical insulating layer. It may increase from the level less than about x = 0.1 at the interface to the peak level. In addition, the unmodified silicon active layer may have a thickness of about 600 GPa or more, and the Si _1-x Ge _x layer may have a thickness of about 800 GPa or less.

Larger drive current capability in PMOS transistors can be achieved by reorganizing the dopant profiles in the channel and body regions. In particular, the difference in solubility of certain dopants in silicon and Si _1-x Ge _x can be advantageously used to improve the properties of PMOS devices. In a preferred PMOS transistor, the Si _1-x Ge _x layer is doped with an N-type dopant, and the concentration of the N-type dopant in the Si _1-x Ge _x layer is in a first direction towards the surface of the unmodified silicon active layer. Have a decreasing profile. This profile preferably has a peak level in the Si _1-x Ge _x layer and is continuously reduced in the first direction in a monotonous manner in which the retranslated N-type dopant profile extends across the unmodified silicon active layer. Can be. Such an N-type dopant may preferably be used to suppress punchthrough in the body region, but may also be used to affect the threshold voltage of a PMOS transistor.

Further, other SOI field effect transistors may include an electrical insulating layer and a composite semiconductor active region on the electrical insulating layer. The composite semiconductor active region may include a silicon active layer having a thickness of about 600 GPa or more, and a single Si _1-x Ge _x layer disposed between the electrical insulating layer and the silicon active layer. The Si _1-x Ge _x layer forms a first junction with the silicon active layer, in which germanium has a monotonically decreasing inclined concentration in a first direction in which germanium extends from the peak level toward the surface of the silicon active layer. . The peak level of germanium in the Si _1-x Ge _x layer is preferably greater than x = 0.15, and the concentration of germanium in the Si _1-x Ge _x layer is at the first junction from the peak level. Varying to a level less than about x = 0.1. More preferably, the concentration of germanium in the Si _1-x Ge _x layer varies from a peak level of 0.2 <x <0.4 to a level of x = 0 at the first junction. In addition, the Si _1-x Ge _x layer interfaces with the electrical insulating layer, and the concentration of the inclined germanium in the Si _1-x Ge _x layer is less than about x = 0.1 at the interface. It may increase from level to the peak level.

Another embodiment of the invention includes a PMOS field effect transistor extending over an electrically insulating layer and having a composite semiconductor active region therein. The composite semiconductor active region is within the germanium two days Si _1-x Ge _x layer peak level one of Si _1-x Ge _x having an inclined concentration decreasing monotonously in a first direction extending towards a surface thereof from within Layer. Also provided is an unmodified silicon active layer extending from the first junction with the single Si _1-x Ge _x layer to the surface. In addition, the composite semiconductor active region has a peak level in a single Si _1-x Ge _x layer if it has essentially at least a re-logated N-type dopant profile extending towards the surface therein. The total charge provided by this N-type dopant affects the threshold voltage of the PMOS transistor. In addition, an N-type dopant in a single Si _1-x Ge _x layer significantly prevents punchthrough caused by a depletion layer that may extend between the source and drain regions. In addition, a lightly doped P-type source and drain region is provided. These regions are formed in the silicon active layer opposite the insulated gate electrode. A source side pocket implant region of N type conductivity is provided, which is formed between the lightly doped P type source region and the single Si _1-x Ge _x layer. These pocket implanted regions form rectified and semi-rectified junctions with source regions and a single Si _1-x Ge _x layer, respectively, and serve to suppress junction leakage.

Another embodiment of an SOI field effect transistor includes a bulk silicon region and an electrically insulating layer on the bulk silicon region. An unmodified silicon active layer having a first thickness is also provided on the electrically insulating layer, and an insulated gate electrode having sidewall insulating spacers is formed on the surface of the unmodified silicon active layer. A Si _1-x Ge _x layer of a first conductivity type is disposed between the electrically insulating layer and the unmodified silicon active layer. In particular, the Si _1-x Ge _x layer forms a first junction with the unmodified silicon active layer, in which the germanium has an inclined concentration monotonously decreasing in a first direction extending from the peak level towards the surface. . A low concentration doped source and drain region of the second conductivity type is also provided. These lightly doped regions are formed in the unmodified silicon active layer, but at a depth less than the thickness of the unmodified silicon active layer. In addition, a source-side pocket implant region of a first conductivity type is provided in the unmodified silicon active layer, which source-side pocket implant region is formed between the lightly doped source region and the Si _1-x Ge _x layer. . According to a preferred form of this embodiment, the Si _1-x Ge _x layer has a first conductivity type doping profile retrologed therein with respect to the surface. This retranslated first conductivity type doping profile may be a retranslated arsenic (or arsenic / phosphorus) doping profile, wherein the retranslated arsenic (or arsenic / phosphorus) doping profile is present in the channel region in the unmodified silicon active layer relative to the maximum concentration of the first conductivity type dopant The concentration of the first conductivity type dopant can be made large Si _1-x Ge _x layer. In particular, the retranslated dopant profile has a peak in the Si _1-x Ge _x layer and is minimal at the bottom of the gate electrode. This retrolled profile is preferably monotonically reduced from the peak level to the minimum level, although other retrolled profiles may be obtained. The thickness of the unmodified silicon active layer and the total amount of dopant in the channel region and underlying Si _1-x Ge _x layer may be carefully adjusted to achieve the desired threshold voltage and to prevent punchthrough.

Embodiments of the present invention also include a method of forming a field effect transistor by forming an insulated gate electrode on a surface of an SOI substrate. The substrate is disposed between an electrically insulating layer, an unmodified silicon active layer on the electrically insulating layer, and the electrically insulating layer and an unstrained silicon active layer, in which Si _1-x Ge having a concentration of germanium inclined therein. _x layer. A source and drain region of a first conductivity type is formed in the unmodified silicon active layer, and a source and drain side of a second conductivity type formed in the unmodified silicon active layer and the Si _1-x Ge _x epitaxial layer. Steps for forming the pocket injection area are also performed. These pocket implant regions form a PN junction with the source and drain regions, respectively. Prior to forming the insulated gate electrode, a step of injecting a dopant for controlling a threshold voltage of a first conductivity type into the unmodified silicon active layer is preferably preceded. This threshold voltage dopant is then annealed after the insulated gate electrode is formed, and redistributed as a result of the difference in dopant solubility in silicon and Si _1-x Ge _x , resulting in a Si _1-x Ge _x epitaxial layer and A retrode profile of the threshold voltage dopant is formed in the silicon active layer. The dopant in the Si _1-x Ge _x epitaxial layer also prevents punchthrough in PMOS devices and reduces floating body effects in NMOS devices.

The substrates and formation methods of the present invention may be used to form NMOS transistors with a reduced floating body effect (FBE). This is because the reduction of FBE reduces the potential barrier for holes flowing from the body region to the source region with the buried silicon germanium layer inclined therein. Therefore, holes generated in the body region by impact ionization flow more easily into the source region along the path of p-Si (body) / p-SiGe (body) / n + SiGe (source) / n + Si (source). I can go. An NMOS transistor can also be formed having a drain current (Id) to gate voltage (Vg) curve with a well-dispersed kink effect characteristic with a subthreshold slope that is evenly distributed over the drain-source voltage (Vds). . The substrate and formation method of the present invention may be used to provide a PMOS transistor having excellent driving capability resulting from high inversion layer carrier mobility in the channel region. This improved drive capability is obtained by reorganizing the channel region dopant through annealing so that the retranslated dopant profile and the desired threshold voltage are achieved simultaneously. Such reorganization of channel region dopants may be used to enhance pocket ion implantation effects. The threshold voltage roll-off characteristics of these NMOS and PMOS devices can exhibit reduced short channel effects (RSCE), and the parasitic bipolar action (PBA) in these devices is suppressed. ) Can be used to reduce the off leakage current.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings illustrating embodiments of the present invention, the thicknesses of certain layers or regions are exaggerated for clarity of specification. In addition, where a layer is described as being "top" of another layer or substrate, the layer may be present directly on top of the other layer or substrate, with a third layer intervening therebetween. Moreover, while the terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types, such as N-type or P-type, each embodiment described and described herein also refers to its complementary embodiment. Include. Like numbers refer to like elements throughout.

With reference to FIGS. 3A-3E, preferred methods of forming an SOI substrate having a Si _1-x Ge _x layer therein are described. As shown in FIG. 3A, the depicted method includes forming a handling substrate 10 having a porous silicon layer 12 therein and a first epitaxial silicon layer 14 formed on the porous silicon layer 12. Include. The first epitaxial silicon layer 14 may have a thickness of about 600 GPa or more. As shown in FIG. 3B, a Si _1-x Ge _x layer 16 is then formed on the first epitaxial silicon layer 14. This Si _1-x Ge _x layer 16 has a thickness of about 800 GPa or less and can be formed using low pressure chemical vapor deposition (LPCVD) techniques performed at temperatures in the range between 700 ° C and 1300 ° C. This deposition step can be performed by exposing the surface of the first epitaxial silicon layer 14 to a deposition gas comprising a mixture of GeH ₄ and SiH ₂ Cl ₂ source gas. In particular, the deposition step is preferably performed while changing the relative concentration of germanium source gas (eg GeH ₄ ) in situ. For example, the flow rate of germanium source gas is preferably such that the concentration of germanium in the Si _1-x Ge _x layer 16 is equal to x = 0 at the junction with the underlying first epitaxial silicon layer 14. Change from the value of to increase to a maximum of 0.2 ≦ x ≦ 0.4. After reaching the maximum concentration level, the flow of germanium source gas is gradually reduced until the concentration of germanium in the Si _1-x Ge _x layer 16 is reduced to zero.

With continued reference to FIG. 3B, the second epitaxial silicon layer 18 continues the deposition step using a SiH ₂ Cl ₂ source gas at a temperature of about 850 ° C., thereby allowing the Si _1-x Ge _x layer 16 to proceed. It can be formed on. Forming the second epitaxial silicon layer 18 is optional.

Referring to FIG. 3C, the supporting substrate 20 is preferably bonded to the second epitaxial silicon layer 18. As shown, this bonding step is preferably performed between the oxide layer 22 present on the supporting substrate 20 and the polished surface of the second epitaxial silicon layer 18. The oxide layer 22 has a thickness in the range of about 800 to 3000 microns. Subsequently, as shown in FIG. 3D, the handling substrate 10 is removed from the composite substrate by separating the composite substrate along the porous silicon layer 12. Conventional techniques may then be used to remove the remaining portion of the porous silicon layer 12 from the composite substrate. As shown in FIG. 3E, this removal step includes removing the porous silicon layer 12 using a planarization or polishing technique that exposes the initial surface 14a of the first epitaxial silicon layer 14. As described in more detail below, active devices (eg, CMOS devices) having more desirable electrical properties can be formed in the first " unstrained " epitaxial silicon layer 14.

4A-4E, other methods of forming an SOI substrate having a Si _1-x Ge _x layer therein will be described. As shown in FIG. 4A, the depicted method uses a Si _1-x Ge _x layer 16 ′ and a second epitaxial silicon layer 18 ′ formed on the Si _1-x Ge _x layer 16 ′ thereon. Forming a handling substrate 10 'having the same. The Si _1-x Ge _x layer 16 ′ may be formed as described above with respect to FIG. 3B. Subsequently, a blanket ion implantation step is performed. The ion implantation step includes implanting hydrogen ions into the handling substrate 10 ′ through the second epitaxial silicon layer 18 ′ to form the hydrogen ion implantation layer 15. Hydrogen ions are preferably implanted at an energy level sufficient to form a first silicon layer 14 'between the hydrogen ion implantation layer 15 and the Si _1-x Ge _x layer 16'. For example, hydrogen ions are implanted at a dose level of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻² and an energy level of 150 to 400 KeV. Referring to FIG. 4C, the supporting substrate 20 is preferably bonded to the second epitaxial silicon layer 18 ′. As shown, this bonding step is preferably performed between the oxide layer 22 present on the supporting substrate 20 and the polished surface of the second epitaxial silicon layer 18 '. Then, as shown in FIG. 4D, the handling substrate 10 ′ is removed from the composite substrate by separating the composite substrate along the hydrogen ion implantation layer 15. At this time, conventional techniques may be used to remove the remaining portion of the hydrogen ion implantation layer 15 from the composite substrate.

As shown in FIG. 4E, this removal step includes removing the hydrogen ion implantation layer 15 using planarization or polishing techniques that expose the initial surface of the first silicon layer 14 ′. According to another embodiment of the present invention, the second epitaxial silicon layer 18 of FIG. 3C and the second epitaxial silicon layer 18 'of FIG. 4C may be thermally oxidized before the bonding step is performed. Alternatively, prior to the bonding step, an electrical insulating layer is on the second epitaxial silicon layer 18, 18 ′, or when the second epitaxial silicon layer 18, 18 ′ is not present. It may be deposited on the Si _1-x Ge _x layers 16, 16 ′. The thickness of the Si _1-x Ge _x layers 16, 16 ′ may be increased if these layers are partially thermally oxidized in preparation for the bonding step. The thickness of the second epitaxial silicon layers 18, 18 'may be set within a range between about 200 and 400 microns.

Alternatively, the Si _1-x Ge _x layers 16, 16 ′ may be formed as layers with an inclined concentration of germanium therein that reaches a maximum level of about 30 percent. Such layers may be formed at temperatures in the range of 700 to 800 ° C. and pressures of about 20 Torr. The source gas may include GeH ₄ 0 to 60 sccm, DCS (SiH ₂ Cl ₂ ) 200 sccm, and HCl 50 to 100 sccm.

Referring to FIG. 5, preferred methods of forming field effect transistors (eg, MOSFETs) in SOI substrates are described. As described in connection with FIGS. 3A-3E and 4A-4E, these methods include forming an unmodified silicon active layer and a buried Si _1-x Ge _x layer therein (block 102). The buried Si _1-x Ge _x layer is preferably epitaxially grown from the unmodified silicon active layer while the concentration of germanium is initially increased from a level of x = 0 to a peak level of 0.2 ≦ x ≦ 0.4. Thus, the concentration of germanium in the buried Si _1-x Ge _x layer is preferably reduced in the direction extending from the peak level therein towards the initial surface of the unmodified silicon active layer (ie, the top surface of the SOI substrate). Have a profile. Dopants for adjusting the threshold voltage are then injected into the substrate (block 104). The "threshold voltage" dopants used in NMOS and PMOS transistors may be separately implanted into the substrate using NMOS and PMOS injection masks, respectively. For NMOS transistors, the threshold voltage dopant typically includes P-type dopants such as boron and indium. However, for PMOS transistors, the threshold voltage dopant includes N-type dopants such as arsenic and phosphorous.

Injecting the threshold voltage dopant includes injecting multiple different dopants of the same conductivity type. For example, in a PMOS device, both arsenic and phosphorus can be implanted as threshold voltage dopants at energy and dose levels, respectively. These multiple dopants have different dopant solubility in silicon and silicon germanium, and this different solubility can be advantageously used to achieve the desired redistribution of the threshold voltage dopants when subsequent thermal annealing steps are performed. Such a desired redistribution will result in a retrograde profile of the threshold voltage dopants. In particular, the desired redistribution of the dopants can improve the resulting inversion layer channel characteristics of the transistor by preventing the reduction in channel mobility that typically occurs when threshold voltage dopants enter the channel region of the transistor. This is particularly advantageous for PMOS devices that are typically limited from the relatively low hole mobility in the inversion layer channel. The thickness of the silicon active layer and the underlying Si _1-x Ge _x layer can also be designed to enhance the desired degree of redistribution of the threshold voltage dopant while simultaneously ensuring that the overall dopant charge affects the resulting threshold voltage. have. Dopants used to influence the threshold voltage in PMOS devices may also be advantageously used to prevent punchthrough.

Subsequently, referring to block 106, an insulated gate electrode is formed on the substrate using conventional techniques. As shown in block 108, the insulated gate electrode is used as a mask during the implantation of lightly doped source (LDS) and lightly doped drain (LDD) dopants into an unmodified silicon active layer. Pocket implant regions may be formed by implanting pocket region dopants into an unmodified silicon active layer and a bottom Si _1-x Ge _x layer (block 110). Such pocket region dopants are preferably implanted at a sufficient dose level and energy level to form a pocket implant region formed between the LDS and LDD regions and the Si _1-x Ge _x layer. As shown at block 112, conventional general techniques may be used to form electrically insulating spacers on the sidewalls of the gate electrode. Highly doped source and drain region dopants are implanted into and through the LDS and LDD regions using the gate electrode and sidewall insulating spacers as implant masks (block “114”). As shown at block 116, a rapid thermal annealing (RTA) step may be performed to drive in the source and drain region dopants. During this annealing step, pre-implanted dopants can be diffused or redistributed in the silicon active layer and the bottom Si _1-x Ge _x layer.

6A-6E, preferred methods of forming an SOI field effect transistor form a substrate having an unmodified silicon active layer 36 formed thereon and an embedded Si _1-x Ge _x layer 34 formed therein. It includes a step. As shown in FIG. 6A, the unmodified silicon active layer 36 has a thickness of about 600 GPa or more and the buried Si _1-x Ge _x layer 34 has a thickness of about 800 GPa or less. Preferably, the unmodified silicon active layer 36 has a thickness in the range of about 800 to 1200 microns and the buried Si _1-x Ge _x layer 34 has a thickness in the range of about 200 to 600 microns. More preferably, the unmodified silicon active layer 36 has a thickness of 1000 GPa and the buried Si _1-x Ge _x layer 34 has a thickness of 400 GPa. A modified or unmodified relatively thin underlayer 32 having a thickness of about 300 mm 3 may be provided between the buried Si _1-x Ge _x layer 34 and the buried oxide layer 30. The lower layer 32 may be omitted. The concentration of germanium in the buried Si _1-x Ge _x layer 34 may be set to zero at the junction of the silicon active layer 36 and the lower layer 32. In addition, the concentration of germanium in the buried Si _1-x Ge _x layer 34 may be set to a peak pevel in the range of 0.2 to 0.4, and may be linearly inclined with respect to the peak level. 30 may be provided on a semiconductor substrate or wafer (not shown).

Referring to FIG. 6B, dopants 38 for adjusting the threshold voltage are injected into the unmodified silicon active layer 36. If NMOS and PMOS devices are formed at adjacent locations within the silicon active layer 36, separate NMOS and PMOS implantation masks (not shown) may be formed on the unmodified silicon active layer 36. Such masks may be used when the N-type dopants are implanted as a threshold voltage dopant for PMOS devices and when the P-type dopant is implanted as a threshold voltage dopant for NMOS devices. The implanted dopants 38 may include boron and indium when forming an NMOS device, and may include arsenic and phosphorus when forming a PMOS device. Other dopants may also be used. In particular, the depicted implantation step may comprise two separate implantation steps. Firstly, threshold voltage dopants, such as BF2 ions, can be implanted at a tilt angle of 0 ° at an energy level in the range of about 30 to 60 KeV and at a dose level in the range of about 8 x 10 ¹¹ to 5 x 10 ¹³ cm ^-2. have. Secondly, threshold voltage dopants, such as indium ions, may be implanted at an energy level in the range of about 150 to 250 KeV and at a dose level in the range of about 8 x 10 ¹¹ to 5 x 10 ¹³ cm ^-2 . When forming a PMOS device, the ion implantation step described above is sufficient to obtain a desired retrode dopant profile in the channel and body regions within the silicon active layer 36 and the lower Si _1-x Ge _x layer 34. Separating and implanting arsenic and phosphorus ions at the dose and energy levels. In particular, the first implantation step may be phosphorus ions are implanted at a tilt angle of 7 ° at an energy level in the range of about 20 to 40 KeV, at a dose level in the range of about 8 x 10 ¹¹ to 5 x 10 ¹³ cm ^-2 . . Arsenic ions may then be implanted at an energy level in the range of about 150-250 KeV, at a dose level in the range of about 8 × 10 ¹¹ to 5 × 10 ¹³ cm ⁻² . The arsenic ions can affect the threshold voltage, but typically can have a greater effect on device characteristics by preventing punchthrough in the body region of the PMOS device.

Referring to FIG. 6C, a conventional general technique may be used to form an insulated gate electrode on the initial surface of the silicon active layer 36. These techniques include forming a thermal oxide layer 42 on the initial surface and depositing a doped or undoped polysilicon layer 40 on the thermal oxide layer 42. Conventional techniques can also be used to pattern the polysilicon layer and thermal oxide layer into an insulated gate electrode having exposed sidewalls. Techniques for forming an insulated gate electrode are mainly granted to US Pat. No. 6,6064,092, Kim, entitled "Semiconductor-on-insulator Substrates Containing Electrically Insulating Mesas" granted to Park. U.S. Patent No. 5,998,840, entitled "Semiconductor-on-insulator Field Effect Transistors With Reduced Floating Body Parasitics," U.S. Pat. 5,877,046, described in detail, the disclosures of which are hereby incorporated by reference. First, source and drain region dopants 39 are implanted into the silicon active layer 36 to form lightly doped source (LDS) and drain (LDD) regions 44a and 44b. As described, these dopants may be implanted in a self-aligning manner using the insulating gate electrode as an injection mask. Boron dopants (eg, BF ₂ ions) for a PMOS device may be implanted at an energy level in the range of about 3 to 30 KeV and at a dose level in the range of about 1 × 10 ¹² to 1 × 10 ¹⁶ cm ^−2. have. Also for NMOS devices, arsenic dopants may be implanted at dose levels in the range of about 1 × 10 ¹² to 1 × 10 ¹⁶ cm ⁻² , at energy levels in the range of about 20 to 50 KeV. A relatively short annealing step can then be performed to diffuse the LDD and LDS dopants horizontally and vertically. Other dopants may be used when forming the LDS and LDD regions.

Referring to FIG. 6D, pocket implant region dopants 46 may be formed to form P-type pocket implant regions 48a and 48b in an NMOS device or N-type pocket implant regions 48a and 48b in a PMOS device. It can be injected at tilt angles in the range of 7 and 35 degrees. This implantation step may be preferably implanted at a sufficient energy level and dose level through the LDD and LDS regions 44a and 44b into the buried Si _1-x Ge _x layer 34. In particular, N-type pocket implantation regions 48a and 48b may be formed by implanting arsenic ions at an energy level in the range of about 100 to 300 KeV, at a dose level in the range of about 1 x 10 ¹² to 1 x 10 ¹⁵ cm ^-2. Can be. P-type pocket implantation regions 48a and 48b may also be formed by implanting boron ions at an energy level in the range of about 20 to 60 KeV, at a dose level in the range of about 1 x 10 ¹² to 1 x 10 ¹⁵ cm ^-2. have.

Highly doped N-type source and drain regions 50a and 50b allow arsenic ions 52 to have an energy in the range of about 20 to 60 KeV and a dose in the range of about 5 x 10 ¹⁴ cm ^-2 to 1 x 10 ¹⁷ cm ^-2. It can form by inject | pouring into it. In addition, for PMOS devices, the heavily doped P-type source and drain regions 50a and 50b may contain BF ₂ ions with energy in the range of about 25 to 40 KeV and about 1 x 10 ¹⁴ cm ^-2 to 5 x 10 ¹⁶ cm. It can form by inject | pouring with the dose of ^-2 range. Drive-in and activation steps may be performed by annealing the substrate using rapid thermal processing techniques. This annealing step may be performed for 10 to 200 seconds in the temperature range of 900 ℃ to 1050 ℃.

With reference to FIGS. 7A-7D, the pre-annealing and post-annealing profiles of N-type dopants in a conventional SOI substrate and a silicon germanium layer embedded therein will be described. In particular, FIG. 7C shows a doping profile for phosphorus and arsenic in a conventional SOI substrate having an buried oxide layer (BOX) formed between a silicon active layer (Top-Si) and a silicon wafer (not shown). These phosphorus and arsenic dopants were injected with energy of 30 KeV and 200 KeV, respectively. As shown in FIG. 7B, the initial Gaussian doping profile spreads out after a rapid heat treatment (RTA) for about 30 seconds at a temperature of about 1000 ° C., resulting in an essentially uniform profile. In contrast, the doping profile shown in FIG. 7A shows that a retrode arsenic profile can be obtained in an SOI substrate having an embedded Si _1-x Ge _x layer therein formed according to the method of the present invention. This retrograde profile is obtained in part by doping the Si _1-x Ge _x layer at a concentration of sufficient germanium to essentially increase the dopant solubility of arsenic in the Si _1-x Ge _x layer relative to the silicon active layer. . In particular, FIG. 7A shows the pre annealed phosphorus and arsenic profile (phosphorus and arsenic dopants are injected with energy of 30 and 200 KeV, respectively) and FIG. 7D shows the post annealed profile. As shown in FIG. 7B, the rapid heat treatment step was performed at about 1000 ° C. for about 30 seconds. As shown in FIG. 7D, the arsenic profile is monotonically from the peak concentration level of 1 × 10 ¹⁹ cm ^{−3 in} the buried Si _1-x Ge _x layer to the minimum concentration level of 1 × 10 ¹⁷ cm ⁻³ at the surface of the substrate. It is decreasing. Depending on the concentration and profile of the phosphorus dopant in the silicon active layer, the binding profile of the phosphorus and arsenic dopant may also be retrolated across the silicon active layer.

Although the preferred embodiments of the invention have been described in the drawings and the description of the invention, although specific terms have been used, these are used only in a generic and descriptive sense, and are used to limit the spirit of the invention as set forth in the appended claims. It is not.

According to the present invention, improved methods and structures formed by forming substrates which do not require the use of modified channel regions to ensure enhanced channel mobility characteristics can be obtained, in particular in punch-through in PMOS devices. This prevents false negatives and reduces floating body effects in NMOS devices.

Claims (58)

Electrical insulation layer; An unmodified silicon active layer on the electrically insulating layer; An insulated gate electrode on a surface of the unmodified silicon active layer; And A first interposed between the electrically insulating layer and the unmodified silicon active layer, forming a first junction with the unmodified silicon active layer, wherein germanium extends from the peak level toward the surface of the silicon active layer Semiconductor-On-Insulator (SOI) field effect transistor comprising a Si _1-x Ge _x layer having an inclined concentration monotonously decreasing in the direction. The method of claim 1, wherein the peak level is greater than x = 0.15 and the concentration of germanium in the Si _1-x Ge _x layer varies from the peak level to a level less than about x = 0.1 at the first junction. SOI (Semiconductor-On-Insulator) field effect transistor. The SOI concentration according to claim 2, wherein the concentration of germanium in the Si _1-x Ge _x layer varies from a peak level of 0.2 &lt; x &lt; 0.4 to a level of x = 0 in the first junction. Semiconductor-On-Insulator) Field Effect Transistor. The method of claim 3, wherein the Si _1-x Ge _x layer interfaces with the electrically insulating layer, and wherein the concentration of the inclined germanium in the Si _1-x Ge _x layer is about x = at the interface. A SOI (Semiconductor-On-Insulator) field effect transistor, characterized by increasing from a level less than 0.1 to the peak level. 2. The SOI (Semiconductor-On-Insulator) field effect transistor according to claim 1, wherein the unmodified silicon active layer has a thickness of about 600 GPa or more. 6. The SOI (Semiconductor-On-Insulator) field effect transistor of claim 5, wherein the Si _1-x Ge _x layer has a thickness of about 800 GPa or less. The method of claim 1, wherein the Si _1-x Ge _x layer is implanted with an N-type dopant, and the concentration of the N-type dopant in the Si _1-x Ge _x layer has a profile decreasing in the first direction. SOI (Semiconductor-On-Insulator) field effect transistor. Electrical insulation layer; A composite semiconductor active region on the electrically insulating layer, wherein the composite semiconductor active region is a single Si _1-x interposed between an unmodified silicon active layer having a thickness of about 600 GPa or more and the electrical insulating layer and the silicon active layer. A Ge _x layer, wherein the Si _1-x Ge _x layer forms a first junction with the silicon active layer, monolithically decreasing in a first direction in which germanium extends from the peak level toward the surface of the silicon active layer A composite semiconductor active region having an inclined concentration; And A SOI (Semiconductor-On-Insulator) field effect transistor comprising an insulated gate electrode on the surface. The method of claim 8, wherein the peak level is greater than x = 0.15 and the concentration of germanium in the Si _1-x Ge _x layer varies from the peak level to a level less than about x = 0.1 at the first junction. SOI (Semiconductor-On-Insulator) field effect transistor. 10. The SOI of claim 9, wherein the concentration of germanium in the Si _1-x Ge _x layer varies from a peak level of 0.2 &lt; x &lt; 0.4 to a level of x = 0 in said first junction. Semiconductor-On-Insulator) Field Effect Transistor. The method of claim 10, wherein the Si _1-x Ge _x layer interfaces with the electrically insulating layer, and wherein the concentration of the inclined germanium in the Si _1-x Ge _x layer is about x = at the interface. A SOI (Semiconductor-On-Insulator) field effect transistor, characterized by increasing from a level less than 0.1 to the peak level. 9. The SOI (Semiconductor-On-Insulator) field effect transistor of claim 8, wherein the Si _1-x Ge _x layer has a thickness of about 800 GPa or less. Electrical insulation layer; A composite semiconductor active region on the electrically insulating layer, wherein the composite semiconductor active region is inclined concentration monotonically decreasing in a first direction in which germanium extends from the peak level in a single Si _1-x Ge _x layer toward the surface. A single Si _1-x Ge _x layer having a silicon active layer extending from the first junction with the single Si _1-x Ge _x layer to the surface and having a minimum level near the surface and having a single A composite semiconductor active region having a retrograded N-type dopant profile having a peak level in the Si _1-x Ge _x layer; And And a PMOS field effect transistor comprising an insulated gate electrode on said surface. 15. The PMOS field effect transistor of claim 13, wherein the silicon active layer has a thickness greater than about 600 GPa and has an unstrained region adjacent to the surface therein. 15. The semiconductor device of claim 14, further comprising: a lightly doped P-type source and drain region extending into the silicon active layer opposite the insulated gate electrode; And And further comprising an N-type conductive source side pocket implant region extending between the lightly doped P-type source region and the single Si _1-x Ge _x layer, each forming a rectified and semi-rectified junction with them. PMOS field effect transistor. Electrical insulation layer; A silicon active layer on the electrically insulating layer; An insulated gate electrode on the surface of the silicon active layer; An inclined concentration disposed between the electrical insulating layer and the silicon active layer, forming a first junction with the silicon active layer, wherein germanium decreases in a direction from the electrical insulating layer toward the insulated gate electrode Si _1-x Ge _x epitaxial layer having; A lightly doped source and drain region of a first conductivity type in the silicon active layer; And And a source side pocket implant region of a second conductivity type extending between said lightly doped source region and said Si _1-x Ge _x epitaxial layer to form rectified and semi-rectified junctions with them. Enhancement mode field effect transistor. delete 17. The enhancement mode field effect transistor of claim 16, wherein the Si _1-x Ge _x epitaxial layer has an N-type dopant profile retrologed therein. 19. The enhancement mode field effect transistor of claim 18, wherein the silicon active layer has a thickness greater than about 600 Hz. Forming a handling substrate having a silicon layer and a Si _1-x Ge _x layer having an inclined concentration extending over said silicon layer and decreasing therein in a direction toward germanium; Adhering a supporting substrate to the handling substrate such that the Si _1-x Ge _x layer is disposed between the supporting substrate and the silicon layer; And Removing a portion of the handling substrate from the supporting substrate to expose the silicon layer and define a semiconductor-on-insulator (SOI) substrate having an embedded Si _1-x Ge _x layer therein. Formation method. 21. The method of claim 20, wherein the silicon layer is an unmodified silicon layer. 21. The method of claim 20, wherein forming the handling substrate comprises forming a first silicon layer therein, a Si _1-x Ge _x layer extending on the first silicon layer, and a second extending on the Si _1-x Ge _x layer. Forming a handling substrate having a silicon layer. 23. The method of claim 22, further comprising thermally oxidizing the second silicon layer to form a thermal oxide layer prior to the bonding step, wherein the supporting substrate includes an oxide surface layer thereon, and the bonding step comprises the oxide surface layer. Forming a semiconductor substrate comprising the step of adhering to the thermal oxide layer. 21. The method of claim 20, wherein depositing an electrically insulating layer on a Si _1-x Ge _x layer is preceded by the bonding step, wherein the supporting substrate comprises an oxide surface layer thereon, and the bonding step comprises the oxide surface layer. And attaching to the electrically insulating layer. 21. The method of claim 20, wherein the handling substrate includes a porous silicon layer therein, and the removing step includes removing a portion of the handling substrate from the supporting substrate by separating the porous silicon layer. Method of forming a semiconductor substrate. 26. The method of claim 25, wherein said removing comprises continuously planarizing said porous silicon layer and said silicon layer. 21. The method of claim 20, wherein said handling substrate comprises a porous silicon layer therein, and said removing step comprises continuously planarizing said porous silicon layer and said silicon layer. The method of claim 20, wherein forming the handling substrate comprises: Epitaxially growing a Si _1-x Ge _x layer on the silicon layer; And Implanting hydrogen ions through the Si _1-x Ge _x layer and the silicon layer to form a hydrogen injection layer in the handling substrate. 29. The method of claim 28, wherein said removing comprises separating said hydrogen injection layer. 30. The method of claim 29, wherein said removing comprises planarizing said hydrogen injection layer. The method of claim 21, wherein forming the handing substrate comprises: Epitaxially growing a Si _1-x Ge _x layer on the silicon layer; And Implanting hydrogen ions through the Si _1-x Ge _x layer and the silicon layer to form a hydrogen injection layer in the handling substrate. 32. The method of claim 31 wherein the removing step comprises separating the hydrogen injection layer. 33. The method of claim 32, wherein removing comprises planarizing the hydrogen injection layer. Forming a handling substrate having an unmodified silicon layer and an epitaxial Si _1-x Ge _x layer extending over said unmodified silicon layer and having an inclined concentration of germanium therein; Adhering a supporting substrate to the handling substrate such that the Si _1-x Ge _x layer is disposed between the supporting substrate and the unmodified silicon layer; And Exposing the unmodified silicon layer and removing a portion of the handling substrate from the supporting substrate to form a semiconductor-on-insulator (SOI) substrate having an embedded Si _1-x Ge _x layer therein. Method of forming a semiconductor substrate. 35. The method of claim 34, wherein said forming step includes forming a handling substrate having an unmodified silicon layer having a thickness of at least about 600 microseconds therein. 36. The method of claim 35, wherein the Si _1-x Ge _x layer has a thickness of about 800 GPa or less. A silicon wafer having an electrical insulation layer thereon; A Si _1-x Ge _x layer formed on the electrically insulating layer, the Si _1-x Ge _x layer having a sloped concentration therein in which germanium decreases in a surface direction opposite to the electrically insulating layer; And A semiconductor-on-insulator (SOI) substrate forming a semi-rectifying junction with the Si _1-x Ge _x layer and including an unstrained silicon active layer extending to the surface of the semiconductor-on-insulator (SOI) substrate. 38. The SOI substrate of claim 37, wherein the Si _1-x Ge _x layer is epitaxially grown from the unmodified silicon active layer. 39. The SOI substrate of claim 38, wherein the unmodified silicon active layer has a thickness of about 600 GPa or more. An electrically insulative layer, an unstrained silicon active layer on the electrically insulative layer, and a slope between the electrically insulative layer and the unstrained silicon active layer and having germanium therein decreasing toward the unstrained silicon active layer. Forming an insulated gate electrode on a surface of a semiconductor on insulator (SOI) substrate comprising a Si _1-x Ge _x epitaxial layer having a concentration; Forming a source and drain region of a first conductivity type in the unmodified silicon active layer; And Forming source and drain side pocket implant regions of a second conductivity type extending in the unmodified silicon active layer and the Si _1-x Ge _x epitaxial layer, respectively, to form a PN junction with the source and drain regions; Method of manufacturing a field effect transistor comprising the step of. 41. The method of claim 40, wherein the unmodified silicon active layer has a thickness of about 600 GPa or more. 41. The method of claim 40, further comprising the step of injecting a dopant for controlling a threshold voltage of a first conductivity type into the unmodified silicon active layer prior to forming the insulated gate electrode, and forming the insulated gate electrode. And subsequently annealing the SOI substrate to form a retrode profile of a threshold voltage dopant in the Si _1-x Ge _x epitaxial layer. 43. The method of claim 42, wherein after forming the source side and drain side pocket injection regions, forming sidewall insulating spacers on the insulated gate electrodes is performed, and forming the source and drain regions comprises: Implanting a first source and drain region dopant of a first conductivity type into the unmodified silicon active layer using the insulated gate electrode as an ion implantation mask; And And injecting a second source and drain region dopant of a first conductivity type into the unmodified silicon active layer using the insulated gate electrode and the sidewall insulating spacer as an ion implantation mask. Manufacturing method. Bulk silicon region; Electrically insulating layer on the bulk silicon region An unmodified silicon active layer having a first thickness on the electrically insulating layer; An insulated gate electrode on the surface of the unmodified silicon active layer; Sidewall insulating spacers on the insulated gate electrode; Disposed between the electrical insulating layer and the unmodified silicon active layer, forming a first junction with the unmodified silicon active layer, wherein germanium is monotonously monolithically in a first direction from the peak level towards the surface A Si _1-x Ge _x layer of a first conductivity type with decreasing slope concentration; Lightly doped source and drain regions of a second conductivity type extending in the unmodified silicon active layer and having a thickness less than or equal to the first thickness; And Semiconductor-On-Insulator (SOI) extending between the lightly doped source region and the Si _1-x Ge _x layer and including a source-side pocket implant region of a first conductivity type in the unmodified silicon active layer Field effect transistor. 45. The SOI field effect transistor of claim 44, wherein said Si _1-x Ge _x layer has a doping profile of a first conductivity type retranslated therein with respect to said surface. 46. The SOI field effect transistor of claim 45, wherein said Si _1-x Ge _x layer has a arsenic doping profile retrologed therein relative to said surface. 46. The method of claim 45, further comprising a channel region of a first conductivity type in said unmodified silicon active layer, wherein a peak concentration of a first conductivity type dopant in said Si _1-x Ge _x layer is within said channel region. SOI (Semiconductor-On-Insulator) field effect transistor, characterized in that greater than the peak concentration of the first conductivity type dopant. 47. The method of claim 46, further comprising a channel region of a first conductivity type in said unmodified silicon active layer, wherein a peak concentration of a first conductivity type dopant in said Si _1-x Ge _x layer is within said channel region. SOI (Semiconductor-On-Insulator) field effect transistor, characterized in that greater than the peak concentration of the first conductivity type dopant. 49. A SOI (Semiconductor-On-Insulator) field effect transistor according to claim 48, wherein the unmodified silicon active layer has a thickness of about 600 GPa or more. 46. The SOI (Semiconductor-On-Insulator) field effect transistor of claim 45, wherein the unmodified silicon active layer has a thickness of about 600 GPa or more. Electrical insulation layer; A silicon active layer of a first conductivity type on the electrically insulating layer; An insulated gate electrode on the surface of the silicon active layer; A source region and a drain region of a second conductivity type in the silicon active layer; Low-concentration doped source and drain regions of a second conductivity type extending between the source region and the drain region to form a channel region under the insulated gate electrode; And An inclined concentration disposed between the lightly doped source and drain regions and the electrically insulating layer, wherein the germanium decreases in a direction from the peak level toward the lightly doped source and drain regions; A field effect transistor comprising a Si _1-x Ge _x epitaxial layer having. 53. The method of claim 51 wherein the lightly doped source and drain regions do not contact the Si _1-x Ge _x epitaxial layer, and the source and drain regions contact the Si _1-x Ge _x epitaxial layer. A field effect transistor, characterized in that. 53. The field effect transistor of claim 51, further comprising an epitaxial silicon layer disposed between the Si _1-x Ge _x epitaxial layer and the electrical insulating layer. 53. The field effect transistor of claim 51, wherein the total thickness of the Si _1-x Ge _x epitaxial layer and the silicon active layer is about 1500 kPa or less. Forming an electrical insulation layer; Forming a silicon active layer of a first conductivity type on the electrically insulating layer; Forming an insulated gate electrode on the surface of the silicon active layer; Forming a source region and a drain region of a second conductivity type in the silicon active layer; Forming lightly doped source and drain regions of a second conductivity type extending between the source region and the drain region and forming a channel region under the insulated gate electrode; And An inclined concentration disposed between the lightly doped source and drain regions and the electrically insulating layer, wherein the germanium decreases in a direction from the peak level toward the lightly doped source and drain regions; A method of forming a field effect transistor comprising the step of forming a Si _1-x Ge _x epitaxial layer having. 56. The method of claim 55, wherein the lightly doped source and drain regions do not contact the Si _1-x Ge _x epitaxial layer, and the source and drain regions contact the Si _1-x Ge _x epitaxial layer. A method of forming a field effect transistor, characterized in that. 56. The method of claim 55, further comprising an epitaxial silicon layer disposed between the Si _1-x Ge _x epitaxial layer and the electrical insulating layer. 56. The method of claim 55 wherein the total thickness of the Si _1-x Ge _x epitaxial layer and the silicon active layer is about 1500 kPa or less.