JP2701762B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a field effect transistor and a semiconductor device obtained by combining them, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, field effect transistors, especially MOS
(Metal-Oxide-Semiconductor
r) miniaturization of field effect transistors (FETs)
It is necessary to increase the substrate concentration in order to suppress the short channel effect. On the other hand, the gate oxide film thickness cannot be reduced without limitation due to restrictions due to withstand voltage and leak current. Therefore, the threshold voltage of the fine MOSFET increases. On the other hand, fine M
In the OSFET, it is necessary to lower the power supply voltage in order to reduce power consumption and ensure long-term reliability. However, if the power supply voltage is reduced while the threshold voltage is high, the element performance will be degraded.

Therefore, a method has been proposed in which a semiconductor thin film is epitaxially grown on a substrate having a high impurity concentration at a low temperature to form a steep impurity concentration distribution in the depth direction, thereby reducing the threshold voltage while suppressing the short channel effect. Have been.
In consideration of element isolation of this structure, LOCOS which forms a field insulating film partially buried in a substrate by selective thermal oxidation is used.
When an element isolation region is formed by oxidizing a substrate at a high temperature for a long time as in the case of isolation, redistribution of impurities is likely to occur during the oxidation process. Precise control becomes difficult.

A method has also been proposed in which after LOCOS isolation is formed, epitaxial growth is selectively performed on the semiconductor surface in the element region. In this case, crystal defects occur near the epitaxial film and the isolation edge, and leakage current and the like are increased. There is a risk of deteriorating device characteristics.

Further, there is a method in which a trench is formed in an element isolation region after an epitaxial film is formed, and an insulating film such as an oxide film is buried in the trench to perform element isolation.
According to this method, the deviation of the element isolation size observed in the LOCOS is logically eliminated, but there is a problem that a defect causing a leak current is generated in the substrate when the trench is formed.

On the other hand, as a transistor structure capable of suppressing the short channel effect, improving the reliability, and improving the current driving capability , a structure in which the substrate impurity concentration of the channel monotonously decreases from the source to the drain has already been proposed. I have. In the case of such a structure, by lowering the concentration near the drain end compared to the concentration near the source, the local threshold voltage near the drain decreases, and the electric field concentration in the lateral direction in the region is reduced. In order to realize the above characteristics, the device characteristics are improved by lowering the impurity concentration near the drain as much as possible.

[0007]

As described above, in the method of forming a semiconductor active layer serving as a channel region by using an epitaxial film grown at a low temperature, an isolation insulating film is formed by oxidizing a substrate such as LOCOS isolation. Thereafter, when a semiconductor thin film is epitaxially grown, a defect causing a leak current is likely to occur at the separation end. Further, when an epitaxial film is formed before element isolation formation, if element isolation by selective oxidation is used, there is a problem that impurity concentration near the surface increases due to re-diffusion of impurities from a base of the epitaxial film, and element characteristics deteriorate. . Further, in the trench isolation, there is a problem that a defect is caused by a stress due to a hole formed in the substrate.

On the other hand, in the case of a structure in which the impurity concentration of the channel is monotonously reduced from the source to the drain, the impurity concentration in the region surrounding the drain region is low and is uniform in a normal lateral direction without applying a drain bias. The depletion layer extends toward the depletion layer due to the structure having a good channel impurity distribution, and the expansion is suppressed in a region near the source where the impurity concentration is high. Therefore, the impurity concentration in the vicinity of the source must be significantly increased in order to suppress the short channel effect.
As a result, there is a problem that the odor of the change in the impurity concentration from the source to the drain becomes large, and the device characteristics are more easily affected by process variations.

[0009]

A feature of the present invention is that an epitaxial film serving as an active region in a first portion is under an element isolation insulating film, and an impurity concentration in the first portion of the epitaxial film is lower than that of a substrate. Lower than the impurity concentration, and
A buried layer having the same conductivity type as that of the substrate impurity and a higher impurity concentration than the second portion of the epitaxial film immediately below the device isolation insulating film and the substrate below the first portion of the epitaxial film in the device region is provided. In semiconductor devices.

Another feature of the present invention is that an epitaxial film is formed over the entire surface of a semiconductor substrate, and then an element isolation insulating film is selectively formed on the epitaxial film. The present invention relates to a method of manufacturing a semiconductor device in which a high-concentration region for electrical element isolation is formed by ion implantation after forming the element isolation insulating film to have the same or larger thickness.

Further, in the above-mentioned semiconductor device, a low-concentration well is formed in the substrate by monotonously decreasing the channel impurity concentration distribution of the epitaxial film from the source side to the drain side on the substrate in which the impurity is heavily doped. Then, a field effect transistor having a lower surface impurity concentration on the drain side can be formed as compared with the case where the impurity concentration is similarly changed from the source to the drain.

In the above method for manufacturing a semiconductor device,
Regarding the impurity doping method of the channel region of a transistor, an epitaxial film with a low impurity concentration is formed on the surface of a well with a high impurity concentration, and the impurity film is obliquely above the gate so that the impurity concentration decreases monotonically from the source to the drain. Can be implanted.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. n-channel MOSFET (In this specification, insulated gate field effect transistors are generally referred to as MOSFE
T will be described with reference to FIG.

First, on a p-well 2 having a concentration of 1 × 10 ¹⁶ cm ⁻³ formed on a p-type semiconductor substrate 1, a concentration of 1 × 10 ¹⁵ c
It has an active area of m ⁻³ of the epitaxial film 3. The element isolation insulating film 4 is located on the epitaxial film 3 and has a higher concentration p-type region 5 'than the well for electrical element isolation.
(Concentration: 3 × 10 ¹⁸ cm ⁻³ ) in the epitaxial layer region immediately below the isolation insulating film. The upper surface of the epitaxial film is flat from the part where the element is formed to the part below the element isolation insulating film. The high-concentration region 5 'makes the threshold voltage of the parasitic MOS transistor in the isolation part higher than the power supply voltage, and achieves electrical insulation between elements. Further, a p-type buried layer 5 having a higher concentration (3 × 10 ¹⁸ cm ⁻³ ) than the well concentration is provided in a deep region of the well.

A gate electrode 7 made of polysilicon is formed on a gate insulating film 6 made of silicon oxide, and n-type source and drain regions having a conductivity type opposite to that of the substrate are provided.

Next, a method of manufacturing a semiconductor substrate according to one embodiment of the present invention will be described with reference to FIGS.

First, a concentration of 1 × 10 ¹⁶ c is formed on a p-type Si substrate 9.
An m ⁻³ p well 10 is formed by ion implantation and thermal diffusion (FIG. 2A).

Next, an Si film 11 is epitaxially grown on the substrate by a CVD method or the like at a low temperature of about 600 ° C. at a substrate temperature of 50 nm (FIG. 2B).

Subsequently, a Si oxide film is deposited and patterned. For example, a Si oxide film 12 is formed by a CVD method, and is etched using a resist mask as a mask. As a result, an element isolation insulating film 12 is formed, and then, in order to obtain electrical element isolation characteristics, a p-type impurity such as boron is transferred to the epitaxial film region immediately below the element isolation Si oxide film 12. At the same time, a high-concentration region 13 ′ is formed by doping by ion implantation. At this time, ions are implanted into regions other than the element isolation region as well, so that the high-concentration region 13 of the impurity is located below the epitaxial film. The implantation energy and the thickness of the isolation oxide film are made larger than the epitaxial film (FIG. 3A).

Next, a gate insulating film 14 is formed, and a poly-Si gate electrode 15 is formed thereon.
The source and drain 16, 16 ′ are formed by ion implantation of n-type impurities such as (FIG. 3B). At this time,
The gate electrode material may be a metal such as tungsten or aluminum.

It is also possible to form a p-channel transistor by using the p-well as an n-well and implanting boron ions into the epitaxial film using phosphorus or phosphor.

Next, as a method of manufacturing a semiconductor device of another embodiment, a process of manufacturing a complementary MOS semiconductor device will be described with reference to FIGS.

First, p-type silicon substrate 17 is selectively p-type.
A well 18 and an n-well 19 are formed (FIG. 4A).
Here, a p-well may not be required depending on the p-type substrate.

Next, an epitaxial Si film 20 is formed on the substrate.
To form An Si oxide film 21 as an element isolation insulating film is selectively formed thereon (FIG. 4B).

Then, using a resist mask 22 or the like for electrical element isolation, boron is ion-implanted into the p-well and phosphorus is ion-implanted into the n-well so as to be doped into the epitaxial film below the element isolation insulating film. Implantation and subsequent activation heat treatment form p-type impurity high concentration regions 23 and 23 'and n-type impurity high concentration regions 24 and 24'. At this time, gallium or indium may be used instead of boron, and hisso or antimony may be used instead of phosphorus (FIG. 4).
(C)). Next, a Si oxide film is formed as the gate insulating film 31, and polysilicon gate electrodes 25 and 26 selectively doped with impurities are formed thereon (FIG. 5A). Here, the impurity doping to the gate electrode can be performed before the polysilicon processing, or after the processing by ion implantation or the like.

Subsequently, n-type and p-type source and drain regions 27, 27 ', 28 and 28' are formed (FIG. 5B). Here, an LDD region can be provided in combination with the sidewall insulating film.

Next, a semiconductor device according to another embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

FIG. 6 shows that the impurity concentration of the epitaxial film 11 is 1 × 10 ¹⁴ cm ^{−3 in} FIG. 3B, and that the impurity concentration distribution in the epitaxial film under the gate electrode 15 extends from the source 16 to the drain 16 ′. This is a structure in which a monotonically reduced region 29 is added.

FIG. 7 shows a process for manufacturing FIG. FIG.
After the steps up to (B), boron (B ⁺ ) ions are implanted at an angle of about 20 ° from the normal direction of the substrate. Here, it is also possible to perform boron ion implantation before forming the source and drain 16, 16 '. The angle θ at which ions are implanted can be changed depending on the design of the device performance such as the threshold voltage.

[0030]

According to the semiconductor device of the present invention, since the element isolation insulating film is formed on the epitaxial film, the occurrence of crystal defects in the film at the element isolation end and the formation of the underlayer during the formation of the epitaxial film. In this case, it is possible to simultaneously suppress the variation from the design dimensions of the element region and improve the element characteristics without re-diffusion of the impurity.

Further, according to the manufacturing method of the present invention, a structure capable of simultaneously achieving electrical element isolation, reduction of well resistance and prevention of latch-up without introducing defects at the element isolation end in the epitaxial film during epitaxial growth. Can be easily made.

Further, by using the structure as shown in FIG. 6, it becomes possible to lower the impurity concentration of the channel substrate at the drain end as compared with the conventional low concentration well, and as a result, the current driving capability is further improved. Then, it is possible to suppress a decrease in the threshold value due to the short channel effect as compared with the case of only the structure in which the channel impurity concentration is monotonously decreased from the source to the drain.

Further, by using the process as shown in FIG. 7, the re-diffusion of impurities from the base in the epitaxial film is suppressed, so that the impurity concentration at the drain end of the channel is kept low and the gate length is reduced. The above configuration capable of suppressing the threshold voltage from being lowered can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a step subsequent to FIG. 2 in order;

FIG. 4 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing a step subsequent to FIG. 4 in order;

FIG. 6 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a sectional view showing a step for obtaining the semiconductor device of FIG. 6;

[Explanation of symbols]

Reference Signs List 1 p-type semiconductor substrate 2 p-well 3 epitaxial film 4 element isolation insulating film 5, 5 ′ p-type impurity high concentration region 6 gate insulating film 7 poly-Si gate electrode 8, 8 ′ source, drain 9 p-type Si substrate 10 p-well REFERENCE SIGNS LIST 11 Si film 12 element isolation insulating film 13, 13 ′ high impurity concentration region 14 gate insulating film 15 gate poly Si electrode 16, 16 ′ source, drain 17 p-type Si substrate 18 p well 19 n well 20 epitaxial Si film 21 element isolation Si Oxide film 22 Resist mask 23,23 'High concentration p-type impurity region 24,24' High concentration n-type impurity region 25 N-channel MOS transistor gate electrode 26 P-channel MOS transistor gate electrode 27,27 'N-channel MOS transistor source and drain 28,28 'p-channel MOS transistor Source, region 30 resist mask 31 gate insulating film impurity concentration toward the drain from the drain 29 source monotonically decreases

Claims (4)

(57) [Claims] In a semiconductor device having a semiconductor epitaxial film on a semiconductor substrate of one conductivity type and a first portion having a low impurity concentration or no impurity in the semiconductor epitaxial film in an active region, the element isolation insulating film is An impurity concentration of a portion located on the second portion of the epitaxial film and located below the first portion of the semiconductor epitaxial film is higher than an impurity concentration of the first portion of the epitaxial film; In addition, the impurity concentration of the second portion of the epitaxial film below the element isolation insulating film is higher than the impurity concentration of the first portion of the epitaxial film. A step of growing an epitaxial film having a low concentration or containing no impurities on a semiconductor substrate of one conductivity type; a step of forming an element isolation insulating film only in an element isolation region on the epitaxial film; Implanting impurities below the epitaxial layer below the element isolation insulating film and the epitaxial layer in a region other than the element isolation region to increase the concentration by ion implantation. . 3. The semiconductor device according to claim 1, wherein the impurity concentration of the epitaxial film immediately below the gate electrode has a distribution that monotonically decreases from the source to the drain. 4. A step of growing an epitaxial film having a low concentration or containing no impurities on a semiconductor substrate of one conductivity type; a step of forming an element isolation insulating film only in an element isolation region on the epitaxial film; Performing ion implantation to increase the concentration by introducing impurities below the epitaxial layer under the device isolation insulating film and the epitaxial layer in a region other than the device isolation region; 4. The method according to claim 3, further comprising the step of: ion-implanting impurities at an angle inclined from a substrate normal.