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KR100393448B1 - 반도체 패키지 및 그 제조 방법 - Google Patents

반도체 패키지 및 그 제조 방법 Download PDF

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Publication number
KR100393448B1
KR100393448B1 KR10-2001-0015991A KR20010015991A KR100393448B1 KR 100393448 B1 KR100393448 B1 KR 100393448B1 KR 20010015991 A KR20010015991 A KR 20010015991A KR 100393448 B1 KR100393448 B1 KR 100393448B1
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semiconductor chip
semiconductor
chip
mounting plate
connecting means
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KR10-2001-0015991A
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KR20020076030A (ko
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백종식
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앰코 테크놀로지 코리아 주식회사
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Priority to KR10-2001-0015991A priority Critical patent/KR100393448B1/ko
Priority to US10/103,048 priority patent/US6700187B2/en
Publication of KR20020076030A publication Critical patent/KR20020076030A/ko
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Publication of KR100393448B1 publication Critical patent/KR100393448B1/ko
Priority to US10/680,280 priority patent/US6846704B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체 패키지 및 그 제조 방법에 관한 것으로서, 반도체 칩의 전기적인 입출력 연결을 골드와이어가 아닌 솔더볼과 골드볼과 같은 도전성 접속수단을 사용하고, 이 도전성 접속수단이 융착되는 리드 부위를 하프에칭 처리함으로써, 패키지의 크기를 칩의 크기에 가깝게 경박단소화시킬 수 있는 구조와, 반도체 칩의 열방출 효과를 극대화시킬 수 있도록 한 구조를 모두 용이하게 실현시킨 반도체 패키지 및 그 제조 방법을 제공하고자 한 것이다.

Description

반도체 패키지 및 그 제조 방법{Semiconductor package and method for manufacturing the same}
본 발명은 반도체 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 반도체 칩의 입출력을 위한 연결을 도전성 접속수단을 사용하고, 도전성 접속수단이 융착되는 리드부위를 하프 에칭하여, 전체적인 두께를 감소시킨 구조의 반도체 패키지 및 그 제조방법에 관한 것이다.
최근에 반도체 패키지의 제조 추세는 반도체 칩에서 발생하는 열의 방출 효과를 극대화시킬 수 있는 구조, 무선 통신기기와 같은 소형의 전자기기에 용이하게 실장되도록 그 크기를 칩의 크기에 가깝게 경박단소화시킨 구조, 제조비를 절감하면서 성능을 크게 향상시킬 수 있는 구조등을 실현시킬 수 있도록 한 제조 추세에 있다.
본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 반도체 칩의 전기적인 입출력 연결을 골드와이어가 아닌 도전성 접속수단을 사용하고, 이 도전성 접속수단이 융착되는 리드 부위를 하프에칭 처리함으로써, 패키지의 크기를 칩의 크기에 가깝게 경박단소화시킬 수 있는 구조와 반도체 칩의 열방출 효과를 극대화시킬 수 있도록 한 구조를 모두 용이하게 실현시킨 반도체 패키지 및 그 제조 방법을 제공하는데 그 목적이 있다.
도 1은 본 발명에 따른 반도체 패키지의 일실시예를 나타내는 단면도,
도 2는 도 1의 반도체 패키지의 제조 방법을 순서대로 나타낸 단면도,
도 3은 본 발명에 따른 반도체 패키지의 다른 실시예를 나타내는 단면도,
도 4는 도 3의 반도체 패키지의 제조 방법을 순서대로 나타낸 단면도,
도 5는 본 발명에 따른 반도체 패키지의 또 다른 실시예를 나타내는 단면도,
도 6은 도 5의 반도체 패키지의 제조 방법을 순서대로 나타낸 단면도,
<도면의 주요 부분에 대한 부호의 설명>
10 : 반도체 칩 12 : 리드
14 : 칩탑재판 16 : 하프에칭된 면
18 : 접착수단 20 : 코팅 금속재
22 : 도전성 접속수단 24 : 수지
26 : 웨이퍼 100,200,300 : 반도체 패키지
이하, 본 발명을 첨부도면을 참조로 설명하면 다음과 같다.
싱가한 목적을 달성하기 위한 본 발명의 반도체 패키지는:
반도체 칩(10)의 크기보다 작은 칩탑재판(14)과; 이 칩탑재판(14)에 접착수단(18)으로 부착되되 하면에 입출력패드가 형성된 반도체 칩(10)과; 상기 칩탑재판(14)의 사방에 인접되게 위치되고 상기 반도체 칩(10)의 입출력패드와 마주보는 면이 하프 에칭된 면(16)으로 형성된 다수의 리드(12)와; 서로 마주보고 있는 반도체 칩(10)의 입출력패드와 상기 리드(12)의 하프에칭된 면(16)간을 연결하며 융착된 도전성 접속수단(22)과; 상기 반도체 칩의 상면과, 칩탑재판의 저면과, 리드의 외측면 및 저면이 외부로 노출시키면서, 반도체 칩과 리드와 도전성 접속수단을 몰딩하고 있는 수지(24)로 구성된 것을 특징으로 한다.
바람직한 구현예로서, 상기 반도체 칩(10)이 보이지 않게 반도체 칩(10)의 상면까지 수지(24)로 몰딩된 구조를 특징으로 한다.
더욱 바람직한 구현예로서, 상기 반도체 칩(10)이 부착되는 칩탑재판(14)이 없는 경우에는, 이 칩탑재판이 없는 공간으로 수지(24)가 채워지도록 한 구조를 특징으로 한다.
특히, 상기 도전성 접속수단(22)이 융착되는 상기 리드(12)의 하프에칭 면(16)에는 도전성 접속수단(22)과 융착 친화성이 있는 코팅금속재(20)로 코팅된 것을 특징으로 한다.
이때, 상기 도전성 접속수단(22)은 솔더볼 또는 골드볼를 사용하는 것이 바람직하고, 상기 코팅금속재(20)는 티타늄 또는 알루미늄을 사용하는 것이 바람직하다.
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지 제조 방법은:
반도체 칩(10)이 부착되는 칩탑재판(14)과, 이 칩탑재판(14)의 사방에 인접되게 위치되고 각 안쪽부분이 하프 에칭된 다수의 리드(12)를 포함하는 리드프레임을 제공하는 단계와; 웨이퍼(26) 상태의 각 반도체 칩(10)의 입출력패드에 도전성접속수단(22)을 융착한 후, 개개의 단위로 소잉하여 구비된 반도체 칩(10)을 상기 칩탑재판(14)에 접착수단(18)으로 부착하는 동시에 상기 도전성 접속수단(22)이 리드(12)의 하프에칭된 면(16)에 융착되어 연결되도록 한 단계와; 상기 반도체 칩(10)의 상면과, 칩탑재판(14)의 저면과, 리드(12)의 외측면 및 저면을 외부로 노출시키면서, 반도체 칩(10)과 도전성 접속수단(22)과 칩탑재판(14)과 리드(12)등을 수지(24)로 몰딩하는 단계로 이루어진 것을 특징으로 한다.
여기서, 본 발명의 일실시예를 첨부한 도 1과 도 2를 참조로 더욱 상세하게 설명하면 다음과 같다.
첨부한 도 1은 본 발명에 따른 반도체 패키지의 일실시예를 나타내고, 도 2는 도 1의 반도체 패키지의 제조 방법을 순서대로 나타낸 단면도이다.
본 발명의 반도체 패키지(100)는 반도체 칩(10)의 입출력패드에 대한 전기적인 입출력 연결을 솔더볼 또는 골드볼과 같은 도전성 접속수단(22)을 사용한 점과, 각각의 리드(12)의 일부분에 하프에칭된 면(16)을 형성한 점에 특징이 있는 바, 이하 본 발명의 반도체 패키지의 제조방법을 순서대로 설명한다.
우선, 웨이퍼(26) 상태의 각 반도체 칩(10)의 입출력패드에 솔더(Solder) 및 골드(Gold) 재질로 만들어진 구형(球形)의 도전성 접속수단(22)을 고온에서 융착시킨 후, 소잉수단을 사용하여 반도체 칩(10)을 개개의 단위로 소잉함으로써, 각 입출력패드에 도전성 접속수단(22)이 융착된 반도체 칩(10)을 구비하게 된다.
또는, 상기 웨이퍼(26)를 개개의 칩 단위로 먼저 소잉한 후, 개개의 칩에 도전성 접속수단(22)을 융착시켜 구비하여도 무방하다.
또한, 상기 반도체 칩(10)이 부착되는 칩탑재판(14)과, 이 칩탑재판(14)의 주변에 인접되게 위치된 다수의 리드(12)로 구성된 리드프레임을 구비하게 되는데, 이때 상기 칩탑재판(14)의 크기는 실장될 반도체 칩(10)의 크기보다 작게 성형되고, 상기 각 리드(12)의 안쪽부분은 하프에칭된 면(16)으로 형성된다.
특히, 상기 각 리드(12)에 대한 하프 에칭 두께는 도전성 접속수단(22)이 융착된 후의 높이(구형의 도전성 접속수단이 상하로 융착됨에 따라 그 직경이 줄어든 후의 높이)와 유사하게 되도록 그 에칭 두께를 조절할 수 있다.
또한, 상기 하프에칭된 면(16)에는 도전성 접속수단(22)의 융착이 용이하게 이루어지도록 솔더 재질의 도전성 접속수단(22)과 융착시 친화력을 갖는 금속, 예를들어 티타늄, 알루미늄과 같은 코팅 금속재(20)로 코팅해주는 것이 바람직하다.
다음으로, 상기 칩탑재판(14)에 접착수단(18)을 사용하여, 상기 도전성 접속수단(22)이 융착된 반도체 칩(10)을 부착하는 동시에 도전성 접속수단(22)이 상기 리드(12)의 하프에칭된 면(16)에 융착되도록 함으로써, 상기 도전성 접속수단(22)에 의하여 반도체 칩(10)의 입출력패드와 리드(12)간의 연결이 이루어지게 된다.
이때, 상기 리드(12)의 하프에칭된 면(16)에는 구리와 같은 코팅금속재(20)로 코팅이 이루어져 있기 때문에, 도전성 접속수단(22)의 융착 연결이 더욱 용이하게 이루어진다.
이어서, 상기 반도체 칩(10)과, 칩탑재판(14)과, 리드(12)와, 도전성 접속수단(22)등을 외부로부터 보호하기 위하여 수지(24)로 몰딩하는 공정을 진행하게 되는데, 상기 반도체 칩(10)의 상면과, 칩탑재판(14)의 저면과, 리드(12)의 외측면 및 저면이 외부로 노출되도록 몰딩을 함으로써, 첨부한 도 1의 반도체 패키지(100)로 제조된다
상기와 같이 제조된 반도체 패키지(100)는 반도체 칩(10)의 상면이 외부로 노출되어 있고, 칩탑재판(14)의 저면도 외부로 노출되어 있어, 반도체 칩(10)에서 발생하는 열을 외부로 신속하고 빠르게 방출시킬 수 있게 된다.
또한, 상기 도전성 접속수단(22)이 융착되는 리드(12)의 융착 자리면은 하프에칭된 면(16)으로 처리되어 있기 때문에, 반도체 패키지의 전체적인 두께를 현격히 줄이면서 경박단소화를 실현할 수 있게 된다.
여기서, 본 발명의 다른 실시예를 첨부한 도 3과 도 4를 참조로 설명하면 다음과 같다.
다른 실시예로서의 반도체 패키지(200)는 일실시예의 반도체 패키지(100)와 그 구조 및 제조 방법이 동일하고, 단지 반도체 칩(10)의 상면이 외부로 노출되지 않도록 반도체 칩(10)의 상면이 수지(24)로 몰딩된 구조를 특징으로 한다.
이는, 반도체 패키지(200)내에서 반도체 칩(10)의 결합력을 증대시켜 반도체칩(10)을 외부로부터 더욱 용이하게 보호할 수 있으며, 일실시예와 같이 칩탑재판(14)의 저면이 외부로 노출되어 있기 때문에 반도체 칩(10)의 열방출 효과도 크게 얻어낼 수 있다.
여기서, 본 발명의 또 다른 실시예를 첨부한 도 5과 도 6을 참조로 설명하면 다음과 같다.
또 다른 실시예로서의 반도체 패키지(300)도 일실시예의 반도체 패키지(100)와 그 구조 및 제조 방법이 동일하고, 단지 반도체 칩(10)이 부착되는 칩탑재판(14)을 배제시킨 구조를 그 특징으로 한다.
상기 칩탑재판(14)을 배제시키는 것은 반도체 칩(10)의 열방출 효과를 크게 기대하지 않아도 되는 경우에 적용 가능하다.
이에, 상기 칩탑재판(14)이 제외된 공간에는 수지(24)가 채워져 반도체 칩(10)의 저면이 몰딩수지(24)와 접촉하게 됨에 따라, 반도체 패키지(300)내에서 반도체 칩(10)의 결합력이 증대되는 효과를 얻을 수 있게 된다.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 및 그 제조 방법에 의하면 반도체 칩의 입출력패드와 리드간의 전기적인 입출력 연결을 도전성 접속수단을 사용하여 연결하는 동시에 도전성 접속수단이 융착되는 리드의 일부분을 하프에칭 처리함에 따라, 반도체 패키지의 전체적인 두께를 현격히 줄어 경박단소화를 실현할 수 있는 장점이 있다.
또한, 반도체 칩의 상면과, 칩탑재판의 저면과, 리드의 저면 및 외측면이 외부로 노출됨에 따라, 반도체 칩의 열방출 효과를 극대화킬 수 있는 장점이 있다.

Claims (7)

  1. 반도체 칩의 크기보다 작은 칩탑재판과;
    상기 칩탑재판에 접착수단으로 부착되되, 하면에 다수의 입출력패드가 형성된 반도체 칩과;
    상기 칩탑재판의 사방에 인접되게 위치되고, 상기 반도체 칩의 입출력패드와 마주보는 면이 하프 에칭된 면으로 형성된 다수의 리드와;
    서로 마주보고 있는 상기 반도체 칩의 입출력패드와 상기 리드의 하프에칭된 면간을 연결하며 융착된 도전성 접속수단과;
    상기 반도체 칩의 상면과, 칩탑재판의 저면과, 리드의 외측면 및 저면을 외부로 노출시키면서, 반도체 칩과 리드와 도전성 접속수단을 몰딩하고 있는 수지로 구성된 것을 특징으로 하는 반도체 패키지.
  2. 제 1 항에 있어서, 상기 반도체 칩이 보이지 않게 반도체 칩의 상면까지 수지로 몰딩된 구조를 특징으로 하는 반도체 패키지.
  3. 삭제
  4. 제 1 항에 있어서, 상기 도전성 접속수단이 융착되는 상기 리드의 하프에칭된 면에는 도전성 접속수단과 융착 친화성이 있는 코팅금속재로 코팅된 것을 특징으로 하는 반도체 패키지.
  5. 제 1 항 또는 제 4 항에 있어서, 상기 도전성 접속수단은 솔더볼 또는 골드볼인 것을 특징으로 하는 반도체 패키지.
  6. 제 4 항에 있어서, 상기 코팅 금속재는 티타늄 또는 알루미늄인 것을 특징으로 하는 반도체 패키지.
  7. 반도체 칩이 부착되는 칩탑재판과, 이 칩탑재판의 사방에 인접되게 위치되고 각 안쪽부분이 하프 에칭된 다수의 리드를 포함하는 리드프레임을 제공하는 단계와;
    웨이퍼 상태의 각 반도체 칩의 입출력패드에 도전성 접속수단을 융착한 후,개개의 단위로 소잉하여 구비된 반도체 칩을 상기 칩탑재판에 접착수단으로 부착하는 동시에 상기 도전성 접속수단이 리드의 하프에칭된 면에 융착되어 연결되도록 한 단계와;
    상기 반도체 칩의 상면과, 칩탑재판의 저면과, 리드의 외측면 및 저면을 외부로 노출시키면서, 반도체 칩과 도전성 접속수단과 칩탑재판과 리드등을 수지로 몰딩하는 단계로 이루어진 것을 특징으로 하는 반도체 패키지 제조 방법.
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