KR100387257B1 - Method of forming a metal line in a semiconductor device - Google Patents
Method of forming a metal line in a semiconductor device Download PDFInfo
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- KR100387257B1 KR100387257B1 KR10-1999-0064012A KR19990064012A KR100387257B1 KR 100387257 B1 KR100387257 B1 KR 100387257B1 KR 19990064012 A KR19990064012 A KR 19990064012A KR 100387257 B1 KR100387257 B1 KR 100387257B1
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- via hole
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000002184 metal Substances 0.000 title claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052802 copper Inorganic materials 0.000 claims abstract description 30
- 239000010949 copper Substances 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 238000007517 polishing process Methods 0.000 claims description 9
- 239000000243 solution Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 3
- 229910004156 TaNx Inorganic materials 0.000 claims description 2
- 229910010421 TiNx Inorganic materials 0.000 claims description 2
- 229910008485 TiSiNx Inorganic materials 0.000 claims description 2
- 229910008835 WSiNx Inorganic materials 0.000 claims description 2
- 239000003929 acidic solution Substances 0.000 claims description 2
- 239000007864 aqueous solution Substances 0.000 claims description 2
- 239000011148 porous material Substances 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000003405 preventing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 다층 금속 배선 형성공정에서 높은 단차비를 갖는 좁은 비아(via) 및 트랜치(trench)를 내부 공공 없이 완전 매립하기 위하여 패턴 상에 확산 방지막을 형성하고, 시드(Seed)막을 형성한 후 화학기계연마(CMP) 공정을 이용하여 패턴되지 않은 상부의 시드막을 제거한다. 그후 묽은 식각 용액으로 비아홀이나 트랜치 측벽의 시드막을 제거하여 확산방지막을 완전 노출시키고, 비아홀 및 트랜치 바닥에만 시드막을 잔류시킨 다음 구리 전기도금 공정으로 구리막이 비아 홀 및 트랜치 바닥에서부터 성장하게 하여 좁은 비아홀 및 트랜치를 공공없이 매립되도록 하는 반도체 소자의 금속 배선 형성방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein a diffusion barrier layer is formed on a pattern to completely fill narrow vias and trenches having high step ratios without internal pores in a multilayer metal wiring forming process. After the seed film is formed, the upper seed film of the unpatterned layer is removed using a chemical mechanical polishing (CMP) process. A thin etching solution is then used to remove the seed film from the via hole or trench sidewalls to completely expose the diffusion barrier, leaving the seed film only at the bottom of the via hole and the trench bottom, and then using a copper electroplating process to allow the copper film to grow from the via hole and the bottom of the trench. Provided is a method of forming a metal wiring in a semiconductor device in which a trench is buried without voids.
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 다층 구리비아 홀(via hole)형성 및 배선 공정에서 높은 단차비를 갖는 좁은 비아 및 트랜치 (trench)를 내부 공공 없이 완전 매립하기 위한 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, the present invention relates to a semiconductor device for completely filling narrow vias and trenches having high step ratios without internal voids in multilayer copper via hole formation and wiring processes. It relates to a metal wiring forming method.
일반적으로, 차세대 반도체 소자의 급격한 고성능화 추세로 비아 홀 크기의 감소와 단차(Aspect ratio)의 증가로 인하여 우수한 단차 피복성(Step coverage), 비아 매립 및 소자의 고속화가 요구되는데 이를 위하여 다마신 패턴상에 구리 금속을 이용한 다층금속 배선 공정이 매우 유용한 방법으로 제시되고 있는 실정이다.In general, due to the rapid increase in performance of next-generation semiconductor devices, excellent step coverage, via filling, and high speed of devices are required due to the reduction of the via hole size and the increase of the aspect ratio. The multi-layer metal wiring process using copper metal is proposed as a very useful method.
종래, 반도체 소자의 금속 배선 형성방법을 도 1a 및 도 1b를 참고하여 설명하면 다음과 같다.Conventionally, a method of forming metal wirings of a semiconductor device will be described with reference to FIGS. 1A and 1B.
도 1a를 참조하면, 반도체 기판(10) 절연막(11) 및 식각방지층(12)을 순차적으로 형성한 후 식각방지막(12) 및 절연막(11)을 일부분을 식각하여 비아 홀 및 트랜치를 형성한다. 비아 홀 및 트랜치가 형성된 전체 상부면에 확산방지막(13)을 형성한 후 구리금속으로 이루어진 시드막(14)을 형성한다.Referring to FIG. 1A, after the insulating film 11 and the etch stop layer 12 of the semiconductor substrate 10 are sequentially formed, portions of the etch stop 12 and the insulating film 11 are etched to form via holes and trenches. After the diffusion barrier 13 is formed on the entire upper surface of the via hole and the trench, the seed layer 14 made of copper metal is formed.
상기에서, 시드막(14) 및 확산방지막(13)은 플라즈마 기상증착방법으로 형성되나, 비아 크기의 감소 및 급격한 단차의 증가로 인한 열악한 층덮힘성으로 인하여 오버 행(Overhang;14a) 또는 증착이 불연속되는 지점(14b) 등이 발생한다.In the above, the seed film 14 and the diffusion barrier 13 are formed by a plasma vapor deposition method, but the overhang 14a or deposition is discontinuous due to poor layer covering properties due to a decrease in the via size and a sharp increase in the step height. The point 14b etc. which arises arise.
도 1b를 참조하면, 전체 상부면에 전기도금을 이용하여 구리막(15)을 증착한 후 화학적 기계적 연마공정으로 식각방지막(12)이 노출될 때까지 구리막(15)을 제거하여 비아 홀 및 트랜치를 매립하여 다층 금속배선공정을 완료한다.Referring to FIG. 1B, the copper layer 15 is deposited on the entire upper surface by electroplating, and then the copper layer 15 is removed until the etch stop layer 12 is exposed by a chemical mechanical polishing process. Fill the trench to complete the multi-layer metallization process.
상술한 바와같이, 종래 반도체 소자의 금속 배선형성방법은 열악한 층덮힘성으로 인한 오버 행(14a) 및 불연속 지점(14b) 등으로 인하여 후속 구리막(15) 형성공정시 비아 홀 내부에 공공(15a) 등이 형성되어 소자의 전기적 특성을 저하시키는 원인이 된다. 그리고, 이러한 금속 배선에 공공(15a) 등이 형성되는 문제를 해결하기 위하여 화학 기상증착방법으로 시드막(14)을 형성하는 방법이 연구되고 있으나, 열악한 접착성, 공정 안전성 및 높은 비용 등의 문제가 있다.As described above, the metal wiring forming method of the conventional semiconductor device has a hole 15a inside the via hole during the subsequent copper film 15 forming process due to the overhang 14a and the discontinuity point 14b due to poor layer covering properties. Etc. are formed, which causes a decrease in the electrical characteristics of the device. In addition, in order to solve the problem of forming the cavity 15a in the metal wiring, a method of forming the seed film 14 by the chemical vapor deposition method has been studied, but problems such as poor adhesiveness, process safety and high cost There is.
따라서, 본 발명은 다층 금속 배선 형성공정에서 높은 단차비를 갖는 좁은 비아 홀 및 트랜치를 내부 공공 없이 구리 금속을 완전 매립할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of completely embedding a copper metal without an internal hole in a narrow via hole and a trench having a high step ratio in a multilayer metal wiring forming process.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성방법은 반도체 기판 상에 절연막 및 식각방지막을 순차적으로 형성한 후 식각방지막 및 절연막 일부분을 식각하여 비아 홀 및 트랜치를 포함하는 패턴을 형성하는 단계; 상기 비아 홀 및 트랜치를 포함한 전체상부면에 확산방지막 및 시드층을 형성한 후 연마공정으로 시드층 일부를 제거하여 비아 홀 및 트랜치 내부에만 시드층이 남도록 하는 단계; 식각 용액을 이용하여 비아 홀 및 트랜치 측벽에 불연속적으로 형성된 상기 시드막을 제거하여 비아 홀 및 트랜치 바닥면에만 상기 시드막이 형성되도록 한 후 전체 상부면에 구리막을 증착하는 단계; 연마공정으로 식각방지막이 노출되도록 상기 구리막을 일부제거하여 상기 비아 홀 및 트랜치에 구리막을 매립하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention may sequentially form an insulating film and an etch stop layer on a semiconductor substrate, and then etching the portion of the etch stop layer and the insulating layer to form a pattern including a via hole and a trench. Forming; Forming a diffusion barrier layer and a seed layer on the entire upper surface including the via hole and the trench, and then removing a portion of the seed layer by a polishing process so that the seed layer remains only inside the via hole and the trench; Removing the seed film discontinuously formed in the via hole and the trench sidewall by using an etching solution so that the seed film is formed only on the via hole and the trench bottom surface, and then depositing a copper film on the entire upper surface; And removing a portion of the copper film to expose the etch stop layer by a polishing process, and embedding a copper film in the via hole and the trench.
도 1a 및 도 1b는 종래 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of devices for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 및 20 : 반도체 기판 11 및 21 : 절연막10 and 20: semiconductor substrate 11 and 21: insulating film
12 및 22 : 식각방지막 13 및 23 : 확산방지막12 and 22: etching barrier 13 and 23: diffusion barrier
14 및 24 : 시드층 15 및 25 : 구리막14 and 24: seed layer 15 and 25: copper film
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2C are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 기판(20) 상에 절연막(21) 및 식각방지막(22)을 순차적으로 형성한 후 식각방지막(22) 및 절연막(21) 일부분을 식각하여 비아 홀 및 트랜치를 포함하는 패턴을 형성한다. 비아 홀 및 트랜치를 포함한 전체상부면에 확산방지막(23) 및 시드(seed)층(24)을 형성한 후 식각방지막(22)이 노출되도록 화학적 기계적 연마공정으로 시드층(24) 일부를 제거하여 비아 홀 및 트랜치 내부에만 시드층(24)이 형성되도록 한다.Referring to FIG. 2A, after the insulating film 21 and the etch stop layer 22 are sequentially formed on the semiconductor substrate 20, portions of the etch stop layer 22 and the insulating layer 21 are etched to include via holes and trenches. Form a pattern. After forming the diffusion barrier 23 and the seed layer 24 on the entire upper surface including the via hole and the trench, a portion of the seed layer 24 is removed by chemical mechanical polishing to expose the etch barrier 22. The seed layer 24 is formed only in the via hole and the trench.
상기에서, 절연막(21)은 3000 내지 10000Å 두께로 형성하되, 저유전율의 폴리머 계열의 막을 시핀 온(spin on) 방식으로 도포하거나, 화학기상증착법을 이용하여 메칠 또는 에칠을 함유한 소스를 사용한 저밀도 산화막으로 이루어진다. 식각방지막(22)은 구리확산 방지 특성을 가지도록 화학기상증착법으로 질소를 함유한 실리콘 질화막 또는 실리콘 질화산화막으로 이루어진다. 비아 홀 및 트랜치를 포함한 패턴은 단일 다마슨(Damascene) 방법을 이용하거나, 이중 다마슨 방법을 이용하여 형성한다.In the above, the insulating film 21 is formed to a thickness of 3000 to 10000Å, a low dielectric constant polymer-based film is applied on the spin on (spin on) method, or using a chemical vapor deposition method using a low density using a source containing methyl or ethyl It is made of an oxide film. The etch stop layer 22 is formed of a silicon nitride film or a silicon nitride oxide film containing nitrogen by chemical vapor deposition to have a copper diffusion preventing property. Patterns including via holes and trenches are formed using a single Damascene method or using a double Damason method.
확산방지막(23)은 TiNx, Ta, TaNx, TaCx, WxN, TiSiNx 및 WSiNx 중 어느 하나이상으로 이루어지되, 물리기상증착방법으로 100Å 이상 두께로 증착하고, 비아홀 측벽에는 10Å 이상의 두께로 형성하거나, 화학기상증착 방법으로 10Å 이상 두께로 증착하고, 비아 홀 측벽에는 10Å 이상의 두께로 증착한다.The diffusion barrier 23 is made of any one or more of TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, and WSiNx, and is deposited to a thickness of 100 Å or more by physical vapor deposition, and formed to a thickness of 10 Å or more on the sidewalls of via holes, or by chemical It is deposited by a vapor deposition method to a thickness of 10Å or more, and to the via hole sidewalls to a thickness of 10Å or more.
시드층(24)은 비아 홀 바닥의 두께가 측벽 두께의 2 내지 4배 이상되도록 물리기상증착방법을 이용하여 -50 내지 350℃ 온도에서 웨이퍼 전면에서의 두께가 200 내지 2000Å 두께로 증착하거나, 화학기상증착방법을 이용하여 100 내지 400℃ 의 온도에서 20 내지 1000Å 두께로 증착한다. 시드층(24)은 구리금속으로 이루어지거나, 확산방지막(23) 보다 비저항이 작은 금속막으로 이루어진다. 화학적 기계적 연마공정은 Al2O3가 함유된 슬러리(slurry)를 이용한다.The seed layer 24 is deposited to a thickness of 200 to 2000 microns on the entire surface of the wafer at a temperature of -50 to 350 ° C. using a physical vapor deposition method such that the thickness of the via hole bottom is 2 to 4 times the thickness of the sidewall. It is deposited to a thickness of 20 to 1000 Pa at a temperature of 100 to 400 ℃ using the vapor deposition method. The seed layer 24 is made of copper metal, or is made of a metal film having a lower specific resistance than the diffusion barrier 23. The chemical mechanical polishing process uses a slurry containing Al 2 O 3 .
도 2b를 참조하면, 구리식각 용액을 이용하여 비아 홀 및 트랜치 측벽에 불연속적으로 형성된 시드막(24)을 제거하여 비아 홀 및 트랜치 바닥면에만 시드막(24)이 형성되도록 한 후 전체 상부면에 구리막(25)을 증착한다.Referring to FIG. 2B, the seed layer 24 is formed on the bottom surface of the via hole and the trench by removing the seed layer 24 discontinuously formed in the via hole and the trench sidewall using a copper etching solution, and then the entire upper surface. The copper film 25 is deposited on it.
상기에서, 구리 식각 용액은 H3PO4+HF, H3PO4, H3PO4+HNO3+HF 및 H2SO4+H2O2중 어느 하나 이상을 함유한 묽은 수용액을 이용하거나, SO4 2-이온을 포함하는 묽은 산성 용액을 이용하고, 식각공정시 구리 식각율은 분당 10 내지 200Å 가 되도록 조절한다. 구리막(25)은 구리전기도금방법으로 형성한다.In the above, the copper etching solution using a dilute aqueous solution containing at least one of H 3 PO 4 + HF, H 3 PO 4 , H 3 PO 4 + HNO 3 + HF and H 2 SO 4 + H 2 O 2 or , Using a dilute acidic solution containing SO 4 2- ions, and the copper etching rate during the etching process is adjusted to 10 to 200 kPa per minute. The copper film 25 is formed by a copper electroplating method.
도 2c를 참조하면, 전체 상부면에 증착된 구리막(24)을 화학적 기계적 연마공정을 이용하여 식각방지막(22)이 노출되도록하여 비아 홀 및 트랜치에 구리막(24)을 매립한다.Referring to FIG. 2C, the copper layer 24 is buried in the via hole and the trench by exposing the copper layer 24 deposited on the entire upper surface to expose the etch stop layer 22 using a chemical mechanical polishing process.
상기에서, 화학적 기계적 연마공정은 Al2O3가 함유된 슬러리(slurry)를 이용한다.In the above, the chemical mechanical polishing process uses a slurry containing Al 2 O 3 .
상술한 바와같이 본 발명은 다층 금속 배선 형성공정에서 높은 단차비를 갖는 좁은 비아(via) 및 트랜치(trench)를 내부 공공 없이 구리금속을 완전 매립할 수 있어 비아 콘택의 저항을 낮추게 되므로 반도체 소자의 전기적 특성이 향상되는 효과가 있다.As described above, according to the present invention, since a narrow via and trench having a high step ratio in a multilayer metal wiring forming process can completely fill a copper metal without internal pores, the resistance of the via contact is lowered. The electrical characteristics are improved.
Claims (9)
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| KR100997433B1 (en) * | 2003-07-22 | 2010-11-30 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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| KR100440476B1 (en) * | 2001-12-14 | 2004-07-14 | 아남반도체 주식회사 | Method for fabricating semiconductor device |
| KR100421913B1 (en) * | 2001-12-22 | 2004-03-11 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| US6709970B1 (en) * | 2002-09-03 | 2004-03-23 | Samsung Electronics Co., Ltd. | Method for creating a damascene interconnect using a two-step electroplating process |
| KR100783274B1 (en) * | 2006-11-29 | 2007-12-06 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
| KR100857008B1 (en) * | 2006-12-27 | 2008-09-04 | 동부일렉트로닉스 주식회사 | Method for Forming of Metal Wiring in Semiconductor Divice |
| US8764961B2 (en) | 2008-01-15 | 2014-07-01 | Applied Materials, Inc. | Cu surface plasma treatment to improve gapfill window |
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| JPH02246324A (en) * | 1989-02-08 | 1990-10-02 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH0729907A (en) * | 1993-07-15 | 1995-01-31 | Nec Corp | Lsi wiring structure and its formation |
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| KR100997433B1 (en) * | 2003-07-22 | 2010-11-30 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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