JPH0729907A - Lsi wiring structure and its formation - Google Patents

Abstract

PURPOSE:To realize graphoepitaxy at a low temperature by constituting material of a bottom side part on the sidewall of a trench part of a wiring pattern, by using material whose absorbability to wiring material is larger than that of the material of trench bottom surface and the sidewall upper part. CONSTITUTION:On an Si substrate 1, SiO2 2 whose absorbability is small is deposited, and SixN1-x 3 whose absorbability is large as compared with SiO2 is deposited on the SiO2 2. Next, SiO2 4 whose absorbability is small is deposited on the SixN1-x 3. The SixN1-x 3 and the SiO2 4 are worked, only the SixN1-x is so eliminated that the bottom of a trench becomes the SiO2 2, and a wiring- shaped trench is formed. Deposited Cu nucleus 5a has orientation (111) to both the bottom and the sidewall, so that buried Cu is subjected to graphoepitaxial growth. Thereby LSI wiring structure having large grain diameter and high orientation can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an LSI wiring, which is one of semiconductor element manufacturing processes.

[0002]

2. Description of the Related Art Conventionally, Al or Al alloy has been used as a wiring material for LSI, but for further miniaturization in the future, the signal due to the high resistance value of Al or Al alloy is used. There is a problem of low reliability due to delay of transmission speed and low migration resistance.
Au, Ag, and Cu are expected as wiring materials that replace Al because of their low resistance and high migration resistance. Conventional Al and Al alloy wiring have been processed at a low temperature by forming AlCl ₃ having a high vapor pressure by a dry etching method using chlorine. However, the chlorine compounds of Au, Ag, and Cu have a low vapor pressure, and it is difficult to process them at a low temperature by the dry etching method. Therefore, wiring formation by an embedding method has been attempted. This method is a method of forming a wiring by forming a groove in a wiring shape and selectively growing a wiring material in the groove, or by uniformly depositing the wiring material on a portion other than the groove and then etching back the wiring material. This embedded wiring is expected to have graphoepitaxy, but in reality, since the manufacturing process temperature is low, graphoepitaxy is difficult. An object of the present invention is to provide an LSI wiring structure having a large grain size and a high orientation, which realizes graphoepitaxy at a low temperature in embedded wiring, and a method for forming the same.

[0003]

According to the present invention, there is provided an LSI wiring structure in which a wiring pattern having a groove formed in a wiring shape is formed on a substrate, and a wiring material is embedded in the groove, and a groove portion of the wiring pattern. The material of the bottom portion of the side wall of L is made of a material having a stronger adsorption force to the wiring material than the material of the bottom surface and the upper portion of the side wall of the groove.
The SI wiring structure. Here, the combination of a material having a weak adsorption force and a material having a strong adsorption force is SiO ₂ and S, respectively.
i _x N _1-x , or SiO ₂ and TiN, or SiO ₂ and T
It is preferably iW, or Si _x N _1-x and TiN, or Si _x N _1-x and TiW.

Further, a method for forming the LSI wiring structure includes a step of depositing a first material on a substrate and a stronger adsorption force to the wiring material than the first material on the first material. Depositing a second material, depositing on the second material a third material having a weaker adsorption force for the wiring material than the second material, the second material and the third material
Processing the material described above to form a wiring-shaped groove having the first material as the bottom surface of the groove, depositing the wiring material in the groove, and removing the wiring material deposited outside the groove. And a step of performing.

[0005]

The wiring is formed by using a material having a weak adsorption force to the wiring material on the bottom surface of the groove of the embedded wiring pattern and an upper portion of the side wall, and a material having a strong adsorption force to the wiring material on the bottom portion of the side wall. The basic principle of graphoepitaxy is that the orientation of crystal grains is influenced not only by the underlying layer but also by the side wall to allow epitaxial growth. 1000
In the case of high temperature deposition of about ℃ or more, no matter where the nuclei grow in the buried hole, the crystal grains rotate so that the interfacial energy with the wall is minimized due to the high degree of in-plane rotational freedom of the crystal grains. Grapho-epitaxial growth is possible because all the crystal grains have the same orientation. However, in-plane rotation of crystal grains with a filling width is difficult in low temperature deposition that is allowed in the LSI manufacturing process, and in order to perform graphoepitaxy, nucleation is caused at the boundary between the wall and the bottom, The orientation must be the same. In the present invention, a material having a weak adsorption force is used for the bottom surface and the upper portion of the side wall of the groove, and a material having a strong adsorption force is used for the bottom portion of the side wall. Originating from the bottom boundary, graphoepitaxy is possible.
By realizing graphoepitaxy at low temperature, it becomes possible to increase the grain size and orientation of embedded wiring. By increasing the grain size and increasing the orientation, the migration resistance of the wiring is improved and a highly reliable wiring is possible.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. Example 1 FIG. 1 is a sectional view of a substrate showing an example of an LSI wiring forming method of the present invention. First, as shown in FIG.
SiO ₂ 2, which is a first material having a weak adsorption force, is deposited on the substrate 1 by the CVD method in an amount of 100 to 10,000 angstroms, and is a second material having a stronger adsorption force than SiO ₂ on SiO ₂ 2. 5 to _{1 of} Si _x N _1-x 3 by the CVD method
00 angstrom is deposited, and then SiO ₂ 4 which is a third material having a weak adsorption force is deposited on Si _x N _{1 -x} 3 by 100 to 10000 angstrom by the CVD method. Next, as shown in FIG. 1 (b), processing the Si _x N _1-x 3 and SiO ₂ 4 by conventional dry etching technique, Si as the bottom of the groove is SiO _{2 2 x} N _1-x Only this is removed to form a wiring-shaped groove. Next, Cu of wiring material
When deposited at 00 ° C., Cu nuclei 5a are formed only at the boundary between the bottom and the sidewall as shown in FIG. 1C at the initial stage of deposition. The Cu nuclei 5a are (1
11) Because of the orientation, the embedded Cu undergoes graphoepitaxial growth. If deposition is continued as it is, Fig. 1
As shown in (d), single crystal Cu5 is formed inside the groove, and polycrystalline Cu6 is formed outside. After that, the polycrystalline Cu outside the groove is removed by a normal etchback technique to form a single crystal Cu wiring as shown in FIG. 1 (e).

The above results indicate that the weakly adsorbing material and the strongly adsorbing material are not SiO ₂ and Si _x N _{1 -x} , but SiO ₂ and T, respectively.
iN, or SiO ₂ and TiW, or Si _x N _1-x and T
Similar results can be obtained with iN or Si _x N _1-x and TiW. The wiring material may be deposited by sputtering or CVD. Further, both the first material and the third material having a weak adsorption force may be the same material or may be different materials. Further, as the wiring material, in addition to Cu used in this example, Au, Ag, A
It may be 1 or the like.

[0008]

As described above, according to the present invention, it is possible to realize an LSI wiring structure having a large grain size and a high orientation by realizing graphoepitaxy in a buried wiring.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment of an LSI wiring forming method according to the present invention.

[Explanation of symbols]

1 Si substrate 2 SiO ₂ 3 Si _x N _1-x 4 SiO ₂ 5 single crystal Cu 5a Cu nucleus 6 polycrystalline Cu

Claims (3)

[Claims] 1. An LSI in which a wiring pattern having wiring-shaped grooves is formed on a substrate and wiring material is embedded in the grooves.
In the wiring structure, the material of the bottom portion of the side wall of the groove portion of the wiring pattern is made of a material having a stronger adsorptive power to the wiring material than the material of the bottom surface and the upper portion of the side wall of the groove portion. Wiring structure. 2. A combination of a material having a weak adsorption force and a material having a strong adsorption force is SiO ₂ and Si _x N _1-x , or SiO ₂ and TiN, or SiO ₂ and TiW, or S.
The LSI wiring structure according to claim 1, wherein the LSI wiring structure is i _x N _1-x and TiN, or Si _x N _1-x and TiW. 3. A step of depositing a first material on a substrate,
A step of depositing a second material having a stronger adsorption force on the first material on the wiring material than the first material, and a weaker adsorption force on the second material than the second material on the wiring material A step of depositing a third material, a step of processing the second material and the third material to form a wiring-shaped groove having the first material as a bottom surface of the groove, and A method of forming an LSI wiring, comprising: a step of depositing a wiring material; and a step of removing the wiring material deposited outside the groove.