KR100376881B1 - Power on reset circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit, and generates a stable reset signal to initialize a chip, thereby improving the stability of chip operation. To this end, the power-on reset circuit of the present invention includes a power detecting unit for detecting an input of a power supply voltage, a first signal delay unit for delaying and outputting an output signal of the power detecting unit, and an output signal of the first signal delay unit. A voltage compensator for outputting the power voltage and compensating for a small slope when the power voltage is applied, a schmitter inverter part for detecting a level of the power voltage output from the voltage compensator and outputting an inverted signal if the voltage is higher than a predetermined voltage; And a second signal delay unit for delaying the output signal of the schmitter inverter unit to generate a power-on reset signal (POR), and outputting a power voltage to the output terminal of the first signal delay unit by an inverted signal of the output signal of the schmitter inverter unit. And a signal feedback unit for transmitting to the input terminal of the voltage compensation unit.

Description

Power on reset circuit {POWER ON RESET CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power on reset circuit, and more particularly to a power on reset circuit which improves the stability of chip operation by generating a stable reset signal to initialize a chip.

In general, a power on reset circuit is a circuit that generates a power on reset signal (POR) that detects power supply to a chip and initializes the chip.

1 is a circuit diagram of a conventional power-on reset circuit.

The conventional power-on reset circuit includes a capacitor C1 connected between a power supply voltage Vcc and a node Nd1, a resistor R1 connected between the node Nd1 and a ground voltage Vss, and The inverters IV1 and IV2 are connected in series between the node Nd1 and the node Nd2 for outputting the power-on reset signal POR.

When the power is turned on, the charge is charged in the capacitor C1, and the charge is gradually discharged by the delay time by the resistor R1. In this case, the power-on reset signal POR is generated by using the time for which the charge stored by the capacitor C1 is discharged through the resistor R1.

However, the conventional power-on reset circuit having the above configuration has a problem in that the power-on reset signal POR is not properly generated when the slope of the applied power voltage Vcc is small.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to generate a stable power-on reset signal (POR) to initialize the chip, thereby providing a power-on reset circuit which improves the stability of chip operation. It is.

1 is a circuit diagram of a conventional power-on reset circuit.

2 is a circuit diagram of a power-on reset circuit according to the present invention;

3A and 3B are output waveform diagrams comparing the power-on reset signal of the prior art and the present invention.

(Explanation of symbols for the main parts of the drawing)

10: power detector 12: first signal delay unit

14 power supply compensation unit 16 Schmitt inverter unit

18: second signal delay unit 20: signal feedback unit

The power-on reset circuit of the present invention for achieving the above object of the present invention,

In the power-on reset circuit,

A power detecting unit detecting an input of a power supply voltage,

A first signal delay unit for delaying and outputting an output signal of the power detection unit;

A voltage compensator for outputting a power voltage by an output signal of the first signal delay unit to compensate for a small slope when a power voltage is applied;

A schmitt inverter unit for detecting a level of the power supply voltage output from the voltage compensating unit and outputting an inverted signal when the voltage is higher than a predetermined voltage;

A second signal delay unit configured to delay an output signal of the schmitter inverter unit to generate a power-on reset signal POR;

And a signal feedback unit configured to transmit a power supply voltage to an output terminal of the first signal delay unit and an input terminal of the voltage compensation unit by an inverted signal of the output signal of the schmitter inverter unit.

The power detection unit includes a first capacitor connected between the power supply voltage and the first node, and a first resistor connected between the first node and the ground voltage.

The first signal delay unit is connected between a first inverter connected between the first node and a second node, a second capacitor connected between the second node and a ground voltage, and between the second node and a third node. A second inverter and a third capacitor connected between the third node and the ground voltage.

The voltage compensating unit includes a first PMOS transistor that transmits a power supply voltage to a fourth node by a signal of the third node, and a fourth capacitor connected between the fourth node and a ground voltage.

The schmitter inverter unit is configured of a schmitter inverter connected between the fourth node and the fifth node.

The second signal delay unit is connected between a fifth capacitor connected between the fifth node and the ground voltage, a fourth inverter connected between the fifth node and the sixth node, and connected between the sixth node and the ground voltage. And a fifth inverter connected between the sixth capacitor and the sixth node for outputting the sixth node and the power-on reset signal POR.

The signal feedback unit includes a second PMOS transistor that transmits a power supply voltage to the third node by a signal of the sixth node.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2 is a circuit diagram of a power-on reset circuit according to the present invention.

The power-on reset circuit of the present invention includes a power supply detecting unit 10, a first signal delay unit 12, a voltage compensating unit 14, a Schmitt inverter unit 14, a second signal delay unit 18, and a signal feedback unit. It consists of a part 20.

The power detector 10 includes a capacitor C11 connected between the power supply voltage Vcc and the node Nd11, and a resistor R11 connected between the node Nd11 and the ground voltage Vss. . When the power is turned on, the power detector 10 charges the capacitor C11 and gradually discharges the charge by a delay time by the resistor R11.

The first signal delay unit 12 includes an inverter IV11 connected between the node Nd11 and a node Nd12, and a capacitor C12 connected between the node Nd12 and the ground voltage Vss. And an inverter IV12 connected between the node Nd12 and the node Nd13, and a capacitor C13 connected between the node Nd13 and the ground voltage Vss. The first signal delay unit 12 delays the output signal of the power detection unit 10 and outputs the delayed signal to the node Nd13.

The voltage compensator 14 is configured between the PMOS transistor MP1 for transmitting the power supply voltage Vcc to the node Nd14 by the signal of the node Nd13, and between the node Nd14 and the ground voltage Vss. It consists of the connected capacitor C14. The voltage compensator 14 is a circuit for compensating for a small slope of the applied power voltage Vcc.

The schmitter inverter section 16 is composed of a schmitter inverter C15 connected between the node Nd14 and the node Nd15. The schmitter inverter unit 16 is used to generate the power-on reset signal POR when the power supply voltage Vcc applied is a predetermined voltage or more.

The second signal delay unit 18 includes a capacitor C15 connected between the node Nd15 and the ground voltage Vss, and an inverter IV14 connected between the node Nd15 and the node Nd16. And an inverter IV15 connected between the capacitor C16 connected between the node Nd16 and the ground voltage Vss, and the node Nd16 outputting the node Nd16 and the power-on reset signal POR. It consists of The second signal delay unit 18 generates a power-on reset signal POR by delaying the output signal of the schmitter inverter unit 16.

The signal feedback unit 20 includes a PMOS transistor MP2 that transmits a power supply voltage Vcc to the node Nd13 by the signal of the node Nd16. The signal feedback unit 20 is a circuit for compensating for a small slope of the applied power voltage Vcc.

The operation of the power-on reset circuit of the present invention having the above configuration will be described.

First, when the power is turned on, the charge is charged in the capacitor C1, and the charge is gradually discharged by the delay time by the resistor R1. Since the inverters IV11 and IV12 are elements having delays, signals of the nodes Nd11 are delayed by the delay inverters IV11 and IV12 and the capacitors C12 and C13 to the node Nd13.

After the delay time, the PMOS transistor MP1 starts to turn on. However, since the current is charged through the feedback transistor MP2, the node Nd13 goes from 'high' to 'low' after the power supply voltage Vcc becomes a predetermined voltage or more and a predetermined time elapses. This is because the threshold voltage is changed using the Schmitt inverter IV13. Therefore, if the signal does not change in the Schmitt inverter IV13 because it does not change over a certain voltage, the signal of the node Nd16 always has a 'low'. Therefore, the feedback transistor MP2 is turned on to compensate for the slope of the voltage.

In addition, the power-on reset circuit of the present invention generates a power-on reset signal (POR) at a voltage capable of initializing the entire chip, and is generated by the first signal delay unit 12 and the second signal delay unit 18. Maintain a constant pulse.

As described above, the present invention uses the signal feedback unit 20 to compensate for the initial voltage in order to improve the instability of the existing power-on reset, and the first signal delay unit 12 to delay and discharge the charge discharge. Was used. Then, when a predetermined voltage or more is applied, the power-on reset circuit operates to have a minimum reset signal voltage, and a second signal delay unit 18 is also added to the rear end to generate a reset signal having a constant pulse width. To do so.

3A and 3B are output waveform diagrams comparing the power-on reset signals of the prior art and the present invention. 3A illustrates a case where the slope of the power supply voltage Vcc is large, and FIG. 3B illustrates a case where the slope of the power supply voltage Vcc is small.

As can be seen from the output waveform diagram, the power-on reset circuit of the present invention solves the problem that the power-on reset signal POR does not occur when the slope of the power supply voltage Vcc is small.

As described above, the power-on reset circuit according to the present invention generates the stable power-on reset signal POR to initialize the chip, thereby improving the stability of the chip operation and improving the reliability of the chip.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (7)

In the power-on reset circuit, A power detecting unit detecting an input of a power supply voltage, A first signal delay unit for delaying and outputting an output signal of the power detection unit; A voltage compensator for outputting a power voltage by an output signal of the first signal delay unit to compensate for a small slope when a power voltage is applied; A schmitt inverter unit for detecting a level of the power supply voltage output from the voltage compensating unit and outputting an inverted signal when the voltage is higher than a predetermined voltage; A second signal delay unit configured to delay an output signal of the schmitter inverter unit to generate a power-on reset signal POR; And a signal feedback unit configured to transmit a power supply voltage to an output terminal of the first signal delay unit and an input terminal of the voltage compensation unit by an inverted signal of the output signal of the schmitter inverter unit. The method of claim 1, And the power detecting unit includes a first capacitor connected between the power supply voltage and the first node, and a first resistor connected between the first node and the ground voltage. The method according to claim 1 or 2, The first signal delay unit is connected between a first inverter connected between the first node and a second node, a second capacitor connected between the second node and a ground voltage, and between the second node and a third node. And a third capacitor connected between the second inverter and the third node and the ground voltage. The method of claim 3, wherein The voltage compensator comprises a first PMOS transistor for transmitting a power supply voltage to a fourth node by a signal of the third node, and a fourth capacitor connected between the fourth node and a ground voltage. Set circuit. The method according to claim 1 or 4, And the schmitter inverter unit comprises a schmitter inverter connected between the fourth node and the fifth node. The method of claim 5, The second signal delay unit is connected between a fifth capacitor connected between the fifth node and the ground voltage, a fourth inverter connected between the fifth node and the sixth node, and connected between the sixth node and the ground voltage. And a fifth inverter connected between the sixth capacitor and the sixth node outputting the sixth node and a power on reset signal (POR). The method according to claim 1 or 6, And the signal feedback unit comprises a second PMOS transistor which transmits a power supply voltage to the third node according to a signal of the sixth node.