KR100324322B1 - Circuit for protecting electrostatic discharge - Google Patents
Circuit for protecting electrostatic discharge Download PDFInfo
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- KR100324322B1 KR100324322B1 KR1019990029976A KR19990029976A KR100324322B1 KR 100324322 B1 KR100324322 B1 KR 100324322B1 KR 1019990029976 A KR1019990029976 A KR 1019990029976A KR 19990029976 A KR19990029976 A KR 19990029976A KR 100324322 B1 KR100324322 B1 KR 100324322B1
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- 239000000872 buffer Substances 0.000 claims abstract description 8
- 238000007599 discharging Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 7
- 101001114059 Homo sapiens Protein-arginine deiminase type-1 Proteins 0.000 description 7
- 102100023222 Protein-arginine deiminase type-1 Human genes 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 101100163833 Arabidopsis thaliana ARP6 gene Proteins 0.000 description 5
- 101100524516 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA2 gene Proteins 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 101100123053 Arabidopsis thaliana GSH1 gene Proteins 0.000 description 2
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 description 2
- 101150092599 Padi2 gene Proteins 0.000 description 2
- 102100035735 Protein-arginine deiminase type-2 Human genes 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 125000000740 n-pentyl group Chemical group [H]C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])* 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- Engineering & Computer Science (AREA)
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Abstract
본 발명은 정전방전 보호회로에 관한 것으로, 종래에는 패드에 고압 또는 저압의 정전펄스가 인가되면 해당 패드에 접속된 정전방전 보호부가 개별적으로 정전펄스를 방전시킴에 따라 다수의 정전방전 보호부를 효과적으로 활용하지 못하여 방전이 취약하며, 기대치 이상의 정전펄스가 인가되는 경우에 방전능력의 한계로 인해 내부회로가 파괴되는 문제점이 있었다. 따라서, 본 발명은 패키지 외부의 핀을 통해 전기신호를 인가받는 다수의 패드와; 상기 패드에 각기 접속되어 인가된 전기신호가 정전펄스일 경우에 이를 방전하는 정전방전 보호부와; 상기 정전방전 보호부에 각기 접속되어 정전펄스가 아닐 경우에 정전방전 보호부로부터 전기신호를 입력받는 내부 입력버퍼와; 상기 임의의 패드에 정전펄스가 인가되면, 다수의 패드 및 그에 각각 접속된 정전방전 보호부로 방전경로가 형성되도록 인접하는 패드 사이에 각각 접속되는 방전경로 형성부로 구성되는 정전방전 보호회로를 통해 임의의 패드에 인가되는 고압 또는 저압의 정전펄스에 대해 인접하는 패드로 연결경로를 형성하도록 하여 정전펄스의 방전을 분산시킴에 따라 방전효율을 높이고, 보다 높은 전압의 정전펄스에 대해서 내부회로를 보호할 수 있게 되어 정전방전 보호회로의 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention relates to an electrostatic discharge protection circuit. In the related art, when a high or low voltage electrostatic pulse is applied to a pad, the electrostatic discharge protection unit connected to the pad discharges the electrostatic pulse individually, thereby effectively utilizing a plurality of electrostatic discharge protection units. There is a problem in that the discharge is vulnerable and the internal circuit is destroyed due to the limitation of the discharge capacity when an electrostatic pulse exceeding the expected value is applied. Thus, the present invention provides a plurality of pads for receiving an electrical signal through a pin outside the package; An electrostatic discharge protection unit for discharging the electric signals connected to the pads when the applied electric signals are electrostatic pulses; An internal input buffer connected to the electrostatic discharge protection unit and receiving an electric signal from the electrostatic discharge protection unit when the electrostatic discharge protection unit is not an electrostatic pulse; When an electrostatic pulse is applied to the arbitrary pads, the electrostatic discharge protection circuit includes a discharge path forming unit connected between adjacent pads to form a discharge path to a plurality of pads and electrostatic discharge protection units respectively connected thereto. Connection paths are formed by adjacent pads to the high or low voltage electrostatic pulses applied to the pads, thereby distributing the discharge of the electrostatic pulses, thereby increasing the discharge efficiency and protecting the internal circuits against the electrostatic pulses of higher voltage. This has the effect of improving the reliability of the electrostatic discharge protection circuit.
Description
본 발명은 정전방전 보호회로에 관한 것으로, 특히 임의의 패드에 인가되는 고압 또는 저압의 정전펄스에 대해 인접하는 패드로 연결경로를 형성하도록 하여 정전펄스의 방전을 분산시키기에 적당하도록 한 정전방전 보호회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection circuit, and in particular, electrostatic discharge protection that is suitable for dispersing discharge of electrostatic pulses by forming connection paths to adjacent pads for high or low voltage electrostatic pulses applied to any pad. It is about a circuit.
종래의 정전방전 보호회로를 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the conventional electrostatic discharge protection circuit in detail with reference to the drawings as follows.
먼저, 도1은 종래 정전방전 보호회로의 레이아웃도로서, 이에 도시한 바와같이 패키지 외부의 핀(미도시)을 통해 입력되는 전기신호는 패드(PAD1,PAD2)에 인가되고, 다시 패드(PAD1,PAD2)에 각각 접속되어 정전펄스를 방전하는 정전방전 보호부(ESD1,ESD2)를 통해 내부 입력버퍼(BUF1,BUF2)로 입력된다.First, FIG. 1 is a layout diagram of a conventional electrostatic discharge protection circuit. As shown therein, an electrical signal input through a pin (not shown) outside the package is applied to the pads PAD1 and PAD2, and again, the pads PAD1, It is input to the internal input buffers BUF1 and BUF2 through the electrostatic discharge protection units ESD1 and ESD2 connected to the PAD2 to discharge electrostatic pulses, respectively.
이때, 상기 정전방전 보호부(ESD1)는 도2의 회로도에 도시한 바와같이 상기 패드(PAD1)와 내부 입력버퍼(BUF1) 사이에 접속된 저항(R1)과; 상기 패드(PAD1)의 출력단과 저항(R1) 사이에 컬렉터가 접속되고, 에미터가 접지(VSS)된 엔피엔 바이폴라 트랜지스터(Q1)와; 상기 패드(PAD1)의 출력단과 저항(R1) 사이에 베이스와 에미터가 공통 접속되고, 상기 엔피엔 바이폴라 트랜지스터(Q1)의 베이스에 컬렉터가 접속된 피엔피 바이폴라 트랜지스터(Q2)와; 상기 엔피엔 바이폴라 트랜지스터(Q1)의 에미터에 애노드(anode)가 접속되고, 그의 컬렉터에 캐소드(cathode)가 접속된 다이오드(D1)와; 상기 저항(R1)과 내부 입력버퍼(BUF1) 사이에 드레인이 접속되고, 게이트와 소스가 공통 접지(VSS)된 엔모스 트랜지스터(Q3)로 이루어진다.At this time, the electrostatic discharge protection unit ESD1 includes a resistor R1 connected between the pad PAD1 and the internal input buffer BUF1 as shown in the circuit diagram of FIG. An enphi bipolar transistor Q1 having a collector connected between the output terminal of the pad PAD1 and a resistor R1 and having an emitter grounded VSS; A PNP bipolar transistor (Q2) having a base and an emitter connected in common between an output terminal of the pad PAD1 and a resistor (R1), and a collector connected to the base of the ENP bipolar transistor (Q1); A diode (D1) having an anode connected to the emitter of the n-Pen bipolar transistor (Q1) and a cathode connected to the collector thereof; A drain is connected between the resistor R1 and the internal input buffer BUF1, and a gate and a source are formed of an NMOS transistor Q3 having a common ground VSS.
한편, 도3은 상기한 바와같은 정전방전 보호부(ESD1)가 구현된 실리콘 웨이퍼 상의 단면도로서, 피형 기판(1) 상의 일부에 엔형 웰(2)을 형성한 다음 고농도 피형 및 엔형 불순물이온을 순차적으로 주입하여 피형 및 엔형 고농도영역(p+,n+)을 형성하고, 게이트전극(3)을 형성하여 각각의 소자들을 형성한 다음 패드(PAD1)와 접지(VSS)에 접속되는 배선을 형성하여 구현한다.3 is a cross-sectional view of a silicon wafer on which the electrostatic discharge protection part ESD1 is implemented as described above, in which a N type well 2 is formed on a part of the substrate 1, and then a high concentration of an Y and impurity ions is sequentially formed. Implanted to form the doped and en-type high concentration regions (p + , n + ), the gate electrodes 3 are formed to form respective elements, and then the wiring connected to the pads PAD1 and ground VSS is formed. Implement
상기한 바와같은 정전방전 보호부(ESD1)는 상기 패드(PAD1)를 통해 입력되는 전기신호가 정상적인 신호에 비해 훨씬 높거나 낮을 경우에 실리콘 제어 정류기(silicon controlled rectifier : SCR)로 동작하는 엔피엔 및 피엔피 트랜지스터(Q1,Q2) 그리고 다이오드(D1), 저항(R1) 및 클램핑(clamping) 동작을 하는 엔모스 트랜지스터(Q3)를 통해 접지(VSS)로 방전시킨다.As described above, the electrostatic discharge protection unit ESD1 operates as a silicon controlled rectifier (SCR) when an electrical signal input through the pad PAD1 is much higher or lower than a normal signal. Discharge to ground VSS through PN transistors Q1 and Q2 and NMOS transistor Q3 which performs diode D1, resistor R1 and clamping operation.
따라서, 고압 또는 저압의 정전펄스가 내부 입력버퍼(BUF1)에 인가되기 전에 정전방전 보호부(ESD1)를 통해 방전되어 내부회로를 보호하게 된다.Therefore, before the high or low voltage electrostatic pulse is applied to the internal input buffer BUF1, the electrostatic discharge protection unit ESD1 is discharged to protect the internal circuit.
그러나, 상기한 바와같은 종래의 정전방전 보호회로는 패드에 고압 또는 저압의 정전펄스가 인가되면 해당 패드에 접속된 정전방전 보호부가 개별적으로 정전펄스를 방전시킴에 따라 다수의 정전방전 보호부를 효과적으로 활용하지 못하여 방전이 취약하며, 기대치 이상의 정전펄스가 인가되는 경우에 방전능력의 한계로 인해 내부회로가 파괴되는 문제점이 있었다.However, in the conventional electrostatic discharge protection circuit as described above, when a high or low voltage electrostatic pulse is applied to the pad, the electrostatic discharge protection unit connected to the pad discharges the electrostatic pulse individually, thereby effectively utilizing a plurality of electrostatic discharge protection units. There is a problem in that the discharge is vulnerable and the internal circuit is destroyed due to the limitation of the discharge capacity when an electrostatic pulse exceeding the expected value is applied.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 임의의 패드에 인가되는 고압 또는 저압의 정전펄스에 대해 인접하는 패드로 연결경로를 형성하도록 하여 정전펄스의 방전을 분산시킬 수 있는 정전방전 보호회로를 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to form a connection path with adjacent pads for a high or low pressure electrostatic pulse applied to any pad. It is to provide an electrostatic discharge protection circuit that can disperse the discharge.
도1은 종래 정전방전 보호회로의 레이아웃도.1 is a layout diagram of a conventional electrostatic discharge protection circuit.
도2는 도1에 있어서, 정전방전 보호부의 회로도.2 is a circuit diagram of an electrostatic discharge protection unit in FIG. 1;
도3은 도2에 있어서, 정전방전 보호부가 구현된 실리콘 웨이퍼 상의 단면도.FIG. 3 is a cross-sectional view of the silicon wafer in which the electrostatic discharge protection unit is implemented in FIG. 2; FIG.
도4는 본 발명의 제1실시예를 보인 회로구성도.4 is a circuit diagram showing a first embodiment of the present invention.
도5는 도4에 있어서, 방전경로 형성부가 구현된 실리콘 웨이퍼 상의 단면도.FIG. 5 is a sectional view of a silicon wafer in which the discharge path forming portion is implemented in FIG. 4; FIG.
도6은 본 발명의 제2실시예를 보인 회로구성도.6 is a circuit diagram showing a second embodiment of the present invention.
도7은 도6에 있어서, 방전경로 형성부가 구현된 실리콘 웨이퍼 상의 단면도.FIG. 7 is a cross-sectional view of a silicon wafer in which the discharge path forming portion is implemented in FIG. 6; FIG.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
PAD11,PAD12:패드 ESD11,ESD12:정전방전 보호부PAD11, PAD12: Pad ESD11, ESD12: Electrostatic Discharge Protection
BUF11,BUF12:내부 입력버퍼 11:방전경로 형성부BUF11, BUF12: Internal input buffer 11: Discharge path forming part
Q11,Q12:엔모스트랜지스터Q11, Q12: NMOS transistor
상기한 바와같은 본 발명의 목적을 달성하기 위한 정전방전 보호회로는 패키지 외부의 핀을 통해 전기신호를 인가받는 다수의 패드와; 상기 패드에 각각 접속되어 인가된 전기신호가 정전펄스일 경우에 이를 방전하는 정전방전 보호부와; 상기 정전방전 보호부에 각각 접속되어 정전펄스가 아닐 경우에 정전방전 보호부로부터 전기신호를 입력받는 내부 입력버퍼와; 상기 임의의 패드에 정전펄스가 인가되면, 다수의 패드 및 그에 각각 접속된 정전방전 보호부로 방전경로가 형성되도록 인접하는 패드 사이에 각각 접속되는 방전경로 형성부를 구비하여 구성되는 것을 특징으로 한다.Electrostatic discharge protection circuit for achieving the object of the present invention as described above comprises a plurality of pads for receiving an electrical signal through a pin outside the package; An electrostatic discharge protection unit for discharging electric signals connected to the pads when the applied electric signals are electrostatic pulses; An internal input buffer connected to the electrostatic discharge protection unit and receiving an electric signal from the electrostatic discharge protection unit when the electrostatic discharge protection unit is not an electrostatic pulse; When the electrostatic pulse is applied to any of the pads, it is characterized in that it comprises a discharge path forming portion connected between the pads adjacent to each other so that the discharge path is formed to a plurality of pads and the electrostatic discharge protection portion respectively connected thereto.
상기한 바와같은 본 발명에 의한 정전방전 보호회로를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings, the electrostatic discharge protection circuit according to the present invention as described above.
먼저, 도4는 본 발명의 제1실시예를 보인 회로구성도로서, 이에 도시한 바와같이 패키지 외부의 핀(미도시)을 통해 입력되는 전기신호는 패드(PAD11,PAD12)에 인가되고, 다시 정전기를 방전하는 정전방전 보호부(ESD11,ESD12)를 통해 내부 입력버퍼(BUF11,BUF12)로 입력되며, 이때 점선 블록으로 표시된 방전경로 형성부(11)는 상기 패드(PAD11)에 게이트 및 드레인이 공통 접속된 엔모스 트랜지스터(Q11)의 소스를 상기 패드(PAD12)에 게이트 및 소스가 공통 접속된 엔모스 트랜지스터(Q12)의 드레인과 접속되도록 구성되며, 상기 정전방전 보호부(ESD11,ESD12)는 종래와 동일하게 구성된다.First, FIG. 4 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 4, an electrical signal input through a pin (not shown) outside the package is applied to the pads PAD11 and PAD12. The discharge path forming unit 11, which is indicated by a dotted line block, has a gate and a drain on the pad PAD11 through an electrostatic discharge protection unit ESD11 and ESD12 for discharging static electricity. The source of the commonly connected NMOS transistor Q11 is connected to a drain of the NMOS transistor Q12 having a gate and a source commonly connected to the pad PAD12, and the electrostatic discharge protection units ESD11 and ESD12 The configuration is the same as in the prior art.
그리고, 도5는 상기한 바와같은 방전경로 형성부(11)가 구현된 실리콘 웨이퍼 상의 단면도로서, 이에 도시한 바와같이 정전방전 보호부(ESD11,ESD12)가 종래와 동일하게 형성될 때, 피형 기판(1) 상의 일부에 고농도 엔형 불순물이온을 순차적으로 주입하여 엔형 고농도영역(n+)을 형성하고, 게이트전극(3)을 형성하여 소자들을 형성한 다음 패드(PAD11,PAD12)와 각각 접속되는 배선을 형성하여 구현한다.FIG. 5 is a cross-sectional view of a silicon wafer on which the discharge path forming unit 11 as described above is implemented. As shown in FIG. 5, when the electrostatic discharge protection units ESD11 and ESD12 are formed in the same manner as in the related art, A high concentration en-type impurity ion is sequentially implanted into a portion of the phase (1) to form a high-enzyme-type high concentration region (n + ), and a gate electrode 3 is formed to form elements, and then connected to pads PAD11 and PAD12, respectively. It is implemented by forming
이때, 상기 방전경로 형성부(11)에 구현된 엔모스 트랜지스터(Q11,Q12)는 게이트에 고전위의 전압이 인가될때만 정상적으로 동작하는 클램프(clamp) 트랜지스터로서, 정상적인 동작에서는 전류경로가 형성되지 않기 때문에 패드(PAD11,PAD12)간에 서로 영향을 주지 않지만, 일예로 일측 패드(PAD11)에 저전위가 인가되고, 타측 패드(PAD12)에 정상적인 입력전압보다 크거나 작은 전압(즉, 정전펄스)이 인가되면 클램프 트랜지스터의 항복(breakdown)현상에 의해 많은 양의 전류가 흐르게 되므로, 패드(PAD11,PAD12) 간에 전류경로가 형성되어 패드(PAD11,PAD12)에 각각 접속된 정전방전 보호부(ESD11,ESD12)를 통해 정전펄스가 방전된다.At this time, the NMOS transistors Q11 and Q12 implemented in the discharge path forming unit 11 are clamp transistors that operate normally only when a high potential voltage is applied to a gate, and a current path is not formed in normal operation. Since the pads PAD11 and PAD12 do not affect each other, for example, a low potential is applied to one pad PAD11, and a voltage greater than or less than a normal input voltage (ie, an electrostatic pulse) is applied to the other pad PAD12. When applied, a large amount of current flows due to breakdown of the clamp transistor, so that a current path is formed between the pads PAD11 and PAD12, and the electrostatic discharge protection parts ESD11 and ESD12 connected to the pads PAD11 and PAD12, respectively. Electrostatic pulse is discharged through).
한편, 도6은 상기 방전경로 형성부(11)의 제2 실시예를 보인 회로구성도로서, 이에 도시한 바와같이 상기 패드(PAD11,PAD12)에 애노드(anode)가 각각 접속되고, 캐소드(cathode)가 서로 맞물리게 접속되는 다이오드(D11,D12)로 구성된다.FIG. 6 is a circuit diagram showing the second embodiment of the discharge path forming section 11, and as shown in FIG. 6, an anode is connected to the pads PAD11 and PAD12, respectively, and a cathode is shown. ) Is composed of diodes D11 and D12 connected in engagement with each other.
그리고, 도7은 상기한 바와같은 본 발명의 제2 실시예에 따른 방전경로 형성부(11)가 구현된 실리콘 웨이퍼 상의 단면도로서, 이에 도시한 바와같이 정전방전 보호부(ESD11,ESD12)가 종래와 동일하게 형성될 때, 피형 기판(1) 상의 일부에 엔형 웰(2)을 형성한 다음 엔형 웰(2) 상의 일부에 고농도 피형 및 엔형 불순물이온을 순차적으로 주입하여 피형 및 엔형 고농도영역(p+,n+)을 형성함으로써, 소자들을 형성한 다음 패드(PAD11,PAD12)와 각각 접속되는 배선을 형성하여 구현한다.FIG. 7 is a cross-sectional view of a silicon wafer on which the discharge path forming unit 11 according to the second embodiment of the present invention is implemented. As shown in FIG. 7, the electrostatic discharge protection units ESD11 and ESD12 are conventionally used. When formed in the same manner as in, the en-type well 2 is formed in a portion on the substrate 1, and then a high concentration of the encapsulated and en-type impurity ions are sequentially injected into a portion of the en-type well 2. By forming + , n + , the devices are formed and then wires connected to the pads PAD11 and PAD12 are formed.
상기한 바와같은 본 발명의 제2 실시예에 따른 방전경로 형성부(11)의 다이오드(D11,D12)는 상기 본 발명의 제1 실시예에 따른 클램프 트랜지스터와 마찬가지로 패드(PAD11,PAD12)에 정상적인 전압이 인가될 경우에는 전류경로가 형성되지 않지만, 어느 하나의 패드(PAD11,PAD12)에 크거나 낮은 전압이 인가되면, 상기 다이오드(D11,D12)의 항복현상에 의해 많은 양의 전류가 흐르게 되므로, 인접하는 패드(PAD11,PAD12) 간에 전류경로가 형성되어 패드(PAD11,PAD12)에 각각 접속된 정전방전 보호부(ESD11,ESD12)를 통해 정전펄스가 방전된다.As described above, the diodes D11 and D12 of the discharge path forming unit 11 according to the second embodiment of the present invention are similar to the pads PAD11 and PAD12 similar to the clamp transistors according to the first embodiment of the present invention. When a voltage is applied, a current path is not formed. However, when a large or low voltage is applied to one of the pads PAD11 and PAD12, a large amount of current flows due to the breakdown of the diodes D11 and D12. A current path is formed between adjacent pads PAD11 and PAD12, and the electrostatic pulses are discharged through the electrostatic discharge protection parts ESD11 and ESD12 respectively connected to the pads PAD11 and PAD12.
상기한 바와같은 본 발명에 의한 정전방전 보호회로는 임의의 패드에 인가되는 고압 또는 저압의 정전펄스에 대해 인접하는 패드로 연결경로가 형성되도록 하여 정전펄스의 방전을 분산시킴에 따라 방전효율을 높이고, 보다 높은 전압의 정전펄스에 대해서 내부회로를 보호할 수 있게 되어 정전방전 보호회로의 신뢰성을 향상시킬 수 있는 효과가 있다.In the electrostatic discharge protection circuit according to the present invention as described above, the connection paths are formed to pads adjacent to the high or low voltage electrostatic pulses applied to an arbitrary pad, thereby increasing the discharge efficiency by dispersing the discharge of the electrostatic pulses. Therefore, since the internal circuit can be protected against the electrostatic pulse of higher voltage, the reliability of the electrostatic discharge protection circuit can be improved.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990029976A KR100324322B1 (en) | 1999-07-23 | 1999-07-23 | Circuit for protecting electrostatic discharge |
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| KR1019990029976A KR100324322B1 (en) | 1999-07-23 | 1999-07-23 | Circuit for protecting electrostatic discharge |
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| KR100324322B1 true KR100324322B1 (en) | 2002-02-16 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940004802A (en) * | 1992-08-12 | 1994-03-16 | 존 엠. 클락 3세 | Electrostatic Discharge (ESD) Protection with NPN Bipolar Transistors |
| JPH06151717A (en) * | 1992-11-04 | 1994-05-31 | Rohm Co Ltd | Ic with built-in protective circuit and ic for driving display device |
| JPH0964281A (en) * | 1995-08-29 | 1997-03-07 | Sanyo Electric Co Ltd | Circuit for protecting integrated circuit from static electricity |
| JPH1050937A (en) * | 1996-07-29 | 1998-02-20 | Nec Corp | Electrostatic protective circuit of integrated circuit |
| KR19980059897A (en) * | 1996-12-31 | 1998-10-07 | 문정환 | Electrostatic (EDS) Protection Circuit |
-
1999
- 1999-07-23 KR KR1019990029976A patent/KR100324322B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940004802A (en) * | 1992-08-12 | 1994-03-16 | 존 엠. 클락 3세 | Electrostatic Discharge (ESD) Protection with NPN Bipolar Transistors |
| JPH06151717A (en) * | 1992-11-04 | 1994-05-31 | Rohm Co Ltd | Ic with built-in protective circuit and ic for driving display device |
| JPH0964281A (en) * | 1995-08-29 | 1997-03-07 | Sanyo Electric Co Ltd | Circuit for protecting integrated circuit from static electricity |
| JPH1050937A (en) * | 1996-07-29 | 1998-02-20 | Nec Corp | Electrostatic protective circuit of integrated circuit |
| KR19980059897A (en) * | 1996-12-31 | 1998-10-07 | 문정환 | Electrostatic (EDS) Protection Circuit |
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