KR100298427B1 - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve a step coverage in a dry etch process of an oxide layer by using etch selectivity of a photo-resist layer and an oxide layer. CONSTITUTION: A polysilicon layer as a conductive layer is formed on a semiconductor substrate. An oxide layer(4) is formed thereon. A source region and a drain region are formed by implanting ions into a whole surface of the semiconductor substrate. An interlayer dielectric(6) is deposited on the whole surface of the above structure. A photo-resist layer is deposited on the interlayer dielectric(6). A contact hole is formed by etching the photo-resist layer and the interlayer dielectric(6). A metal layer(8) is deposited on the whole surface of the semiconductor substrate. A metal line is formed by patterning the metal layer(8).

Description

Manufacturing Method of Semiconductor Device

1 is a process flowchart showing a method for forming a contact hole for connection between conductive layers in a conventional semiconductor device.

2 is a process flow chart showing a method for forming a contact hole for connection between conductive layers in a semiconductor device of the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 gate oxide film

3: gate electrode 4: oxide film

5 sidewall 6 interlayer insulating film

7: photosensitive film 8: metal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of improving step coverage during dry etching of an oxide film by using etching selectivity of a photosensitive film and an oxide film.

A method of forming a contact hole for connection between conductive layers in a conventional semiconductor device will be described with reference to FIG.

As shown in FIG. 1A, a gate oxide film 2, a gate electrode 3, and an oxide film 4 are sequentially formed on the semiconductor substrate 1, and then patterned into a gate pattern through a photolithography process.

Subsequently, as shown in FIG. 1 (b), ions are implanted into the entire surface of the substrate to form a source region S and a drain region D. Then, an oxide film is formed on the entire surface and etched back to form sidewalls 5. Next, ion implantation is performed to form a LDD (Lightly Doped Drain) structure.

Next, as shown in Fig. 1 (c), a BPSG (Borophospho silicate glass) is deposited as the interlayer insulating film 6 on the entire surface of the substrate, and a reflow process is performed.

Subsequently, after the photosensitive film 7 is coated on the interlayer insulating film 6 as shown in FIG. 1 (d), the photoresist film 7 is patterned, and the wet etching of the interlayer insulating film 6 is performed, followed by dry etching. At this time, the dry etching conditions are gas; CF ₄ (60 sccm) + CHF ₃ ( ₄₀ sccm), power; About 650 watts, pressure; 1.5-2.0Torr, clearance: about 1cm

Next, as shown in FIG. 1 (e), the photoresist layer is removed, and the oxide layer 4 on the gate electrode 3 is dry-etched to form a contact hole. Process conditions at this time are gas; 0 ₂ (10-100 sccm), power; 600-800 Watts, Pressure; 1Torr or less

An annealing process is then performed as shown in FIG. 1 (f) to improve planarization and contact hole step coverage of the interlayer insulating film 6. In this case, the reflow process may be performed in the process of FIG. 1 (d), and the annealing process may be further performed in the process of FIG. 1 (e) to improve planarization and contact hole step coverage.

Next, aluminum is deposited and patterned as the metal 8 as shown in FIG. 1 (g).

In the prior art, there is a problem in that complex processes such as a reflow process annealing process and a wet etching process are required after the formation of the BPSG, which is an interlayer insulating film, to improve step coverage during metal deposition after contact hole formation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method capable of improving the step coverage of a contact hole formed in an interlayer insulating film by a simple process.

The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a semiconductor substrate first conductive layer, the step of forming an interlayer insulating film on the entire surface of the substrate, the step of applying a thin photosensitive film on the interlayer insulating film, the Patterning a photoresist film into a contact hole pattern, and dry etching the interlayer insulating film by a predetermined thickness using the photoresist pattern as a mask, and etching the photoresist film and the interlayer insulating film under an etching condition in which an etch selectivity between the photoresist film and the interlayer insulating film is about 1: 1. Forming a contact hole exposing the first conductive layer by simultaneously etching the same, depositing and patterning a metal on the interlayer insulating layer to form a second conductive layer connected to the first conductive layer through the contact hole. Including the process.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

First, as shown in FIG. 2 (a), a polysilicon layer is formed on the semiconductor substrate 1 as the conductive layer for forming the gate oxide film 2 and the gate electrode 3, and an oxide film 4 is formed as the gate insulating film. The pattern is formed into a gate pattern through a photolithography process.

Subsequently, as shown in FIG. 2 (b), ions are implanted into the entire surface of the substrate to form the source region 5 and the drain region D. Then, an oxide film is formed as an insulating film on the entire surface and etched back to the sidewall 5 And then ion implantation to form a LDD (Lightly Doped Drain) structure.

Next, for example, BPSG (Borophospho silicate glass) is deposited as the interlayer insulating film 6 on the entire surface of the substrate as shown in FIG. 2 (c), and a reflow process is performed. At this time, the thickness of the BPSG film is slightly thicker than that of the prior art, that is, about 3000-5000 mm thicker than the conventional one.

Subsequently, as shown in FIG. 2 (d), the photoresist film 7 is applied on the interlayer insulating film 6 to be thinner than that of the prior art, that is, at a thickness of 1/2 of the prior art, and then patterned into a contact hole pattern. 6) Dry etch a certain thickness. At this time, the dry etching conditions are gas; CF ₄ (60 sccm) + CHF ₃ ( ₄₀ sccm), power; 650 watts, pressure; 1.5-2.0 Torr, gap; about 1 cm.

Next, as shown in FIG. 2 (e), the photoresist and the interlayer dielectric BPSG are etched under an etching process condition in which the selectivity of the photoresist film and the oxide film is about 1: 1, using only O ₂ gas; , Pressure; 1.5-2.0 Torr, clearance; remove the photosensitive film to the A portion of the process conditions of about 1cm, and then again using CF ₄ (60sccm) + CHF ₃ (40seem) + O ₂ (10-20seem) gas The process conditions proceed in the same manner as described above to etch the portion B, and then continue the etching process to etch to the portion C as shown in the second (f). At this time, the interlayer insulating layer 6 and the spreading degree are less than 1: 1 of the wet etching, but the down-etching time is long due to the process characteristics, so the step coverage is improved beyond the wet etching effect. Subsequently, an etching process is performed under the following conditions: gas; O ₂ (10-100 sccm), power; 600-800 watts, pressure; 1 Torr or less to form contact holes.

Subsequently, as shown in FIG. 2 (g), the metal is deposited on the entire surface of the substrate, for example, aluminum is deposited, and then patterned into a predetermined pattern through a photolithography process to form a metal wiring.

As described above, according to the present invention, the photoresist film and the interlayer insulating film are simultaneously etched under an etching condition with an etching selectivity of 1: 1, thereby eliminating the need for a separate photoresist film removal process and a wet etching process, and shortening the process time. In addition, since the photosensitive film is applied thinner than before, cost reduction and patterning ability are improved, and reflow and annealing of the interlayer insulating film are omitted, thereby simplifying the process.

Claims (3)

Forming a first conductive layer on a semiconductor substrate; forming an interlayer insulating film over the entire surface of the substrate; applying a thin photosensitive film on the interlayer insulating film; patterning the photosensitive film into a contact hole pattern; and forming the photosensitive film pattern. Dry etching the interlayer insulating layer using a mask, and simultaneously etching the photosensitive layer and the interlayer insulating layer under an etching condition in which the etch selectivity of the photosensitive layer and the interlayer insulating layer is about 1: 1, thereby exposing the first conductive layer. Forming a second conductive layer connected to the first conductive layer through the contact hole by depositing and patterning a metal on the interlayer insulating layer. . The method of manufacturing a semiconductor device according to claim 1, wherein said interlayer insulating film is formed of BPSG. The etching condition of claim 1, wherein the etching selectivity of the photoresist and the interlayer insulating layer is about 1: 1; gas; CF ₄ (60 sccm) + CHF ₃ (40 sccm) + O ₂ (10-20 sccm), power; Watt, pressure; 1.5-2.0 Torr.