KR100282217B1 - Manufacturing Method of Semiconductor Memory Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device that prevents deterioration of capacitor characteristics, wherein a capacitor is formed on a first interlayer insulating film on an isolation layer. A second interlayer insulating film is formed on the first interlayer insulating film including the capacitor. The first metal contact is formed to penetrate the second interlayer insulating film and the first interlayer insulating film and to be electrically connected to the capacitor lower electrode and the semiconductor substrate at the same time. A third interlayer insulating film is formed on the second interlayer insulating film including the first metal contact. A second metal contact is formed so as to be electrically connected to the capacitor upper electrode through the third interlayer insulating film and the second interlayer insulating film. The passivation film is deposited on the third interlayer insulating film including the second metal contact at a temperature lower than a temperature at which the first metal contact and the capacitor lower electrode and the second metal contact and the capacitor upper electrode react with each other. According to the method of manufacturing a semiconductor device, by depositing the passivation film at a low temperature of 250 ° C. or less, hydrogen penetration and stress caused by the passivation film deposition can be minimized, and the metal contacts and the capacitor electrodes can react with each other without the diffusion barrier. This can prevent the deterioration of the characteristics of the capacitor.

Description

A METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of depositing a passivation layer of a ferroelectric random access memory (FRAM) that prevents deterioration of characteristics of a ferroelectric capacitor.

Ferroelectric memory devices are being actively researched for use as next-generation memories due to advantages such as nonvolatile, random access, and low voltage operation.

Passivation and package processes are essential for the practical use of ferroelectric memory devices, but the characteristics of capacitors are deteriorated due to hydrogen (H) infiltration and stress generated in these processes, making it difficult to realize products.

1 is a cross-sectional view illustrating a structure of a conventional semiconductor memory device.

Referring to FIG. 1, in the ferroelectric memory device, an isolation layer 4 is formed on a semiconductor substrate 2 by defining an active region and an inactive region. The gate electrode 6 is formed on the semiconductor substrate 2 in the active region. A first interlayer dielectric 8 is formed on the semiconductor substrate 2 including the device isolation film 4 and the gate electrode 6.

A capacitor 14 including a capacitor lower electrode 10, a ferroelectric layer 11, and a capacitor upper electrode 12 is formed on the first interlayer insulating layer 8. A capping layer 9 is formed of TiO ₂ or the like so as to surround the capacitor 14 in order to prevent the ferroelectric layer 11 and other materials from reacting. A second interlayer insulating film 16 is formed on the first interlayer insulating film 8 including the capping layer 9. The second interlayer insulating film 16, the first interlayer insulating film 8, and the capping layer 9b are electrically connected to the semiconductor substrate 2 and simultaneously with the capacitor lower electrode 10 and the semiconductor substrate 2. Each of the first metal contacts 18a and 18b is formed to be electrically connected.

A third interlayer insulating film 20 is formed on the second interlayer insulating film 16 including the first metal contacts 18a and 18b. A second metal contact 22 is formed through the third interlayer insulating film 20, the second interlayer insulating film 16, and the capping layer 9b to be electrically connected to the capacitor upper electrode 12. The passivation film 24 is formed on the third interlayer insulating film 20 including the second metal contact 22.

In the conventional passivation film 24, an oxide film formed by an ECR (Electro Cyclotron Resonance) method or a PE-TEOS (Plasma Enhanced CVD TetraEthyl OrthoSilicate) oxide film is used.

The ECR oxide film and the PE-TEOS film require a deposition temperature of 300 ° C-400 ° C.

However, when the process of 200 ° C. or higher is performed after the formation of the second metal contact 22, a problem occurs in that the characteristics of the ferroelectric are deteriorated due to the mutual reaction of platinum, which is a capacitor electrode material, and aluminum, which is a metal contact material.

2A to 2D are SEM (Scanniong Electron Microscope) photographs showing the reaction between the capacitor upper electrode (Pt) and the contact electrode (Al) according to the change in the annealing temperature.

Referring to FIG. 2A, when the annealing process (passivation layer deposition process) is not performed after the formation of the second contact electrode 22 electrically connected to the capacitor upper electrode 12, the capacitor upper electrode 12 and the second contact are not performed. No reactant is formed between the electrodes 22.

However, as shown in FIG. 2B, when the annealing temperature is 200 ° C., a Pt-Al reactant is formed in a thin thickness between the capacitor upper electrode 12 and the second contact electrode 22, and the annealing temperature is 300 ° C. FIG. As shown in Fig. 2c and 400 ° C (Fig. 2d), the Pt-Al reactant is further increased.

3 is a graph showing a hysteresis loop of a ferroelectric capacitor according to a change in annealing temperature.

Referring to FIG. 3, the residual polarization of the ferroelectric capacitor, that is, the sensing charge, is gradually increased as the annealing temperature (passivation film deposition temperature) increases from 200 ° C, 300 ° C, and 400 ° C to room temperature (25 ° C), respectively. It can be seen that the decrease.

In order to solve the above problems, a diffusion barrier layer such as TiN is formed between the capacitor electrodes and the contact electrodes to prevent a reaction between the capacitor electrodes and the contact electrodes. However, since the passivation film deposition temperature is still high, a problem arises in that the sensing charge of the ferroelectric capacitor is greatly reduced due to labor penetration and stress.

The present invention has been proposed to solve the above-mentioned problems, and it is possible to prevent the deterioration of the characteristics of the capacitor due to the deposition temperature during the passivation film deposition, and even without forming a diffusion barrier between the capacitor electrodes and the metal contacts. It is an object of the present invention to provide a method of manufacturing a semiconductor memory device capable of preventing a reaction between capacitor electrodes and metal contacts.

1 is a cross-sectional view showing the structure of a conventional semiconductor memory device.

2a to 2d are SEM images showing the reaction between the capacitor upper electrode (Pt) and the contact electrode (Al) according to the change in the annealing temperature.

3 is a graph showing a hysteresis loop of a ferroelectric capacitor according to a change in annealing temperature.

4A through 4D are flowcharts sequentially showing processes of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

5 is a SEM photograph after deposition of a passivation film of a semiconductor memory device according to an embodiment of the present invention.

Figure 6 is a graph showing the sensing charge before and after passivation film deposition according to the conventional and embodiments of the present invention.

<Explanation of symbols for main parts of drawing>

2, 100: semiconductor substrate 4, 102: device isolation film

6, 104: gate electrode 8, 106: first interlayer insulating film

9, 107: capping layer 10, 108: capacitor lower electrode

11, 109: ferroelectric film 12, 110: capacitor upper electrode

14, 112 capacitor 16, 114 second interlayer insulating film

18a, 18b, 116a, 116b: first metal contact

20, 118: third interlayer insulating film 22, 120: second metal contact

24, 122: passivation film

[Configuration]

According to the present invention for achieving the above object, a manufacturing method of a semiconductor memory device, comprising: forming a first insulating layer on a semiconductor substrate having a device isolation film; Forming a capacitor by sequentially forming a capacitor lower electrode, a capacitor dielectric layer, and a capacitor upper electrode on the first insulating layer above the device isolation layer; Forming a second insulating layer on the first insulating layer including the capacitor; Forming a first metal contact through the second insulating layer and the first insulating layer to be electrically connected to the capacitor lower electrode and the semiconductor substrate at the same time; Forming a third insulating layer on the second insulating layer including the first metal contact; Forming a second metal contact through the third insulating layer and the second insulating layer to be electrically connected to the upper electrode of the capacitor; And forming a passivation film on the third insulating layer including the second metal contact, wherein a temperature at which the first metal contact and the capacitor lower electrode react with each other and a temperature at which the second metal contact and the capacitor upper electrode react with each other. Form at low temperatures.

[Action]

Referring to FIG. 6, in the novel semiconductor memory device manufacturing method according to an embodiment of the present invention, a passivation film is deposited on the entire surface of a semiconductor substrate after a metal contact process electrically connected to capacitor electrodes. At this time, by depositing the passivation film at a low temperature of 250 ℃ or less, it is possible to minimize the hydrogen penetration and stress caused by the passivation film deposition, and to prevent the metal contacts and the capacitor electrodes react with each other without a diffusion barrier, thereby The deterioration of the characteristics can be prevented.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 4 to 6.

4A through 4D are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4A, in the method of manufacturing a semiconductor memory device according to an embodiment of the present invention, an isolation layer 102 is formed on a semiconductor substrate 100 by defining an active region and an inactive region. A transistor including a gate oxide film (not shown) and a gate electrode 104 and a source / drain region (not shown) are formed in the semiconductor substrate 100 in the active region.

Including the transistor, a first interlayer insulating film 106 having a flat upper surface is formed on the entire surface of the semiconductor substrate 100.

In FIG. 4B, a ferroelectric capacitor 112 including a capacitor lower electrode 108, a ferroelectric layer 109, and a capacitor upper electrode 110 is formed on the first interlayer insulating layer 106. The capacitor lower electrode 108 and the upper electrode 110 are generally formed of platinum (Pt), and here, are formed to a thickness of about 2300 kPa and about 2300 kPa, respectively. The ferroelectric film 109 is formed of, for example, Pb (Zr, Ti) O [PZT] or Pb (La) (Zr, Ti) O [PLZT] or the like, and is formed of PZT having a thickness of about 2500 kPa. A capping layer 107b is formed of TiO ₂ to cover the ferroelectric capacitor 112. This capping layer 107b is formed to prevent the ferroelectric film 109 from reacting with other materials in subsequent processes. A capping layer 107a may be further formed between the first interlayer insulating layer 106 and the capacitor lower electrode 108.

A second interlayer insulating film 114 is formed on the first interlayer insulating film 106 including the capping layer 107b. The second interlayer insulating film 114, the first interlayer insulating film 106, and the capping layer 107b are electrically connected to the source / drain regions and electrically connected to the source / drain regions and the capacitor lower electrode 108 at the same time. Each of the first metal contacts 116a and 116b is formed to be connected.

Referring to FIG. 4C, a third interlayer dielectric layer 118 is formed on the second interlayer dielectric layer 114 including the first metal contacts 116a and 116b, and the third interlayer dielectric layer 118 and the third interlayer dielectric layer 118 are formed. The second metal contact 120 is formed to penetrate the second interlayer insulating film 114 and the capping layer 107b and to be electrically connected to the capacitor upper electrode 110. The first and second metal contacts 116a, 116b, and 120 are formed of aluminum (Al) by, for example, a sputtering deposition method.

Finally, as shown in FIG. 4D, the passivation film 122 is deposited on the third interlayer insulating film 118 including the second metal contact 120 to a thickness of about 6000 kPa.

For example, the passivation layer 122 is deposited at a temperature lower than the temperature at which the metal contact material Al and the capacitor electrode material Pt react as an oxide film, that is, lower than 250 ° C. Preferably it is deposited at 200 ° C or less.

The passivation film 122 is formed of at least one of a P-silane base (SiH ₄ based PECVD) oxide film, a PE-TEOS oxide film, PSG, BPSG, and USG. On the other hand, even if the ECR oxide film is formed at 200 ° C. or lower, the step coverage is not very good, and thus it is not suitable as a passivation film.

5 is a SEM photograph after passivation film deposition of a semiconductor memory device according to an embodiment of the present invention, Figure 6 is a graph showing the sensing charge before and after passivation film deposition according to the prior art and the embodiment of the present invention.

Referring to FIG. 5, the PE-TEOS oxide film is deposited as the passivation film 122 at a temperature of 200 ° C. or less, and it can be seen that their reactants are not formed between the capacitor electrode and the contact electrode.

In addition, in FIG. 6, the sensing charge when the conventional ECR oxide film is used as the passivation film is significantly reduced to about 1 μC / cm 2 at 190 ° C. (about 9 μC / cm 2) at 190 ° C. according to an embodiment of the present invention. On the other hand, in the case of the formed P-silane base oxide film and the PE-TEOS oxide film formed at 200 ° C., it can be seen that the sensing charge is maintained as it is (except voltage of 3V). The diffusion barrier layer TiN is formed between the contact electrodes.

As described above, according to the method of forming a capacitor of a semiconductor memory device according to the present invention, even if a diffusion barrier is not formed between the capacitor electrodes and the contact electrodes, the reaction between the capacitor electrodes and the contact electrodes is prevented, and even after the passivation layer is deposited. The characteristics of the ferroelectric capacitor are maintained.

According to the present invention, as the conventional passivation film is deposited at a temperature of 200 ° C. or higher, the sensing charge of the ferroelectric capacitor is reduced due to the stress and hydrogen penetration generated during the deposition of the passivation film, and the characteristics of the capacitors as the capacitor electrodes and the metal contacts react with each other. This deterioration problem is solved.

By depositing the passivation film at a low temperature of 200 ° C. or less, hydrogen penetration and stress due to the passivation film deposition can be minimized, and the metal contacts and the capacitor electrodes can be prevented from interacting with each other without the diffusion barrier, thereby the characteristics of the capacitor. There is an effect that can prevent this deterioration.

Claims (2)

Forming a first insulating layer on the semiconductor substrate having the device isolation film; Forming a capacitor by sequentially forming a capacitor lower electrode, a capacitor dielectric layer, and a capacitor upper electrode on the first insulating layer on the device isolation layer; Forming a second insulating layer on the first insulating layer including the capacitor; Forming a first metal contact through the second insulating layer and the first insulating layer to be electrically connected to the capacitor lower electrode and the semiconductor substrate at the same time; Forming a third insulating layer on the second insulating layer including the first metal contact; Forming a second metal contact through the third insulating layer and the second insulating layer to be electrically connected to the capacitor upper electrode; And forming a passivation film on the third insulating layer by the plasma CVD method at a low temperature of 250 ° C. or lower including the second metal contact. The method of claim 1, wherein the passivation film is formed of at least one of a P-silane base oxide film, a PE-TEOS oxide film, a PSG, a BPSG, and a USG.