KR100280515B1 - Manufacturing method of highly integrated semiconductor device - Google Patents
Manufacturing method of highly integrated semiconductor device Download PDFInfo
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- KR100280515B1 KR100280515B1 KR1019980045910A KR19980045910A KR100280515B1 KR 100280515 B1 KR100280515 B1 KR 100280515B1 KR 1019980045910 A KR1019980045910 A KR 1019980045910A KR 19980045910 A KR19980045910 A KR 19980045910A KR 100280515 B1 KR100280515 B1 KR 100280515B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 239000011800 void material Substances 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- General Chemical & Material Sciences (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 고집적 반도체소자의 제조방법에 관한 것으로, 종래에는 패턴 사이의 이격영역이 미세해짐에 따라 평탄화 및 층간절연을 위한 막이 채워질 때, 보이드가 형성되어 콘택의 접촉불량을 유발하는 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부에 서로 이격되는 패턴을 형성하는 공정과; 상기 패턴이 형성된 반도체기판의 상부전면에 질화막을 증착한 후, 선택적으로 식각하여 패턴의 측면에 측벽을 형성하는 공정과; 상기 측벽이 형성된 반도체기판의 상부전면에 고온저압 산화막을 증착하는 공정과; 상기 고온저압 산화막이 증착된 반도체기판의 상부전면에 감광막을 도포 및 노광한 후, 현상량을 조절하여 패턴간 이격거리에 감광막이 잔류하도록 하는 공정과; 상기 잔류된 감광막을 마스크로 하여 상기 고온저압 산화막을 습식식각하는 공정과; 상기 잔류된 감광막을 제거한 후, 반도체기판의 상부전면에 층간절연막을 형성하는 공정으로 이루어지는 고집적 반도체소자의 제조방법을 제공하여 조밀한 패턴의 이격영역 사이에 종횡비 감소를 통해 평탄화 및 층간절연을 위한 막의 채워지는 특성을 향상시켜 보이드의 형성을 방지함으로써, 콘택의 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention relates to a method for fabricating a highly integrated semiconductor device, and in the related art, when a space for planarization and interlayer insulation is filled as a spaced area between patterns becomes fine, voids are formed to cause contact failure of contacts. Accordingly, the present invention provides a method for forming a pattern spaced apart from each other on top of a semiconductor substrate; Depositing a nitride film on the upper surface of the semiconductor substrate on which the pattern is formed, and then selectively etching to form sidewalls on the side surfaces of the pattern; Depositing a high temperature low pressure oxide film on an upper surface of the semiconductor substrate on which the sidewalls are formed; Coating and exposing the photosensitive film on the upper surface of the semiconductor substrate on which the high temperature and low pressure oxide film is deposited, and controlling the amount of development so that the photosensitive film remains at a distance between patterns; Wet etching the high temperature low pressure oxide film using the remaining photoresist as a mask; After the remaining photoresist film is removed, there is provided a method for manufacturing a highly integrated semiconductor device comprising the step of forming an interlayer insulating film on the upper surface of the semiconductor substrate to reduce the aspect ratio between the spaced areas of the dense pattern to planarization and interlayer insulation By improving the filling property to prevent the formation of voids, there is an effect that can improve the reliability of the contact.
Description
본 발명은 고집적 반도체소자의 제조방법에 관한 것으로, 특히 조밀한 패턴의 이격영역에 층간절연막의 채워지는 특성을 향상시켜 콘택(contact)의 신뢰성을 확보하기에 적당하도록 한 고집적 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a highly integrated semiconductor device, which is suitable to secure contact reliability by improving the filling property of an interlayer insulating film in a spaced region of a dense pattern. It is about.
종래 고집적 반도체소자의 제조방법을 도1a 내지 도1c의 수순단면도, 도2 및 도3의 단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional highly integrated semiconductor device will be described in detail with reference to the cross-sectional views of FIGS. 1A to 1C and the cross-sectional views of FIGS. 2 and 3.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 소정거리 이격되는 게이트(2A,2B)를 형성한다. 이때, 상기 게이트(2A,2B)는 반도체기판(1)의 상부에 게이트산화막, 폴리실리콘, 텅스텐 실리사이드 및 캡 질화막을 순차적으로 증착한 후, 패터닝하여 형성한다.First, as illustrated in FIG. 1A, gates 2A and 2B spaced a predetermined distance from each other are formed on the semiconductor substrate 1. In this case, the gates 2A and 2B are formed by sequentially depositing a gate oxide film, polysilicon, tungsten silicide, and a cap nitride film on the semiconductor substrate 1 and then patterning the gate oxide film, polysilicon, tungsten silicide, and cap nitride film.
그리고, 도1b에 도시한 바와같이 상기 게이트(2A,2B)가 형성된 반도체기판(1)의 상부전면에 질화막(3)을 증착한 후, 선택적으로 식각하여 상기 게이트(2A,2B)의 측면에 측벽을 형성한다. 이때, 게이트(2A,2B)의 측벽은 반도체소자를 엘디디(lightly doped drain : LDD)구조로 형성하여 단채널에 의한 영향(short channel effect)을 최소화한다.1B, a nitride film 3 is deposited on the upper surface of the semiconductor substrate 1 on which the gates 2A and 2B are formed, and then selectively etched to the side surfaces of the gates 2A and 2B. Form sidewalls. At this time, the sidewalls of the gates 2A and 2B form a semiconductor device with a lightly doped drain (LDD) structure to minimize the short channel effect.
그리고, 도1c에 도시한 바와같이 상기 측벽이 형성된 반도체기판(1)의 상부전면에 평탄화 및 층간절연을 위한 비피에스지막(4)을 형성한다.As shown in FIG. 1C, a non-PS film 4 for planarization and interlayer insulation is formed on the upper surface of the semiconductor substrate 1 having the sidewalls formed thereon.
이때, 반도체소자가 고집적화됨에 따라 도2에 도시한 바와같이 게이트(2A,2B) 사이의 이격영역이 점점 줄어들게 되어 비피에스지막(4)이 게이트(2A,2B) 사이의 이격영역에 채워질 때, 보이드(void,10)가 발생하게 된다.At this time, as the semiconductor device is highly integrated, as shown in FIG. 2, the separation area between the gates 2A and 2B gradually decreases, so that when the BPS film 4 is filled in the separation area between the gates 2A and 2B, A void 10 is generated.
상기한 바와같이 보이드(10)가 발생하면, 보이드(10)와 비피에스지막(4) 사이의 계면에 폴리머(polymer)가 형성되고, 이 폴리머는 후속 공정으로 콘택형성을 위해 비피에스지막(4)을 식각할 때 식각을 방해한다.As described above, when the void 10 is generated, a polymer is formed at the interface between the void 10 and the BPS film 4, and the polymer is then subjected to the BPS film 4 for contact formation in a subsequent process. ), It interferes with etching.
따라서, 도3에 도시한 바와같이 게이트(2A,2B) 사이의 이역영역에 채워진 비피에스지막(4)이 완전히 식각되지 않게 되어 콘택의 접촉이 불가능해진다.Therefore, as shown in FIG. 3, the BPS film 4 filled in the region between the gates 2A and 2B is not etched completely, and contact of the contacts is impossible.
상기한 바와같이 종래 고집적 반도체소자의 제조방법은 패턴 사이의 이격영역이 미세해짐에 따라 평탄화 및 층간절연을 위한 막이 채워질 때, 보이드가 형성되어 콘택의 접촉불량을 유발하는 문제점이 있었다.As described above, the conventional method of manufacturing a highly integrated semiconductor device has a problem in that voids are formed when a film for planarization and interlayer insulation is filled as the spaced area between patterns becomes fine, causing contact failure of contacts.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 조밀한 패턴의 이격영역 사이에 평탄화 및 층간절연을 위한 막의 채워지는 특성을 향상시켜 보이드의 형성을 방지할 수 있는 고집적 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to improve the filling property of a film for planarization and interlayer insulation between spaced areas of a dense pattern to prevent the formation of voids. The present invention provides a method for manufacturing a highly integrated semiconductor device.
도1은 종래 고집적 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a highly integrated semiconductor device.
도2는 종래의 기술에 따른 층간절연막의 채워지는 특성을 보인 단면도.Figure 2 is a cross-sectional view showing the filling characteristics of the interlayer insulating film according to the prior art.
도3은 종래의 기술에 따른 콘택의 접촉불량을 보인 단면도.3 is a cross-sectional view showing a poor contact of the contact according to the prior art.
도4는 본 발명의 일 실시예를 보인 수순단면도.Figure 4 is a cross-sectional view showing an embodiment of the present invention.
도5는 본 발명의 일 실시예에 따른 층간절연막의 채워지는 특성을 보인 단면도.Figure 5 is a cross-sectional view showing the filling characteristics of the interlayer insulating film according to an embodiment of the present invention.
도6은 본 발명의 다른 실시예를 보인 단면도.Figure 6 is a cross-sectional view showing another embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12A,12B:게이트11: Semiconductor Board 12A, 12B: Gate
13:질화막 14:고온저압 산화막13: Nitride film 14: High temperature low pressure oxide film
15:감광막 16:비피에스지막15: Photosensitive film 16: BPS film
상기한 바와같은 본 발명의 목적을 달성하기 위한 고집적 반도체소자 제조방법의 바람직한 일 실시예는 반도체기판의 상부에 서로 이격되는 패턴을 형성하는 공정과; 상기 패턴이 형성된 반도체기판의 상부전면에 질화막을 증착한 후, 선택적으로 식각하여 패턴의 측면에 측벽을 형성하는 공정과; 상기 측벽이 형성된 반도체기판의 상부전면에 고온저압 산화막을 증착하는 공정과; 상기 고온저압 산화막이 증착된 반도체기판의 상부전면에 감광막을 도포 및 노광한 후, 현상량을 조절하여 패턴간 이격거리에 감광막이 잔류하도록 하는 공정과; 상기 잔류된 감광막을 마스크로 하여 상기 고온저압 산화막을 습식식각하는 공정과; 상기 잔류된 감광막을 제거한 후, 반도체기판의 상부전면에 층간절연막을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.One preferred embodiment of the method for manufacturing a highly integrated semiconductor device for achieving the object of the present invention as described above comprises the steps of forming a pattern spaced apart from each other on the upper portion of the semiconductor substrate; Depositing a nitride film on the upper surface of the semiconductor substrate on which the pattern is formed, and then selectively etching to form sidewalls on the side surfaces of the pattern; Depositing a high temperature low pressure oxide film on an upper surface of the semiconductor substrate on which the sidewalls are formed; Coating and exposing the photosensitive film on the upper surface of the semiconductor substrate on which the high temperature and low pressure oxide film is deposited, and controlling the amount of development so that the photosensitive film remains at a distance between patterns; Wet etching the high temperature low pressure oxide film using the remaining photoresist as a mask; And removing the remaining photoresist film, and forming an interlayer insulating film on the upper surface of the semiconductor substrate.
상기한 바와같은 본 발명에 의한 고집적 반도체소자 제조방법의 바람직한 일 실시예를 도4a 내지 도4e의 수순단면도 및 도5의 단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method for manufacturing a highly integrated semiconductor device according to the present invention as described above will be described in detail with reference to the cross-sectional view of FIG. 4A through FIG. 4E and the cross-sectional view of FIG. 5.
먼저, 도4a에 도시한 바와같이 반도체기판(11)의 상부에 소정거리 이격되는 게이트(12A,12B)를 형성한다. 이때, 상기 게이트(12A,12B)는 반도체기판(11)의 상부에 게이트산화막, 폴리실리콘, 텅스텐 실리사이드 및 캡 질화막을 순차적으로 증착한 후, 패터닝하여 형성한다.First, as shown in FIG. 4A, gates 12A and 12B are spaced apart from each other by a predetermined distance on the semiconductor substrate 11. In this case, the gates 12A and 12B are formed by sequentially depositing a gate oxide film, a polysilicon, a tungsten silicide, and a cap nitride film on the semiconductor substrate 11 and patterning the same.
그리고, 도4b에 도시한 바와같이 상기 게이트(12A,12B)가 형성된 반도체기판(11)의 상부전면에 질화막(13)을 증착한 후, 선택적으로 식각하여 상기 게이트(12A,12B)의 측면에 측벽을 형성한다. 이때, 게이트(12A,12B)의 측벽은 고집적 반도체소자를 엘디디구조로 형성하여 단채널에 의한 영향을 최소화한다.As shown in FIG. 4B, the nitride film 13 is deposited on the upper surface of the semiconductor substrate 11 on which the gates 12A and 12B are formed, and then selectively etched to the side surfaces of the gates 12A and 12B. Form sidewalls. At this time, the sidewalls of the gates 12A and 12B form a highly integrated semiconductor device with an LED structure to minimize the influence of the short channel.
그리고, 도4c에 도시한 바와같이 상기 측벽이 형성된 반도체기판(11)의 상부전면에 고온저압 산화막(14)을 얇게 증착한다.Then, as shown in FIG. 4C, the high temperature low pressure oxide film 14 is thinly deposited on the upper front surface of the semiconductor substrate 11 on which the sidewalls are formed.
그리고, 도4d에 도시한 바와같이 상기 고온저압 산화막(14)이 증착된 반도체기판(11)의 상부전면에 감광막(15)을 도포 및 노광한 후, 현상량을 조절하여 상기 게이트(12A,12B)간 이격영역에 감광막(15)이 잔류하도록 한다. 이때, 감광막(15)은 게이트(12A,12B)의 높이가 0.9㎛에서 이격거리가 0.1㎛이하가 되면, 현상량의 조절에 의해 게이트(12A,12B)간 이격영역에 잔류한다.As shown in FIG. 4D, the photosensitive film 15 is coated and exposed on the upper surface of the semiconductor substrate 11 on which the high temperature low pressure oxide film 14 is deposited, and then the amount of development is adjusted to control the gates 12A and 12B. The photosensitive film 15 is left in the spaced apart region. At this time, when the heights of the gates 12A and 12B are 0.9 μm and the separation distance is 0.1 μm or less, the photoresist film 15 remains in the spaced area between the gates 12A and 12B by controlling the amount of development.
그리고, 도4e에 도시한 바와같이 상기 잔류된 감광막(15)을 마스크로 하여 상기 고온저압 산화막(14)을 습식식각한다. 이때, 감광막(15)의 마스킹에 의해 잔류하는 고온저압 산화막(14)과 상기 측벽의 사이에 보이드(20)가 형성되며, 이 보이드(20)는 후속 콘택공정을 위해 층간절연막을 식각할 때 식각 스토퍼(stopper)로 활용할 수 있게 되므로, 측벽의 두께를 줄일 수 있게 되어 상대적으로, 게이트(12A,12B)간 이격거리를 넓게 할 수 있다. 따라서, 종횡비(aspect ratio)가 감소된다.As shown in FIG. 4E, the high temperature low pressure oxide film 14 is wet-etched using the remaining photosensitive film 15 as a mask. At this time, a void 20 is formed between the high temperature low pressure oxide film 14 remaining by the masking of the photosensitive film 15 and the side wall, and the void 20 is etched when the interlayer insulating film is etched for the subsequent contact process. Since it can be utilized as a stopper, it is possible to reduce the thickness of the sidewalls, thereby relatively increasing the separation distance between the gates 12A and 12B. Thus, the aspect ratio is reduced.
이후에, 도5에 도시한 바와같이 상기 잔류된 감광막(15)을 제거하고, 반도체기판(11)의 상부전면에 평탄화 및 층간절연을 위한 비피에스지막(16)을 형성한다.Thereafter, as shown in FIG. 5, the remaining photoresist film 15 is removed, and the BPS film 16 is formed on the upper surface of the semiconductor substrate 11 for planarization and interlayer insulation.
이때, 게이트(12A,12B)간 이격영역에는 상기 감광막(15)의 마스킹으로 인해 고온저압 산화막(14)이 잔류하게 되어 종횡비가 감소되고, 이에 따라 비피에스지막(16)의 채워지는 특성이 향상된다.In this case, the high-temperature low-pressure oxide film 14 remains due to the masking of the photosensitive film 15 in the spaced area between the gates 12A and 12B, thereby reducing the aspect ratio, thereby improving the filling property of the BP layer 16. do.
한편, 도6은 본 발명의 다른 실시예로서, 상기 도4e에서 수행되는 고온저압 산화막(14)의 습식식각 조건을 조절하여 고온저압 산화막(14)이 상기 잔류된 감광막(15)의 중앙부까지 식각되도록 하고 상기 감광막(15)을 제거한 것으로, 후속 평탄화 및 층간절연을 위한 비피에스지막(16)의 형성시에 비피에스지막(16)의 채워지는 특성을 더욱 향상시킬 수 있다.On the other hand, Figure 6 is another embodiment of the present invention, by adjusting the wet etching conditions of the high temperature low pressure oxide film 14 performed in FIG. 4e, the high temperature low pressure oxide film 14 is etched to the center of the remaining photosensitive film 15 By removing the photosensitive film 15, the filling property of the BP film 16 may be further improved when the BP film 16 is formed for subsequent planarization and interlayer insulation.
상기한 바와같은 본 발명에 의한 고집적 반도체소자의 제조방법은 조밀한 패턴의 이격영역 사이에 종횡비 감소를 통해 평탄화 및 층간절연을 위한 막의 채워지는 특성을 향상시켜 보이드의 형성을 방지함으로써, 콘택의 신뢰성을 향상시킬 수 있는 효과가 있다.The manufacturing method of the highly integrated semiconductor device according to the present invention as described above improves the filling property of the film for planarization and interlayer insulation through the reduction of the aspect ratio between the spaced apart regions of the dense pattern, thereby preventing the formation of voids, resulting in contact reliability. There is an effect to improve.
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