KR100289674B1 - Light exposure method and light exposure device - Google Patents

Abstract

The present invention provides an exposure method for forming a prescribed pattern on a semiconductor substrate, comprising: measuring a size of a semiconductor substrate, determining an error between the design size of the semiconductor substrate and the measured size; Heating or cooling the semiconductor substrate to correct the design size and exposing a defined pattern on the semiconductor substrate. Furthermore, the present invention is an exposure apparatus for forming a prescribed pattern on a semiconductor substrate, wherein the light source for directing the exposure onto the semiconductor substrate, the detector for detecting the alignment mark formed on the semiconductor substrate, and the alignment mark are detected. And a substrate position sensor for detecting positional information about the semiconductor substrate.

The exposure apparatus is also provided with a signal processor for measuring the size of the semiconductor substrate from the output signal from the substrate position sensor and for detecting an error between the design size of the semiconductor substrate and the measured size. Moreover, the exposure apparatus is further provided with a temperature control mechanism for heating or cooling the semiconductor substrate based on the output from such a signal processing section.

Description

Exposure method and exposure device {LIGHT EXPOSURE METHOD AND LIGHT EXPOSURE DEVICE}

The present invention relates to an exposure method and an exposure apparatus, and more particularly, to an exposure apparatus and an exposure method in which a circuit pattern formed on a mask is placed on a semiconductor substrate and the circuit pattern is transferred.

In recent years, the demand for high integration in semiconductor integrated circuits has increased. Therefore, there has been a tendency for miniaturization of pattern dimensions formed on semiconductor integrated circuits. As the size of the pattern is miniaturized, the registration accuracy required in the case of overlapping the mask pattern on the semiconductor substrate becomes extremely precise.

In the manufacture of semiconductor integrated circuits, the required registration accuracy is considered to be approximately 1/4-1/3 of the minimum dimension of the pattern to be formed. In the following, an example of a dynamic random access memory (DRAM) which is a typical semiconductor integrated circuit is used to describe this registration accuracy.

For example, in a DRAM having a 64 MB (megabyte) capacity, the minimum dimension in the pattern formed on the semiconductor substrate is about 0.35 mu m. Therefore, the registration accuracy required in this case is approximately 0.10 mu m. In 256 MB DRAM, the minimum dimension of the pattern formed on the semiconductor substrate is about 0.25 mu m, and therefore the required registration accuracy is about 0.07 mu m. Furthermore, for DRAMs having a 1 GB (gigabyte) capacity, the minimum dimension of the pattern formed on the semiconductor substrate is about 0.18 mu m, and thus the required registration accuracy is extremely precise, approximately 0.05 mu m.

Here, there are many factors that affect the registration accuracy, for example, the inherent deformation of the semiconductor substrate and the mechanical accuracy of the exposure apparatus. Moreover, there are several ways to classify registration accuracy. Such methods include a method of distinguishing between chip registrations and chip registrations.

4 is a schematic plan view showing a semiconductor substrate in order to explain the state of registration between chips. As shown in Fig. 4, an alignment mark A for registration between chips is formed in advance on each chip. Therefore, the aim is to accurately overlap the mask pattern on the semiconductor substrate 35 by using the alignment mark A as a reference. Therefore, by concentrating on only one chip, a problem arises as to whether or not the mask pattern overlaps exactly with all the plurality of alignment marks on the chip. In FIG. 4, the dotted line represents the area exposed in the previous exposure process, and the solid line represents the area to be exposed in the next exposure process. In Fig. 4, there is a large difference between the two, but this difference is exaggerated in the drawing, and the actual difference is small.

On the other hand, Figs. 5A and 5B show a schematic plan view of a chip for explaining registration in the chip. In the registration in the chip, the goal is to accurately overlap the mask pattern with respect to the plurality of alignment marks (A-I) or several points in the chip. In Fig. 5 (a), the mask pattern lies exactly on the alignment mark (A). However, it is not exactly placed on the other alignment mark (B-H). In the particular case shown, the semiconductor substrate 35 is somewhat smaller than the design dimensions. Furthermore, in Fig. 5B, the mask pattern is exactly placed on the alignment mark A, but the other alignment marks B-H are somewhat moved in the direction of rotation with respect to the alignment mark A.

The accuracy of registration between chips is mainly influenced by the accuracy and stage accuracy of the alignment sensor of the exposure apparatus. On the other hand, the registration accuracy in the chip is mainly influenced by the distortion (warping, distortion, instability in magnification) and reticle rotation of the lens used in the exposure apparatus.

Methods for improving inter-chip registration accuracy and in-chip registration accuracy have been the subject of urgent research. In particular, the manufacture of highly integrated memory, such as 256 MB DRAM, has focused on a very important issue that increases registration accuracy within the chip. As described below, there are two important reasons for this.

The first reason is that a silicon nitride film, a silicon oxide film, and a polycrystalline film cause deformation of the semiconductor substrate when it is formed on the semiconductor substrate and thus cause a registration error (Ref .: Akira IMAI et al., SPIE 2726, pp. 104-112). Because I know. The second reason is that as the chip size increases as the semiconductor substrate expands or contracts at a predetermined rate, the degree of error in registration in the chip also increases.

6 is a plan view of a single chip for explaining the registration error in the chip. By registering a black rectangle having a rectangular shape on the outside, the exposure pattern is superimposed on the chip. 7 is a table showing the relationship between the film thickness and the film type and the amount of deformation of the semiconductor substrate formed on the semiconductor substrate. As shown in Fig. 6, an example of such an error in registration in the chip caused by the deformation of the semiconductor substrate is based on the semiconductor substrate having a length of 22 mm in the longer direction. By placing two registration error measurement marks in the longer direction of the chip and forming a film of different material, the degree of deformation in the semiconductor substrate was investigated. As shown in the table of Fig. 7, it can be seen from the corresponding result that a maximum registration error of about 0.1-0.2 [mu] m occurred in the chip, which would result in 256 MB DRAM memory or equivalent device if no correction is taken. Not suitable for manufacturing

In the prior art, a method in which the projection magnification is somewhat adjusted in the projection and exposure apparatus has been provided for correcting the registration error in the chip caused by the deformation of the semiconductor substrate. Such an example is described below.

8 is a flowchart illustrating an example of the prior art for a method for correcting a registration error in a chip. 9 shows alignment marks formed on a wafer to calculate registration errors. In this calibration method, first in step A of FIG. 8, the semiconductor substrate to which the photoresist is applied is conveyed to the exposure apparatus and mounted in the holder. Next, in step B of FIG. 8, the semiconductor substrate is aligned. In step C, the amount of error at several points on the semiconductor substrate is measured by the alignment sensor of the exposure apparatus. If, for example, the error is measured at four points near the periphery of the semiconductor substrate (alignment mark (J-M)), the semiconductor substrate is deformed in the X and Y directions using the following equations in steps C and D: Can be determined.

Strain in the X direction: (dX4 + dX3) / L _x (ppm) ... equation (1)

Deformation in the Y direction: (dY1 + dY2) / L _y (ppm) ... equation (2)

Here, dY1 is an error in the Y direction in the alignment mark J, -dY2 is an error in the Y direction in the alignment mark K, and none represents an equivalent value for the alignment mark. Moreover, -dX3 is an error in the X direction in the alignment mark L, and dX4 is an error in the X direction in the alignment mark M. The error is the difference between the design value and the measured value when the center of the semiconductor substrate is correctly positioned. Moreover, Ly is the distance between alignment marks (J, K) and Lx is the distance between alignment marks (L, M). In order to simplify the description, the error in the X direction in the alignment marks (J, K) was taken as 0, and the error in the Y direction in the alignment marks (L, M) was taken as 0.

Finally, in step F, corrections are made to movement, rotation, verticality, size reduction, and the like. In parallel with this calibration, in steps G and H, the amount of correction from the strain ratio of the substrate to the projection magnification is determined as derived in the previous step, and the semiconductor substrate is exposed in step I when the projection magnification is corrected. .

However, the prior art method for calibrating registration in the chip involves the following problem. That is, fine adjustment of the projection magnification is performed by changing the air pressure between groups of projection lenses to change the refractive index between the projection lens and the air. However, there is a limitation due to the lens design for the range of refractive index adjustment. Specifically, if the projection magnification of the exposure apparatus using the reduction projection method is converted to the strain ratio of the semiconductor substrate, the possible change is limited to the range of about 5-10 ppm.

Moreover, in the equal magnification X-ray exposure apparatus, which is a typical equal magnification exposure apparatus, it is impossible in principle to adjust the ratio of magnification, and thus any deformation occurring in the semiconductor substrate cannot be corrected in this manner.

It is an object of the present invention to provide an exposure apparatus and an exposure method in which accurate registration in a chip can be achieved for a wide range of strain ratios in a semiconductor substrate, regardless of the type of exposure system used.

In order to achieve the above object, the present invention includes the following steps in an exposure method for forming a prescribed pattern onto a semiconductor substrate. That is, the size of the semiconductor substrate is measured and the difference between the measured size and the design size of the semiconductor substrate is found. Thus, the semiconductor substrate is heated or cooled to calibrate the semiconductor substrate to its design size. The light of a prescribed pattern is exposed on the semiconductor substrate.

Hereinafter, the operation of the present invention provided as described above. In each semiconductor manufacturing step, the temperature of the semiconductor substrate is changed. Moreover, due to the action of various films formed on the semiconductor substrate, errors may occur between the actual size of the semiconductor substrate and its design size. However, in the present invention, after adjusting the temperature of the semiconductor substrate so that any error is eliminated, the pattern is exposed. Therefore, accurate exposure can always be performed.

The exposure apparatus according to the present invention functions as a light source for illuminating an exposure onto a semiconductor substrate, a detector for detecting an alignment mark on the semiconductor substrate, and a substrate position sensor for detecting position information with respect to the semiconductor substrate when the alignment mark is detected. A laser interferometer is provided. The exposure apparatus includes a signal processor and a temperature control mechanism, which measures the size of the semiconductor substrate from the output signal of the laser interferometer, calculates an error between the design size and the measured size of the semiconductor substrate, and the temperature control mechanism. Heats or cools the semiconductor substrate based on the output from the signal processor.

1 is a schematic cross-sectional view of an exposure apparatus according to a first embodiment of the present invention.

2 is a flowchart showing an exposure method using the exposure apparatus according to the first embodiment of the present invention.

3 is a schematic cross-sectional view of an exposure apparatus according to a second embodiment of the present invention.

4 is a plan view of a semiconductor substrate showing a registration state between chips;

FIG. 5 is a plan view of a chip for explaining an error corresponding to an exposure pattern in the case of registration in a chip, FIG. 5A is a view showing a chip spread out with respect to a center alignment mark, and FIG. 5B is rotated with respect to the center alignment mark. Figure showing a chip.

6 is a plan view of a semiconductor chip for explaining the registration error in the chip.

7 is a table showing the relationship between deformation of a semiconductor substrate and film type and film thickness in general semiconductor manufacturing.

8 is a flowchart for explaining an example of the prior art of the method for correcting the registration error in the chip.

9 is a diagram of alignment marks on a semiconductor substrate in accordance with one example of the prior art.

Explanation of symbols on the main parts of the drawings

1: Temperature regulating fluid circulation mechanism 2: Temperature sensor

7: optical transceiver 8: stage

9: holder 11: laser interferometer

12 projection lens 13 reticle

17: He-Ne laser 19: fly eye lens

20: reflector 23: focusing lens

Hereinafter, with reference to the drawings will be described a specific embodiment of the present invention.

1 is a schematic cross-sectional view of an exposure apparatus of an embodiment of the present invention. As shown in Fig. 1, this exposure apparatus has a stage on which an excimer laser and a semiconductor substrate 35 are mounted, which serve as a light source for generating exposure L. As shown in FIG. This exposure apparatus is also provided with a detector 6. This detector 6 recognizes an alignment mark previously formed on the semiconductor substrate 35 by the optical transceiver 7. The alignment marks are formed (four total positions or more) on the semiconductor substrate 35 respectively in directions perpendicular to each other (X and Y directions) at at least two positions (a general example of alignment marks, the arrangement shown in FIG. May be used in the present invention).

The exposure apparatus is also provided with a holder 9 on which the semiconductor substrate 35 is mounted and a position of a signal and an alignment mark from the detector 6 as well as a temperature control fluid circulation mechanism 1 installed inside the holder 9. And a control unit 4 and a signal processing unit 5 for determining the deformation ratio of the semiconductor substrate 35. The exposure apparatus has a temperature controller (3) based on a temperature sensor (2) for measuring the temperature of the semiconductor substrate (35) placed on the holder (9) and a signal from a signal processor and a signal from the temperature sensor (2). And a control unit 4 for providing PID control.

The exposure L of such an exposure apparatus is produced using an excimer laser of 248 nm wavelength, for example. This excimer laser 22 emits KrF excimer laser light that includes only a specific frequency band. This exposure L is deformed into a suitable form by the beam extender 21. Then, it is transferred to the fly's eye lens 19 via the reflector 20. This fly's-eye lens 19 has an array of a plurality of small lenses, allowing a uniform exposure L to be transferred to a reticle to be described later. The exposure L is deformed again by passing through the aperture stop 18 and the focusing lens 23. Finally, the exposure L is uniformly illuminated on the reticle 13. The circuit pattern is previously formed on the reticle 13. As a result, the exposure L that has passed through the circuit pattern of the reticle 13 is reduced to the projection magnification defined by the projection lens 12 and is focused on the surface of the semiconductor substrate 35 so that the desired pattern is placed thereon. Exposed.

The exposure apparatus includes an alignment optical system in addition to the exposure optical system. In this alignment optical system, the laser light from the He-Ne laser 17 is transferred onto the alignment mark formed on the semiconductor substrate 35 via the reflectors 15, 16 and the optical transceiver 7, and the positional information Is collected by a detector 6 that detects diffracted light. The light used for alignment does not need to be He-Ne laser light, and light in a wide wavelength range can be used to detect an image of the alignment mark. The same optical system can also be used for alignment and exposure.

The temperature control fluid circulation mechanism 1 for raising and lowering the temperature of the semiconductor substrate 35 is installed in the holder 9 and connected to the temperature controller 3 through a defined pipework. In addition, a temperature sensor 2 is installed in the holder 9. The temperature sensor 2 is a high resolution sensor using a platinum resistance etc., for example. The output signal from the temperature sensor 2 installed in the holder 9 is transmitted to the control section 4 described above. The controller 4 performs PID control of the temperature controller 3 so that the temperature of the semiconductor substrate 35 reaches a prescribed temperature in a short time.

Next, the step of measuring the actual distance between the alignment marks in order to calculate the strain ratio of the semiconductor substrate 35 is described. As already mentioned, the alignment mark is formed in the X direction or the Y direction of the semiconductor substrate 35. The He-Ne laser is continuously irradiated from the optical transceiver 7 onto the semiconductor substrate 35. When the alignment mark on the semiconductor substrate 35 comes directly under the optical transceiver 7, this alignment mark is detected by the detector 6. At this point, the positional information related to the semiconductor substrate is measured by the laser interferometer 11 serving as the substrate position sensor, and this information is recorded. Thus, the stage 8 is moved again until the next alignment mark is below the optical transceiver 7. The position of the semiconductor substrate 35 when this alignment mark comes under the optical transceiver 7 is measured. The actual distance between the alignment marks is detected from the positional information about the semiconductor substrate 35 as measured by the laser interferometer 11. The laser interferometer actually measures the distance traveled by the stage 8 directly, but since the semiconductor substrate 35 is mounted on the stage 8, the distance between the alignment marks can be measured accurately.

Here, it is preferable to provide at least two alignment marks in each X and Y direction, that is, four or more alignment marks in the X and Y direction, respectively. In particular, if an alignment mark is provided outside the semiconductor substrate 35, the deformation ratio of the semiconductor substrate 35 can be determined by the above-described equations (1) and (2). By increasing the number of alignment marks, the deformation ratio can be determined more accurately.

Next, a method for correcting an error in an exposure pattern caused by deformation of the semiconductor substrate 35 according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 2 is a flowchart showing an exposure method using the exposure apparatus shown in FIG. 1.

First, in step A of FIG. 2, the semiconductor substrate 35 (wafer) is mounted on the holder 9 shown in FIG. 1, and in step B, the temperature of the semiconductor substrate 35 by the temperature sensor 2 is obtained. Is measured. In step C, the stage 8 is moved so that the semiconductor substrate 35 is aligned with the optical transceiver 7. Here, the temperature measuring step (B) and the sorting step (C) may be reversed in order. Next, in step D, alignment marks formed at a plurality of positions on the semiconductor substrate 35 (wafer) are detected by the detector 6 through the optical transceiver 7. In step E, the signal processing unit 5 calculates the deformation ratio by comparing the detected distance between the alignment marks with the design distance between the predetermined alignment marks. In steps F and G, errors are calculated and corrected respectively.

Next, a procedure for correcting the error is described. In general, the deformation (dL) of a material due to temperature changes can be known from the equation: where α is a constant of thermal expansion.

L = L0 (1 + αT) ... (3)

dL = L2-L1 = L0 (1 + αT2)-L0 (1-αT1) ... (4)

From here,

L: length of material

T: temperature

L1: length of material at temperature T1

L2: length of material at temperature T2

Deformation dL is derived from the above amount of error, and T1 is a predetermined temperature of the semiconductor substrate. L0 is the theoretical distance between the alignment marks and can be determined if information relating to the chip design specification is provided. The constant (α) of thermal expansion is a material-specific value, 2.6 × 10 ⁻⁶ for silicon. Preferably, in order to correct the error more accurately, the constant of thermal expansion should be determined for each film application and pattern formation step in the semiconductor manufacturing process. However, in the case of a typical 6 inch diameter silicon semiconductor substrate, the thickness of the substrate itself is approximately 700 占 퐉, so that if this value is used, it is large enough so that no large error occurs in comparison with the thicknesses of the various films subsequently formed.

Next, in step H, the target substrate temperature T2 is determined. For example, suppose that the temperature of the semiconductor substrate 35 is 23 ° C., the distance between the alignment marks is 100 mm, and the error between the two alignment marks is −0.50 μm (the plate shrinks with respect to the design value). Using equations (1) and (2), the target substrate temperature T2 can be calculated as about 24.92 ° C. Conversely, if the substrate is extended with respect to the design value, the target substrate temperature T2 is set to about 21.08 ° C.

If the target substrate temperature T2 is determined based on the calculation result from the controller 4 shown in Fig. 1, the temperature of the semiconductor substrate in step I is controlled by the temperature control mechanism. In particular, the temperature of a fluid such as fluoride (water may be used) is controlled by the thermostat 3. This fluid is circulated through the holder 9 to regulate the temperature of the semiconductor substrate 35 via the holder 9. The temperature of the semiconductor substrate 35 is measured by the PID controlled by the temperature sensor 2 and the controller 4. Next, step J confirms when the temperature of the semiconductor substrate 35 is sufficiently close to, for example, within ± 0.2 ° C. to the target substrate temperature T2, and then exposure is started in step K. In this case, the moving component, the rotating component, and the like are also corrected in parallel with the process of correcting the deformation of the semiconductor substrate 35. In this way, errors due to deformation of the semiconductor substrate can be corrected accurately. Considering the temperature control mechanism separately from the system using the fluid defined as above, the temperature can be electrically controlled by providing thermoelectric wiring or the like to the holder.

Furthermore, according to the present invention, in the case of a silicon semiconductor substrate, the deformation is corrected by approximately 2.6 ppm per 1 degree C temperature change, so if a 20 ppm calibration is required, a temperature change of about 8 ° C. is sufficient. There is no detrimental effect of this temperature change on the photoresist. Therefore, the optical response of the photoresist occurs without disturbance, and therefore the error is corrected over a wide range of strain ratios. The temperature of the semiconductor substrate is in the range of 20-30 ° C.

3 shows a schematic cross-sectional view of a second embodiment. As shown in FIG. 3, this exposure apparatus differs from the first embodiment in that a temperature regulating section 3a is provided in the pipework between the thermostat 3 and the thermostatic fluid circulation mechanism 1. Apart from this, the configuration is the same as the exposure apparatus shown in FIG.

When the plurality of semiconductor substrates are exposed, if the temperature of the semiconductor substrate 35 is controlled by the temperature controller 3 alone, it takes a long time to reach the target substrate temperature T2 even if PID control is used. As a result, the throughput in semiconductor manufacturing is reduced. To avoid this problem, when a plurality of semiconductor substrates are processed, continuing from the second semiconductor substrate 35, the semiconductor substrate 35 is first placed on the temperature regulating section 22 so that the temperature is previously set to the target substrate temperature. Adjusted. Thereafter, the temperature is adjusted by the temperature regulating section 3a, and then the semiconductor substrate is mounted to the holder 9, and the temperature is adjusted as described in the first embodiment, and then exposed.

By regulating the temperature of the continuous semiconductor substrate in advance by the temperature regulating section 3a, the time for the semiconductor substrate to reach the target substrate temperature is reduced, whereby the effect of improved throughput in semiconductor manufacturing can be obtained. However, the present invention is not limited to this, and a thermostat including thermoelectric wiring or the like may also be used.

As described above, in the present invention, the distance between the alignment marks is measured and this distance is compared with the design distance to measure the error between the two. The strain ratio of the semiconductor substrate after pretreatment is determined, the semiconductor substrate is heated or cooled to a target substrate temperature corresponding to this strain ratio, and the pattern is exposed. Therefore, the error is corrected and accurate registration in the chip is possible, and registration defects are reduced to increase the yield in semiconductor manufacturing.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the embodiments of the invention should be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and therefore equivalent to the claims. All changes in scope and its contents are included therein.

The complete disclosure of Japanese Patent Application No. 09-005375, which includes the specification, drawings and abstract, is incorporated by reference in its entirety.

According to the present invention described above, after measuring the distance between the alignment mark and comparing this distance with the design distance and measuring the error between the two and pre-processing, the strain ratio of the semiconductor substrate is determined, and the target corresponding to this strain ratio An exposure apparatus having the effect of heating or cooling the semiconductor substrate to a substrate temperature, and then transferring the pattern, thereby correcting errors and allowing accurate registration in the chip, and reducing defects in registration to increase the yield in semiconductor manufacturing; and An exposure method is provided.

Claims (20)

An exposure method for forming a prescribed pattern on a semiconductor substrate, Measuring a size of the semiconductor substrate; Determining an error between the design size of the semiconductor substrate and the measured size; Heating or cooling the semiconductor substrate to calibrate the semiconductor substrate to the design size; And Exposing a prescribed pattern of light to the semiconductor substrate. 2. An exposure method according to claim 1, wherein the size of the semiconductor substrate is measured by measuring a distance between two or more alignment marks previously formed on the surface of the semiconductor substrate. The exposure method of claim 2, wherein the at least two alignment marks are formed on the surface of the semiconductor substrate in a direction perpendicular to each other. The exposure method of claim 2, wherein the alignment mark is formed near an outer edge of the semiconductor substrate. The semiconductor device of claim 2, wherein one of the at least two alignment marks is detected and at the same time position information about the semiconductor substrate is recorded. Another one of the two or more alignment marks is detected and at the same time the position information of the semiconductor substrate is recorded, And the size of the semiconductor substrate is calculated from the positional information. An exposure method for forming a prescribed pattern on a semiconductor substrate, Measuring a size of the semiconductor substrate; Determining an error between the design size and the measured size of the semiconductor substrate; Detecting a temperature of the semiconductor substrate and calculating a temperature difference between the temperature and a target substrate temperature to adjust the semiconductor substrate to the design size; Heating or cooling the semiconductor substrate based on the temperature difference; And Exposing a prescribed pattern on a surface of the semiconductor substrate. 7. An exposure method according to claim 6, wherein the size of the semiconductor substrate is measured by measuring a distance between two or more alignment marks previously formed on the surface of the semiconductor substrate. 8. The exposure method according to claim 7, wherein the at least two alignment marks are formed on the surface of the semiconductor substrate in a direction perpendicular to each other. 8. The exposure method according to claim 7, wherein the at least two alignment marks are formed near an outside of the semiconductor substrate. 8. The semiconductor device according to claim 7, wherein one of the at least two alignment marks is detected and at the same time position information for the semiconductor substrate is recorded, The other of the two or more alignment marks is detected and at the same time the positional information about the semiconductor substrate is recorded, And the size of the semiconductor substrate is calculated from the positional information. As a method of forming a prescribed pattern on a semiconductor substrate, Measuring a size of the semiconductor substrate; Determining an error between the design size of the semiconductor substrate and the measured size; Detecting a temperature of the semiconductor substrate; Calculating a temperature difference for heating and cooling from an error between an actual size and a design size of the semiconductor substrate and a thermal expansion constant of the semiconductor substrate; Heating or cooling the semiconductor substrate based on the temperature difference to correct the size of the semiconductor substrate to a design size; And Exposing a prescribed pattern on a surface of the semiconductor substrate. 12. An exposure method according to claim 11, wherein the size of the semiconductor substrate is measured by measuring a distance between two or more alignment marks previously formed on the surface of the semiconductor substrate. The exposure method of claim 12, wherein the at least two alignment marks are formed on the surface of the semiconductor substrate in a direction perpendicular to each other. The method of claim 12, wherein the at least two alignment marks are formed near an outer edge of the semiconductor substrate. 13. The method of claim 12, wherein one of the two or more alignment marks is detected and at the same time the positional information about the semiconductor substrate is recorded, The other of the two or more alignment marks is detected and at the same time the positional information about the semiconductor substrate is recorded, And the size of the semiconductor substrate is calculated from the positional information. An exposure apparatus for forming a prescribed pattern on a semiconductor substrate, A light source for transferring an exposure onto the semiconductor substrate; A detector for detecting an alignment mark formed on the semiconductor substrate; A substrate position sensor for detecting position information on the semiconductor substrate when the alignment mark is detected; A signal processor for measuring the size of the semiconductor substrate from the output signal from the substrate position sensor and detecting an error between the measured size and the design size of the semiconductor substrate; And And a temperature adjusting mechanism for heating or cooling the semiconductor substrate based on the output from the signal processor. 17. An exposure apparatus according to claim 16, further comprising a temperature sensor for detecting a temperature of said semiconductor substrate. 18. An exposure apparatus according to claim 17, further comprising a control unit for calculating a heating temperature or a cooling temperature based on an error in temperature information from the temperature sensor and a size of a semiconductor substrate from the signal processing unit. . The method of claim 16, wherein the temperature control mechanism A thermostat for adjusting a specified thermostat fluid to a specified temperature, and And a temperature control fluid circulation mechanism for circulating the temperature control fluid in the vicinity of the semiconductor substrate. 20. The exposure apparatus according to claim 19, wherein the temperature control mechanism includes a temperature control unit for preheating or cooling the semiconductor substrate to a temperature close to the target substrate temperature before the exposure process.