KR100250753B1 - Fabrication method of flash memory cell - Google Patents
Fabrication method of flash memory cell Download PDFInfo
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- KR100250753B1 KR100250753B1 KR1019960054381A KR19960054381A KR100250753B1 KR 100250753 B1 KR100250753 B1 KR 100250753B1 KR 1019960054381 A KR1019960054381 A KR 1019960054381A KR 19960054381 A KR19960054381 A KR 19960054381A KR 100250753 B1 KR100250753 B1 KR 100250753B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
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- Toxicology (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
본 발명은 플래쉬 메모리 셀의 제조 방법에 관한 것으로, 특히 제조 공정을 단순화시킬 수 있도록 한 플래쉬 메모리 셀의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell capable of simplifying a manufacturing process.
일반적으로 전기적인 프로그램(Program) 및 소거(Erasure) 기능을 가지는 플래쉬(Flash) 메모리 소자의 메모리 셀은 게이트 전극의 형태에 따라 적층-게이트형(Stack-gate type)과 스프리트-게이트 형(Split-gate type)으로 나누어진다. 그러면 스프리트-게이트 형의 게이트 전극을 갖는 종래 플래쉬 메모리 셀의 제조 방법을 도1a 내지 도1d를 통해 설명하면 다음과 같다.In general, a memory cell of a flash memory device having an electric program and an erasure function has a stack-gate type and a split-gate type according to the shape of a gate electrode, gate type). A method of manufacturing a conventional flash memory cell having a split-gate type gate electrode will now be described with reference to FIGS. 1A to 1D.
도1a는 실리콘 기판(1)상에 터널 산화막(2), 제1폴리실리콘층(3), 유전체막(4) 및 제2폴리실리콘층(5)을 순차적으로 형성한 상태의 단면도로서, 상기 제1 및 제2폴리실리콘층(3 및 5)은 폴리실리콘을 증착한 후 불순물 이온을 주입 또는 도핑하여 형성한다. 그리고 상기 유전체막(4)은 질화막으로 형성하거나, 산화막, 질화막 및 산화막이 적층된 ONO 구조로 형성한다.1A is a cross-sectional view of a state in which a tunnel oxide film 2, a first polysilicon layer 3, a dielectric film 4 and a second polysilicon layer 5 are sequentially formed on a silicon substrate 1, The first and second polysilicon layers 3 and 5 are formed by implanting or doping impurity ions after depositing polysilicon. The dielectric film 4 is formed of a nitride film or an ONO structure in which an oxide film, a nitride film, and an oxide film are laminated.
도1b는 상기 제2폴리실리콘층(5), 유전체막(4), 제1폴리실리콘층(3) 및 터널 산화막(2)을 순차적으로 패터닝하여 상기 실리콘 기판(1)상에 터널 산화막(2), 플로팅 게이트(3A), 유전체막(4) 및 콘트롤 게이트(5A)가 적층된 구조의 게이트 전극을 형성한 후 상기 게이트 전극의 양측벽에 절연막 스페이서(6)를 형성한 상태의 단면도이다.1B is a plan view of the tunnel oxide film 2 on the silicon substrate 1 by successively patterning the second polysilicon layer 5, the dielectric film 4, the first polysilicon layer 3 and the tunnel oxide film 2, ), The floating gate 3A, the dielectric film 4, and the control gate 5A are formed on the gate insulating film 5, and then the insulating film spacers 6 are formed on both side walls of the gate electrode.
도1c는 전체 상부면에 셀렉트 게이트 산화막(7) 및 제3폴리실리콘층(8)을 순차적으로 형성한 상태의 단면도이고, 도1d는 상기 제3폴리실리콘층(8)을 패터닝하여 셀렉트 게이트(8A)를 형성하고 노출된 부분의 상기 실리콘 기판(1)에 불순물 이온을 주입하여 접합영역(9)을 형성한 상태의 단면도이다.1C is a cross-sectional view in which a select gate oxide film 7 and a third polysilicon layer 8 are sequentially formed on the entire upper surface. FIG. 1D is a cross-sectional view of the third polysilicon layer 8, 8A are formed on the silicon substrate 1 and impurity ions are implanted into the silicon substrate 1 of the exposed portion to form a junction region 9.
그런데 상기와 같은 메모리 셀의 제조 방법은 상기 터널 산화막, 셀렉트 게이트 산화막과 같이 질(Quality)을 제어하기 어려운 산화막 형성 과정을 포함하며 공정의 단계도 복잡하여 수율이 낮아지는 단점을 갖는다. 또한 최상부에 형성되는 상기 셀렉트 게이트(8A)의 폭은 사진 장비의 임계치수와 무관하게 설정되기 때문에 전체적인 메모리 셀의 크기를 감소시키기 어려우며, 따라서 고집적 소자의 제조에 상기와 같은 메모리 셀 제조 방법을 적용하기 어려운 실정이다.However, the above-described method of manufacturing a memory cell has a disadvantage in that it involves an oxide film formation process which is difficult to control quality, such as the tunnel oxide film and the select gate oxide film, and the process is complicated and the yield is low. In addition, since the width of the select gate 8A formed at the uppermost portion is set independent of the critical number of the photographic equipment, it is difficult to reduce the size of the entire memory cell. Therefore, This is a difficult situation.
따라서 본 발명은 폴리실리콘층을 형성한 후 패터닝하여 플로팅 게이트와 셀렉트 게이트 동시에 형성하므로써, 제조 공정을 단순화하고 셀의 크기를 감소시킬 수 있는 플래쉬 메모리 셀의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, it is an object of the present invention to provide a method of manufacturing a flash memory cell that can simplify a manufacturing process and reduce a size of a cell by simultaneously forming a floating gate and a select gate after forming a polysilicon layer and patterning the polysilicon layer.
상술한 목적을 달성하기 위한 본 발명에 따른 플래쉬 메모리 셀의 제조 방법은 실리콘 기판상에 게이트 산화막 및 제1폴리실리콘층을 순차적으로 형성한 후 상기 제1폴리실리콘층을 패터닝하여 플로팅 게이트 및 셀렉트 게이트를 각각 형성하는 제1단계와, 상기 플로팅 게이트 및 셀렉트 게이트의 양측벽에 절연막 스페이서를 형성한 후 전체 상부면에 유전체막 및 제2폴리실리콘층을 순차적으로 형성하는 제2단계와, 상기 제2폴리실리콘층을 패터닝하여 상기 플로팅 게이트 상부에 콘트롤 게이트를 형성한 후 노출된 상기 실리콘 기판에 불순물 이온을 주입하여 접합영역을 형성하는 제3단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a flash memory cell, including: forming a gate oxide layer and a first polysilicon layer on a silicon substrate in sequence; patterning the first polysilicon layer; A second step of sequentially forming a dielectric film and a second polysilicon layer on the entire upper surface after forming insulating film spacers on both side walls of the floating gate and the select gate, And a third step of patterning the polysilicon layer to form a control gate on the floating gate, and then implanting impurity ions into the exposed silicon substrate to form a junction region.
도1a 내지 도1d는 종래 플래쉬 메모리 셀의 제조 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory cell.
도2a 내지 도2e는 본 발명에 따른 플래쉬 메모리 셀의 제조 방법을 설명하기 위한 소자의 단면도.FIGS. 2A to 2E are sectional views of a device for explaining a method of manufacturing a flash memory cell according to the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1 및 11 : 실리콘 기판 2 : 터널 산화막1 and 11: Silicon substrate 2: Tunnel oxide film
3 및 13 : 제1폴리실리콘층 3A 및 13A : 플로팅 게이트3 and 13: first polysilicon layers 3A and 13A: floating gate
4 및 14 : 유전체막 5 및 15 : 제2폴리실리콘층4 and 14: dielectric films 5 and 15: second polysilicon layer
5A 및 15A : 콘트롤 게이트 6 및 16 : 절연막 스페이서5A and 15A: control gates 6 and 16: insulating film spacer
7 : 셀렉트 게이트 8 : 제3폴리실리콘층7: select gate 8: third polysilicon layer
8A 및 13B : 셀렉트 게이트 12 : 게이트 산화막8A and 13B: select gate 12: gate oxide film
9 및 19 : 접합영역9 and 19: joint regions
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도2a 내지 도2e는 본 발명에 따른 플래쉬 메모리 셀의 제조 방법을 설명하기 위한 소자의 단면도이다.2A to 2E are cross-sectional views of a device for explaining a method of manufacturing a flash memory cell according to the present invention.
도2a는 실리콘 기판(11)상에 게이트 산화막(12) 및 제1폴리실리콘층(13)을 순차적으로 형성한 상태의 단면도이고, 도2b는 상기 제1폴리실리콘층(13)을 패터닝하여 서로 인접된 플로팅 게이트(13A) 및 셀렉트 게이트(13B)를 각각 형성한 후 상기 플로팅 게이트(13A) 및 셀렉트 게이트(13B)의 양측벽에 절연막 스페이서(16)를 형성한 상태의 단면도로서, 상기 제1폴리실리콘층(13)을 패터닝한 후 상기 플로팅 게이트(13A) 및 셀렉트 게이트(13B) 사이의 상기 실리콘기판(11)에 불순물 이온을 주입하여 채널(Channel) 영역의 채널 저항값을 조절하면 전자의 주입 효율을 향상시킬 수 있다.FIG. 2A is a cross-sectional view of a state in which a gate oxide film 12 and a first polysilicon layer 13 are sequentially formed on a silicon substrate 11, FIG. 2B is a cross-sectional view of the first polysilicon layer 13, Sectional view of a state in which insulating gate spacers 16 are formed on both side walls of the floating gate 13A and the select gate 13B after the adjacent floating gates 13A and select gates 13B are formed, After the polysilicon layer 13 is patterned and impurity ions are implanted into the silicon substrate 11 between the floating gate 13A and the select gate 13B to adjust the channel resistance value of the channel region, The injection efficiency can be improved.
도2c는 전체 상부면에 유전체막(14) 및 제2폴리실리콘층(15)을 순차적으로 형성한 상태의 단면도로서, 상기 제1 및 제2 폴리실리콘층(13 및 15)은 폴리실리콘을 증착한 후 불순물 이온을 주입 또는 도핑하여 형성한다. 그리고 상기 유전체막(14)은 질화막으로 형성하거나, 산화막, 질화막 및 산화막이 적층된 ONO구조로 형성한다.FIG. 2C is a cross-sectional view showing a state in which the dielectric film 14 and the second polysilicon layer 15 are sequentially formed on the entire upper surface, and the first and second polysilicon layers 13 and 15 are formed by depositing polysilicon And then impurity ions are implanted or doped. The dielectric film 14 is formed of a nitride film or an ONO structure in which an oxide film, a nitride film, and an oxide film are stacked.
도2d는 상기 제2폴리실리콘층(15)을 패터닝하여 상기 플로팅 게이트(13A) 상부에 콘트롤 게이트(15A)를 형성한 후 노출된 상기 실리콘 기판(11)에 불순물 이온을 주입하여 접합영역(19)을 형성한 상태의 단면도로서, 이때 도2e에 도시된 바와 같이 상기 콘트롤 게이트(15A)는 상기 플로팅 게이트(13A)의 상부로부터 상기 셀렉트 게이트(13B)의 가장자리까지 연장되도록 즉, 상기 셀렉트 게이트(13B)와 중첩되지 않도록 형성된다.The second polysilicon layer 15 is patterned to form a control gate 15A on the floating gate 13A and impurity ions are implanted into the exposed silicon substrate 11 to form a junction region 19 The control gate 15A is formed so as to extend from the upper portion of the floating gate 13A to the edge of the select gate 13B as shown in FIG. 2E, 13B.
상술한 바와 같이 본 발명에 의하면, 폴리실리콘층 형성 후 플로팅 게이트와 셀렉트 게이트를 동시에 패터닝하여 형성하므로써 공정의 단계가 단순화되어 소자의 수율이 향상된다. 또한 상기 셀렉트 게이트의 폭을 감소시켜 전체적인 메모리 셀의 크기를 감소시킬 수 있으므로 고집적 메모리 소자의 제조가 가능해지는 탁월한 효과가 있다.As described above, according to the present invention, since the floating gate and the select gate are formed by patterning simultaneously after the polysilicon layer is formed, the step of the process is simplified and the yield of the device is improved. In addition, since the width of the select gate can be reduced to reduce the size of the entire memory cell, it is possible to manufacture a highly integrated memory device.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960054381A KR100250753B1 (en) | 1996-11-15 | 1996-11-15 | Fabrication method of flash memory cell |
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| KR1019960054381A KR100250753B1 (en) | 1996-11-15 | 1996-11-15 | Fabrication method of flash memory cell |
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| KR100250753B1 true KR100250753B1 (en) | 2000-04-01 |
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