KR100249862B1 - Multi-channel accumulator using multi-step adder of pipe line structure - Google Patents

Abstract

The present invention relates to a cumulative integrator that is used to implement a signal synchronization acquisition device in a broadband CDMA system. Multi-channel cumulative integrator using one cumulative adder, consisting of a value multiplexer and a pipelined multi-step adder for adding each multiplexer output, and a cumulative integral intermediate value storage device for storing each cumulative integral value Therefore, by accumulating the cumulative integration of multiple channel signals in time division with the same cumulative integrator, an efficient initial synchronization device can be configured to save hardware resources.

Description

Multi-channel cumulative integrator using multi-step cumulative adder of pipeline structure

The present invention relates to a cumulative integrator device which is essentially used for implementing a signal synchronization acquisition device in a wideband CDMA system.

The role of the cumulative integrator used in the signal synchronizer is to calculate the cumulative integral of the signal input to the signal synchronizer. The device continuously accumulates a large amount of signal input and therefore requires a very high bit count adder. However, as the number of bits of the adder increases, a lot of hardware resources are consumed, and thus the operation speed of the adder is slowed down.

An initial searcher for operating at high chip rates in a wideband CDMA system requires a very high speed multi-bit accumulator. That is, the number of bits of the cumulative adder required for the initial synchronization device implementation of the CDMA signal is proportional to the cumulative integration depth for initial synchronization acquisition of the signal. If the signal cumulative integration length of the initial synchronization acquisition device is very long, the number of bits of the cumulative integrator increases proportionally. This increase in the number of bits serves as a decisive factor in slowing the operation speed of the initial signal acquisition device.

The present invention relates to a CDMA system base station signal initial synchronization acquisition device using an EPLD, a conventional method using one cumulative adder in one channel has been used.

This method has a disadvantage in that a large amount of cumulative integrator is required when there are several signal channels used in the base station signal initial synchronization device, which requires a lot of hardware resources.

Therefore, in the present invention, a cumulative integrator of a pipeline structure is used to implement a cumulative integrator essential for implementing an initial synchronization acquisition device for a wideband CDMA system base station. It is an object of the present invention to provide a multi-channel cumulative integrator using a multi-step cumulative adder having a pipelined structure that configures hardware to perform calculation using a time division method.

1 is a schematic diagram of a signal acquisition apparatus having a multi-channel cumulative integrator according to the present invention;

2 is a multi-channel cumulative integrator diagram using a multi-step adder having a pipeline structure.

* Description of the symbols for the main parts of the drawings *

200,208 multiplexing means 201 code extension means

202: bit separating means for input signal 210,220,230: adding means for each bit

203: bit coupling means 204: switch means

205: demultiplex means 206, 207: cumulative intermediate value storage means

209: cumulative intermediate value bit separating means

The multi-channel cumulative integrator using the multi-step cumulative adder of the pipeline structure according to the present invention for achieving the above object is a cumulative integrator used to implement a signal synchronization acquisition device of the CDMA system, and the corresponding signal among the multi-channel multi-signal inputs Input signal multiplexing means for selecting, multiplexing, and separating bit by bit; Multi-step of the pipeline structure in which the input signal multiplexed by the input signal multiplexing unit and the signal fed back are added bit by bit, and the bit-by-bit adding means is provided in multiple stages so as to transfer the generated carry to the next stage. Adding means; Output means for combining and accumulating the accumulated signals separated by bits from the multi-step addition means for each bit digit; If the result of one cumulative addition value does not accumulate by the cumulative integral length, it is composed of feedback means for demultiplexing and feeding back to the multi-step adding means to accumulate as much data as desired. It is characterized by calculating the integral value.

The present invention increases the operation speed by using the pipeline technique of the accumulator adder used in the cumulative integrator. With this cumulative integrator, one can use the cumulative integrator hardware and some additional circuitry to calculate the cumulative integration over multiple channels of signals using a time division method.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a signal acquisition apparatus having a multi-channel cumulative integrator according to the present invention. As shown, the signal acquisition apparatus includes two blocks, a block 110 for calculating the cumulative integral value for the in-phase channel and a block 120 for calculating the cumulative integral value for the orthogonal channel. Each block is described simultaneously. The signal input to each block is a signal obtained by converting an RF signal received from a base station into an intermediate frequency band IF. The input signal is multiplied by the cosine value cos (wct) in the in-phase channel (111), and multiplied by the sine value sin (wct) in the orthogonal channel (121). In this way, the analog signal calculated by multiplying each channel by an appropriate value is converted into digital signals 111 and 121 using the A / D converter 112. The in-phase channel signal is multiplied by the in-phase channel pseudo noise (PN) code (113), and the orthogonal channel signal is multiplied by the orthogonal channel PN code (114) and summed (115). The signal which has undergone the above process is accumulated and accumulated by the signal of the specified length in the cumulative integrator 116 to which the present invention is applied. The processing of the orthogonal channel signal is performed by multiplying the signal passed through the A / D converter 122 by the inverse inverse channel PN code (123) and adding the inverse channel signal by the orthogonal channel PN code (124) to (125). The cumulative integral value is calculated using the cumulative integrator 126.

2 is a block diagram of a multi-channel cumulative integrator using a multi-step adder having a pipeline structure. As shown, input signal multiplexing means (200,201, 202) for selecting and multiplexing the corresponding signal among the multiple signal inputs of the multi-channel and separating by bit unit is provided, and the input multiplexed by bit by the input signal multiplexing means (200,201,202) The multi-step addition means 210, 220, 230 of a pipeline structure is provided with a multi-stage addition means for adding the signal and the signal fed back bit by bit and transferring the generated carry to the next stage, and adding the multi-step addition means. Output means (203, 304) are provided for combining and accumulating the accumulated signals separated by bits from the means (210, 220, 230) by bit digits, and demultiplexing when the result of one cumulative addition value is not accumulated by the cumulative integral length. Feedback is added to the step adding means to accumulate as much data as desired. A feedback means (205,206,207,208,209) is provided.

The input signal multiplexing means (200, 201, 202) is a multiplexing means for selecting only one channel signal at a time of the multiple signal input of the multi-channel and the code for sign-extending the input signal selected through the multiplexing means 200 to M bits Expansion means 201 and an input signal bit separation means 202 for separating the signal extended by the M bits bit by bit.

Bit-wise addition means (210, 220, 230) of the multi-step addition means is an adder (211, 235,) for receiving the N-th bit data input from the input signal separation means and the N-th accumulated intermediate value bit data fed back; Storage means 212, 213, 231, 232, 233, 234 for storing the output data of the adder so as to synchronize the output of the bit data.

The output means includes a bit combining means 203 which combines the output bit data of the multi-step adding means 210, 220, 230 by the number of digits and combines them so as to form a complete addition result, and the result of the combined cumulative addition value is accumulated. A cumulative value is output when accumulated by the integral length, and a switching means 204 for feeding back to the multi-step adding means.

The feedback means receives the bit-combined data fed back from the bit combining means 203, demultiplexes the demultiplexing means 205, and memory means 206 and 207 to receive the demultiplexed data and store the accumulated intermediate value. A multiplexing means 208 for receiving and accumulating the accumulated intermediate value stored in the storage means, and a cumulative intermediate value bit separating means for separating the multiplexed cumulative intermediate value by bit digits to input the multiply accumulating intermediate value into the multi-step addition means 210,220,230. 209 is provided.

The signal input to the multi-channel cumulative integrator is K channels. In this K channel input signal, only one channel signal is input to the code extension means 201 by the multiplexing means 200 at a time. The signal input to the sign expansion means is sign extended to M bits and input to the bit separation means 202. The role of the bit separation means is input by dividing the signal extended by M bits into the appropriate bits to the L branches 210, 220, 230 of the multi-step adder. In the operation of the adder means 1, the N1-bit data input from the input signal separation means 202 and the N1-bit data of the output of the accumulated intermediate value bit separation means 209 are added in the adder means 211. At this time, the carry generated in the adder means 211 of the adder branch 1 210 is transferred to the adder branch 2 220 and added by the adder means of the adder branch 2 220. The output of the adder means 211 of the adder branch 1 210 is stored by the storage means so as to be kept synchronized with the output of the other adder branch and then output. In other words, if the total number of adder branches is L, the output of the adder means of the first adder branch must be output after the L-1 step is delayed by the L-1 storage means, and the output of the remaining L-1 adder branches is kept in sync. do. The operation of the L-th adder branch 230 delays the NL bit output of the input signal bit separating means by L-1 steps using the storage means 231 and 233 and simultaneously stores the output of the NL bit of the cumulative intermediate value bit separating means. The L-1 step is delayed using the means 232,234. The delayed input data and the output value of the intermediate value storing means are added using the adder means 235 and then output 203 to the bit combining means. In the bit combining means, the outputs of each adder branch are sorted by the number of digits and combined so as to produce one complete addition result. If the result of one cumulative addition value combined in this way is not accumulated by the cumulative integration length, it is stored by the demultiplexing means 205 in its cumulative intermediate value storage means 206 and 207. If the cumulative integral length of the cumulative adder accumulates as much data as desired, it is switched to the output by the switch means 204. At this time, the contents of the accumulated intermediate value storing means are all initialized to the value of '0'.

According to the present invention, a cumulative integrator using a multi-step cumulative adder having a pipeline structure is used when implementing the cumulative integrator used in the accumulator. This high-speed cumulative integrator can calculate the cumulative integral value for signals of multiple channels with one cumulative integrator, thereby saving hardware resources in implementing the cumulative integrator device.

Claims (5)

In the cumulative integrator used to implement the signal synchronization acquisition device of the CDMA system, Input signal multiplexing means for selecting and multiplexing a corresponding signal among the multiple signal inputs of the multi-channels and separating the signals in bit units; The multi-step of the pipeline structure in which the input signal multiplexed by the input signal multiplexing means and the signal fed back are added bit by bit, and the bit-by-bit addition means is provided in multiple stages so as to transfer the generated carry to the next stage. Adding means; Output means for combining and accumulating the accumulated signals separated by bits from the multi-step addition means for each bit digit; When the result of one cumulative addition value is not accumulated by the cumulative integral length, it is composed of feedback means to accumulate as much data as desired by adding back by multiplexing and feeding back to the multi-step addition means. A multi-channel cumulative integrator using a multi-step cumulative adder having a pipelined structure, characterized by calculating a cumulative integral value for a multi-channel signal. The method of claim 1, The input signal multiplexing means, Multiplexing means for selecting only one channel signal at a time among the multiple signal inputs of the multi-channel; Code extending means for sign-extending the input signal selected by the multiplexing means into M bits; The multi-channel cumulative integrator using a pipelined multi-step cumulative adder, characterized in that the input signal bit separating means for separating the signal extended by the M bit by bit. The method of claim 1, Bit-wise addition means of the multi-step addition means, An adder for receiving and adding the N-th bit data input from the input signal separating means and the N-th accumulated intermediate value bit data fed back; A multi-channel cumulative integrator using a pipelined multi-step cumulative adder, characterized in that it comprises storage means for storing the output data of the adder to match the output synchronization of all the bit data. The method of claim 1, The output means, Bit combining means for arranging the output bit data of the multi-step adding means by the number of digits so as to form one complete addition result; If the result of the combined cumulative addition value accumulates by the cumulative integral length, the cumulative value is output. Otherwise, the multi-step accumulation of the pipeline structure comprises a switching means for feeding back the multi-step adding means. Multichannel cumulative integrator with adder. The method of claim 1, The feedback means, Demultiplexing means for receiving the bit-combined data fed back from the output means; Storage means for receiving the demultiplexed data and storing it as a cumulative intermediate value; Multiplexing means for receiving and accumulating the accumulated intermediate values stored in the storage means; A multi-channel cumulative integrator using a multi-step cumulative adder having a pipelined structure, characterized in that it comprises a cumulative intermediate value bit separating means for dividing the multiplexed cumulative intermediate value into the multi-step adding means by bit digits.

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