KR100204163B1 - Manufacture of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that can be easily and inexpensively manufactured. The present invention relates to an insulating sheet 38 having a metal layer 40a adhered to one surface on a semiconductor chip 32 on which an inactive film 34 is formed. ), A step of drilling a portion of the metal layer 40a corresponding to the electrode 36 of the semiconductor chip 32, and a hole of the metal layer 40a formed by the drilling. Drilling to expose the insulating sheet 38 at the portion corresponding to 40b) and exposing the electrode 36, and connecting to form an electrical connection between the electrode 36 and the metal layer 40a through a hole formed by the drilling. The step of forming the metal layer 40a in the required wiring pattern 40, and exposing the external connection terminal joining portion 43 of the wiring pattern 40 to expose the insulating film 42 on the insulating sheet 38. Forming and bonding the external connection terminal to the exposed external connection terminal It characterized in that it comprises.

Description

Manufacturing Method of Semiconductor Device

1 is a partial cross-sectional view of a semiconductor device.

2 is a partial cross-sectional view of a state in which the insulating sheet is thermally compressed.

3 is a partial cross-sectional view of the metal layer in a perforated state.

4 is a partial sectional view of a state in which the insulation sheet is punched out.

5 is a partial sectional view of a state in which a plating film is formed.

6 is a partial sectional view of a state in which a wiring pattern is formed.

7 is a partial cross-sectional view of an insulating film formed state.

8 is an explanatory diagram showing an example of arrangement of solder bumps.

9 is a partial cross-sectional view of a metal layer deposited on the passivation film and a photosensitive resist applied thereon.

10 is a partial sectional view of a state in which an ultraviolet shielding layer is installed.

11 is a partial cross-sectional view of a state in which the insulating sheet is thermally compressed.

12 is a partial cross-sectional view of the metal layer in a perforated state.

13 is a partial cross-sectional view of a state in which the insulation sheet is punched out.

14 is a partial sectional view of a state where a plating film is formed.

Fig. 15 is a partial sectional view of a state in which a wiring pattern is formed.

FIG. 16 is an explanatory diagram showing a state in which ultraviolet rays are irradiated to a negative photosensitive resist. FIG.

17 is a partial cross-sectional view of a state where an external connection terminal junction is formed.

18 is a partial cross-sectional view with a solder ball attached.

19 is an explanatory diagram showing a state in which ultraviolet rays are irradiated to a positive photosensitive resist.

20 is a partial sectional view of a state in which a metal layer is provided on the surfaces of an insulating sheet and a wiring pattern.

21 is a partial cross-sectional view of a state in which lands are provided on the surface of the insulating sheet.

Fig. 22 is a partial sectional view of a state in which external connection terminals are bonded to lands;

23 is a cross-sectional view showing an example of a conventional semiconductor device.

* Explanation of symbols for main parts of the drawings

30 semiconductor device 31 semiconductor chip

34: passivation film 36: Al pad

38: insulating sheet 40: wiring pattern

40a: metal layer 42: insulating film

43: external connection terminal junction 44: punched hole

46: external connection terminal 48: protective film

50: UV shielding layer 50a: metal layer

51 photosensitive resist 54 storage hole

58: metal layer 60: land

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, which can easily manufacture semiconductor devices having almost the same dimensions as semiconductor chips such as LSI chips.

There is a strong demand for miniaturization in order to increase the mounting density of semiconductor devices on which semiconductor chips are mounted.

The miniaturization of such a semiconductor device leads to the miniaturization of a package encapsulating a semiconductor chip.

In order to satisfy the above requirements, a chip size package, that is, a CSP (chip size package or chip scale package) has recently emerged.

There are several types of CSP types, but an example thereof is shown in FIG.

Where 10 is a semiconductor chip and 12 is a ceramic substrate. The ceramic substrate 12 is formed in substantially the same size as the semiconductor chip 10. A wiring pattern 14 for inputting or outputting a signal is formed on the ceramic substrate 10, and the wiring pattern 14 passes through a through hole 16 to form a land on a lower surface side of the ceramic substrate 12 in a required arrangement. Connection portion 18 of an external connection terminal).

The electrode of the semiconductor chip 10 is connected to the wiring pattern 14 via the Au bumps 20 and the AgPd paste 22, and a resin 24 is formed in the gap between the semiconductor chip 10 and the ceramic substrate 12. It is sealed.

According to the semiconductor device, miniaturization can be achieved. However, since the ceramic substrate 10 and the Au bump 20 are used, the semiconductor device is not only expensive but also requires a large number of parts, such as the manufacture of the ceramic substrate 10 separately. There is a problem that manufacturing is cumbersome.

Accordingly, the present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device which can be manufactured easily and at low cost.

The present invention has the following configuration in order to achieve the above object.

That is, the step of fixing the other surface of the insulating sheet on which the metal layer is formed on one surface on the semiconductor chip on which the passivation film is formed, the step of punching the portion of the metal layer corresponding to the electrode of the semiconductor chip, and the punching processing Exposing the electrode by punching the insulating sheet at a portion corresponding to the hole of the formed metal layer, electrically connecting the electrode and the metal layer through the hole formed by the punching process, and the metal layer. Forming an insulating film on the insulating sheet by exposing the external connection terminal junction of the wiring pattern, and bonding the external connection terminal to the exposed external connection terminal junction. Characterized in that.

A UV shielding layer for protecting the circuit surface of the semiconductor chip from ultraviolet rays is provided on the semiconductor chip on which the passivation film is formed, and the portion of the UV shielding layer corresponding to the electrode of the semiconductor chip is drilled to obtain another insulating sheet on the semiconductor chip. By sticking one side, the semiconductor chip can be protected from ultraviolet rays used in the photolithography step.

The step of punching the insulating sheet is an etching process for etching the insulating sheet.

In addition, the step of punching the portion of the metal layer corresponding to the electrode of the semiconductor chip and the step of forming the metal layer into required wiring patterns are performed by etching.

In addition, the step of electrically connecting the electrode and the metal layer via a hole formed by the punching processing is a plating step of forming a plating film on the hole and the electrode.

The step of forming the insulating film is a photolithography step of applying a photosensitive resist on the insulating sheet, exposing and developing the photosensitive resist film to expose an external connection terminal junction.

As the ultraviolet shielding layer, a Cr metal layer can be preferably used.

A semiconductor device capable of forming a thin insulating sheet and an insulating film serving as an interposer (intermediate), and the insulating sheet and the insulating film act as buffer layers of the semiconductor chip, thereby relieving stress generated between the semiconductor chip and the mounting substrate. Can be easily provided at low cost.

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail according to an accompanying drawing.

1 shows a cross-sectional view of the manufactured semiconductor device 30.

32 is a semiconductor chip, 34 is a passivation film made of SiO ₂ or the like covering the surface of the semiconductor chip 32, and 36 is an Al pad (electrode) which is a terminal manufactured in the semiconductor chip 32. The passivation film 34 is not formed in the Al pad 36, and the Al pad 36 is exposed to the surface of the semiconductor chip 32. A plurality of Al pads 36 are formed on the semiconductor chip 32 in a required pattern.

38 is an insulating sheet made of acrylic resin or the like, and is thermally compressed on the semiconductor chip 32 by covering the passivation film 34 of the semiconductor chip 32. A perforation hole 39 is formed in a portion of the insulating sheet 38 corresponding to the Al pad 36, and the Al pad 36 is exposed.

40 is a wiring pattern, and is electrically connected to the Al pad 36 via the perforation hole 39, the inner periphery wall surface of the passivation film 34 and the plating film 41 formed on the Al pad 36, and the insulating sheet. It is formed on the 38 at the required pattern.

The wiring pattern 40 is formed in a required pattern by etching a metal layer to be formed on the insulating sheet 38 as described later.

Further, the electrical connection between the wiring pattern 40 and the Al pad 36 may be performed by filling the conductive paste in the punched hole 39 (not shown).

42 covers an insulating sheet 38 and a wiring pattern 40 with an insulating film.

The insulating film 42 may be formed using various materials, for example, a photosensitive solder resist, as the protective film of the wiring pattern 40.

In the appropriate part corresponding to each wiring pattern 40 of the insulating film 42, the perforation hole 44 is formed in the insulating film 42 so that it may become matrix form (for the perforation hole 44), for example. Part of the wiring pattern 40 exposed by the external connection terminal junction portion 43).

46 is an external connection terminal, which is arranged in electrical connection with each external connection terminal joining portion 43 through each of the perforation holes 44, and protrudes on the insulating film 42.

The external connection terminal 46 may be formed in a ball shape as shown, but may be formed in a flat land shape or other shape.

48 is a protective film that covers and protects the sidewalls of the semiconductor chip 32, the passivation film 34, and the insulating sheet 38, and prevents moisture from entering the boundary of each layer. The protective film 48 may be formed using a resin of a suitable material, but is not necessarily provided. Instead of the protective film 48, a frame made of metal or the like may be fixed (not shown).

Since it is formed as mentioned above, the semiconductor device 30 of the same size as the semiconductor chip 32 can be formed.

In addition, since the insulating sheet 38 and the insulating film 42 serving as the interposer can be formed thinly, the thin semiconductor device 30 can be formed.

Since the insulating sheet 38 and the insulating film 42 are not so high in hardness, they also function as a buffer layer for protecting the surface of the semiconductor chip 32.

In addition, the surface opposite the semiconductor chip 32 may be exposed to increase heat dissipation. In addition, in order to improve heat dissipation, the heat sink may be fixed (not shown).

2 to 7 show a manufacturing process for manufacturing the semiconductor device 30 shown in FIG.

First, as shown in FIG. 2, the other surface of the insulating sheet 38 having the same metal layer 40a formed on one surface by adhesion or physical vapor deposition is formed on the surface of the semiconductor chip 32 with the passivation film 34 formed thereon. The thermocompression bonding is performed to cover the Al pad 36.

Next, a resist is applied on the metal layer 40a, patterned by a known photolithography process, and then etched to form holes 40b in the metal layer 40a at the portion corresponding to the Al pad 36. Drilling is performed (see FIG. 3).

Subsequently, as shown in FIG. 4, the metal layer 40a is etched with a mask, and punched through the insulating sheet 38 corresponding to the hole 40b to form a punched hole 39. FIG. The Al pad 36 is exposed to the drilling hole.

Next, a resist is applied on the metal layer 40a, and the same electrolysis or electroless plating is performed on the inner circumferential wall surface of the hole 40b, the hole 39 and the passivation hole of the passivation film 34, and the Al pad 36. To form a plating film 41 (see FIG. 5). The film 41 can also be formed by physical vapor deposition means (sputtering or the like).

Further, a resist is applied on the metal layer 40a, the wiring pattern is patterned by a photolithography process, and then the metal layer 40a is etched to form the wiring pattern 40 (see FIG. 6).

Subsequently, a photosensitive resist is applied on the insulating sheet 38 to cover the wiring pattern 40 to form the insulating film 42, and a wiring pattern covered with the photosensitive resist film by performing exposure development by a photolithography process. The photosensitive resist film in the portion corresponding to the external connection terminal joining portion 43 in 40 is removed to expose the wiring pattern 40 in this portion (see FIG. 7).

The solder ball (external connection terminal) 46 is disposed in the exposed external connection terminal joining portion 43 and reflowed to fix the solder ball 46 on the wiring pattern 40. As the external connection terminal, a lead pin may be fixed to the joint 43 in addition to the solder ball (not shown).

If necessary, a resist can be applied to the sidewall of the semiconductor device 30 and dried to form a protective film 48.

As described above, the semiconductor device 30 shown in FIG. 1 can be completed.

8 is an explanatory diagram showing an arrangement example of the external connection terminal 46. As shown in FIG.

In addition, the punching process shown in FIG. 3 and the formation of the wiring pattern shown in FIG. 6 can be made into the same etching process. After this process, the process shown in FIG. 4 and FIG. 5 is performed.

In the process of FIG. 5, the conductive paste may be filled in the hole 39 without plating, so that the metal layer 40a or the wiring pattern 40 and the Al pad 36 may be electrically connected.

9 to 19 show another embodiment of a method of manufacturing a semiconductor device. This embodiment is characterized in that the circuit formed on the semiconductor chip is not damaged by ultraviolet irradiation in the photolithography step, particularly when the insulating film 42 is formed using a negative photosensitive resist.

9 and 10 are ultraviolet rays for shielding ultraviolet rays used as an exposure light source in a photolithography step before thermocompression bonding the insulating sheet 38 to the surface of the semiconductor chip 32 in the characteristic step of this embodiment. The process of installing the shielding layer 50 is shown.

The ultraviolet shielding layer 50 is formed in the range except the Al pad 36 on the passivation film 34 as shown in FIG. 10 to protect the range in which the circuit is formed on the semiconductor chip 32 from ultraviolet rays. do.

In order to form the ultraviolet shielding layer 50, as shown in FIG. 9, the metal layer 50a is first deposited on the semiconductor chip 32 inactive film 34 by sputtering or vapor deposition, or the like. 51). In the case where the photosensitive resist 51 is negative, exposure is performed by shielding a portion corresponding to the Al pad 36, and removing the photosensitive resist 51 of the portion corresponding to the Al pad 36 to remove the metal layer 50a. By exposing and etching the metal layer 50a, the ultraviolet shielding layer 50 is formed on the passivation film 34 (see FIG. 10).

In the case of using the positive type as the photosensitive resist 51, the exposure range is reversed from the case of using the negative type.

In the above photolithography process, ultraviolet light is used for exposure of the photosensitive resist 51. However, during exposure by the ultraviolet light, the metal layer 50a is deposited on the entire surface of the passivation film 34 as a base layer of the photosensitive resist 51. As a result, regardless of whether the photosensitive resist 51 is negative or positive, ultraviolet rays are shielded by the metal layer 50a, thereby preventing damage to the semiconductor chip 32 circuit.

As a metal used for the ultraviolet shielding layer 50, Cr can be used preferably, and ultraviolet-ray can be shielded enough by the thickness of about 0.1 micrometer. In addition, a Cu metal layer can be used instead of the Cr metal layer. In addition, the ultraviolet shielding layer 50 can be formed in a plurality of laminated structures like the Cr metal layer, the Ni metal layer, and the Cu metal layer.

The manufacturing process after FIG. 11 is the same as the process mentioned above. That is, after the ultraviolet shielding layer 50 is formed, the insulating sheet 38 on which the metal layer 40a is deposited is formed on the surface of the semiconductor chip 32 (see FIG. 11).

Next, a photosensitive resist is applied to the surface of the metal layer 40a, a resist pattern is formed by a photolithography process, and the metal layer 40a is etched to form a hole 40b (Fig. 12). . In this photolithography step, ultraviolet rays are exposed to the photosensitive resist coated on the surface of the metal layer 40a. However, since the surface of the insulating sheet 38 is covered with the metal layer 40a, the photosensitive resist is also negative in this step. Irrespective of the type, the damage to the semiconductor chip 32 can be prevented.

Subsequently, the insulating sheet 38 is etched using the metal layer 40a having the holes 40b formed thereon as a mask, and the punched holes 39 are formed in the insulating sheet 38 corresponding to the holes 40b (Thirteenth Step). See also).

Next, the plating film 41 is formed by electroless copper plating and electrolytic copper plating on the inner circumferential wall surface of the hole 40b, the hole hole 39 and the hole of the passivation film 34 and the Al pad 36. (See Figure 14.)

Next, in order to form the wiring pattern 40 by etching the metal layer 40a, a photosensitive resist is coated on the surface of the metal layer 40a, and the photosensitive resist is exposed and developed by a photolithography process as described above. The resist pattern is formed, and the metal layer 40a is etched to form the wiring pattern 40 (see Fig. 15). In the photolithography step, when the photosensitive resist is exposed to ultraviolet rays, the underlying layer of the photosensitive resist is completely covered by the metal layer 40a and the plating film 41, so that the circuit of the semiconductor chip 32 is not damaged.

After the wiring pattern 40 is formed as described above, in order to form a junction portion for joining the wiring pattern 40 and the external connection terminal, the insulating pattern 38 is covered on the insulating sheet 38 to cover the wiring pattern 40. The photosensitive resist 42a which becomes 42 is apply | coated, the photosensitive resist 42a is exposed and developed, and the external connection terminal junction part 43 of the wiring pattern 40 is exposed.

FIG. 16 is a state in which the portions corresponding to the external connection terminal junctions 43 are shielded and then exposed. FIG. 17 is an exposure and development of the photosensitive resist, and the insulating film 42 is perforated to allow the external connection terminal junctions 43 to be exposed. Indicates an exposed state.

FIG. 16 shows a case where a negative photosensitive resist is used as the photosensitive resist for forming the insulating film 42. As shown in FIG. In the negative photosensitive resist, the part to which light does not reach is melt | dissolved by the developing solution. Therefore, when exposing, the part corresponding to the external connection terminal junction part 43 is shielded with a mask and irradiated with ultraviolet rays.

The above-mentioned ultraviolet shielding layer 50 is effective because it does not damage the circuit of the semiconductor chip 32 at the time of said ultraviolet irradiation. That is, in the photolithography process, when there is no ultraviolet shielding layer 50, there is no layer shielding ultraviolet rays between the patterns of the wiring pattern 40 when the ultraviolet rays are irradiated. Thus, the photosensitive resist, the insulating sheet 38, and the passivation layer 34 ) Is transmitted through ultraviolet rays, and ultraviolet rays are incident on the surface of the semiconductor chip 32 to damage the circuit.

In the above photolithography process, when irradiating the photosensitive resist with ultraviolet rays, the metal layer covers the irradiation surface of light as a base layer in the entire range. In this photolithography process, since the wiring pattern 40 is formed, the ultraviolet ray transmission is performed. There is a problem that the circuit of the semiconductor chip 32 is damaged.

19 shows the exposure method by ultraviolet rays in the case of using a positive resist as the photosensitive resist for forming the insulating film 42. FIG. In the case of the positive type, since the part where ultraviolet rays reach is melt | dissolved with a developing solution, it shields with a mask and irradiates an ultraviolet-ray except the site | part which exposes the external connection terminal junction part 43 as shown in figure. The external connection terminal junction portion 43 as shown in FIG. 17 is formed by developing after exposure.

In the case of using the positive photosensitive resist as described above, the ultraviolet light only needs to be irradiated to the exposed portion of the external connection terminal joining portion 43. Since the external connection terminal junction 43 is provided in a range in which the wiring pattern 40 is formed, when using a positive photosensitive resist, the irradiation range of ultraviolet rays is limited to a range in which the wiring pattern 40 is formed. can do. In other words, in the case of using a positive photosensitive resist, ultraviolet light may be irradiated within a range in which the wiring pattern 40 is formed as the base layer. Thus, the ultraviolet ray is shielded by the wiring pattern 40, and the ultraviolet shielding layer 50 is formed. Even if it is not equipped, the damage of the circuit of the semiconductor chip 32 can be prevented.

As described above, the external connection terminal junction 43 is exposed from the insulating film 42, the solder ball (external connection terminal) 46 is disposed on the exposed external connection terminal junction 43, and reflowed to solder The ball 46 is fixed on the wiring pattern 40 to obtain a semiconductor device (see FIG. 18). Then, a resist is applied and dried on the sidewall of the semiconductor device 30 as needed, and the protective film 48 is formed to complete the semiconductor device 30 shown in FIG.

The semiconductor device manufacturing method shown in FIGS. 9 to 19 described above is provided with the ultraviolet shielding layer 50 on the passivation film 34, in particular, when the photolithography process is performed using a negative photosensitive resist. It is effective in manufacturing a semiconductor device, preferably, without damaging the circuit.

20 to 22 show the accommodating holes 54 of the insulating film 42 for joining the external connection terminals 46 to ensure that the external connection terminals 46 can be connected to the external connection terminal junctions 43. A method of forming a land around the inner surface and the receiving opening 54 is shown.

20 is a state in which a metal layer 58 such as a copper layer is formed on the surface of the insulating film 42 and the inner surface of the storage hole 54 by the sputtering method or the vapor deposition method in the state where the storage hole 54 shown in FIG. 17 is formed. It is shown.

Next, a photosensitive resist is applied to the surface of the metal layer 58, the photosensitive resist is left inside the storage hole 54 and the periphery of the storage hole 54 by a photolithography process, and the metal layer 58 is etched. The land 60 is formed (see FIG. 21).

The land 60 is electrically connected to the external terminal joining portion 43 at the bottom thereof, and the inner surface and the circumference of the housing hole 54 are covered with a metal layer.

22 shows a state in which the external connection terminal 46 is bonded to the land 60. In the example shown in FIG. 18, the external connection terminal 46 is connected to the external terminal junction portion 60 of the wiring pattern 40 at the bottom thereof. In this example, the external connection terminal 46 is connected via the land 60. Since the external connection terminal 46 is also securely bonded to the inner surface of the receiving hole 54, the external connection terminal 46 can be more securely bonded to the semiconductor chip 32.

In the above embodiment, the semiconductor chip 32 which has been reorganized has been described. However, the insulating sheet 38 and the wiring pattern are formed on the wafer as described above using a wafer in which a plurality of semiconductor chips 32 are manufactured. 40, the insulating film 42, and the external connection terminal 46 are fabricated and then sliced and separated into pieces, whereby a plurality of semiconductor devices 30 can be formed at once, thereby reducing costs. Can be.

According to the method of manufacturing a semiconductor device according to the present invention, as described above, since it can be mainly manufactured by an etching process, a photolithography process, etc., a small and lightweight semiconductor device can be easily manufactured at low cost. In addition, a semiconductor device can be manufactured without damaging the semiconductor chip by providing an ultraviolet shielding layer on the circuit surface of the semiconductor chip and exposing it.

Claims (7)

Fixing the other surface of the insulating sheet having a metal layer on one surface on the semiconductor chip on which the passivation film is formed, drilling a portion of the metal layer corresponding to an electrode of the semiconductor chip, and metal layer formed by the drilling Drilling the insulating sheet at a portion corresponding to the hole of the hole to expose the electrode; electrically connecting the electrode and the metal layer through the hole formed by the drilling; Forming an insulating film on the insulating sheet by exposing the external connection terminal junction of the wiring pattern; and bonding the external connection terminal to the exposed external connection terminal junction. A method of manufacturing a semiconductor device, characterized in that. The semiconductor chip according to claim 1, wherein an ultraviolet shielding layer for protecting the circuit surface of the semiconductor chip from ultraviolet rays is provided on the semiconductor chip on which the passivation film is formed, and the portion of the ultraviolet shielding layer corresponding to the electrode of the semiconductor chip is drilled. A method of manufacturing a semiconductor device, characterized in that the other side of the insulating sheet is fixed to the substrate. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the step of natural processing the insulating sheet is an etching step of etching the insulating sheet. The etching process according to any one of claims 1 to 3, wherein the step of punching a portion of the metal layer corresponding to the electrode of the semiconductor chip and the step of forming the metal layer into a required wiring pattern are performed by etching. Method of manufacturing a semiconductor device. The process of any one of claims 1 to 4, wherein the step of electrically connecting the electrode and the metal layer via a hole formed by the drilling is a plating step of forming a plating film on the hole and the electrode. Method of manufacturing a semiconductor device. The photolithography process according to any one of claims 1 to 5, wherein the step of forming the insulating film includes applying a photosensitive resist on the insulating sheet, exposing and developing the photosensitive resist film to expose an external connection terminal junction. The semiconductor device manufacturing method characterized by the above-mentioned. The semiconductor device manufacturing method according to any one of claims 1 to 6, wherein a Cr metal layer is used as the ultraviolet shielding layer.