KR0172290B1 - Method of manufacturing mos transistor - Google Patents
Method of manufacturing mos transistor Download PDFInfo
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- KR0172290B1 KR0172290B1 KR1019950003739A KR19950003739A KR0172290B1 KR 0172290 B1 KR0172290 B1 KR 0172290B1 KR 1019950003739 A KR1019950003739 A KR 1019950003739A KR 19950003739 A KR19950003739 A KR 19950003739A KR 0172290 B1 KR0172290 B1 KR 0172290B1
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- forming
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- polysilicon film
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- semiconductor substrate
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910003849 O-Si Inorganic materials 0.000 claims description 2
- 229910003872 O—Si Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000006227 byproduct Substances 0.000 claims 1
- 229910052723 transition metal Inorganic materials 0.000 abstract description 7
- 150000003624 transition metals Chemical class 0.000 abstract description 7
- 230000035515 penetration Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 150000002736 metal compounds Chemical class 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자 제조공정 중 게이트 전극 형성방법에 있어서, 반도체기판(110 상부에 게이트 절연층(13), 전도층(14), 진성 폴리실리콘층(15)을 차례로 형성하는 제1단계; 상기 진성 폴리실리콘층(15), 전도층(14), 게이트 절연층(13)을 소정 패턴으로 패터닝하는 제2단계; 노출된 상기 진성 폴리실리콘층(150 상에 전이금속층을 형성한 후, 열처리하는 제3단계; 및 전체구조 표면에 산화층(21)을 형성하는 제4단계를 포함하는 것을 특징으로 하여, 금속 화합물의 침투에 의한 게이트 절연용(13)의 막질 저하를 방지하고, 전이금속의 선택성을 향상 시켜 소자의 전기적 특성, 특히 신뢰성을 향상시킬 수 있는 특유의 효과가 있는 게이트 전극 형성방법에 관한 것이다.In the gate electrode forming method of the semiconductor device manufacturing process, the first step of sequentially forming a gate insulating layer 13, a conductive layer 14, an intrinsic polysilicon layer 15 on the semiconductor substrate 110; Patterning the intrinsic polysilicon layer 15, the conductive layer 14, and the gate insulating layer 13 in a predetermined pattern; forming a transition metal layer on the exposed intrinsic polysilicon layer 150, and then performing heat treatment And a fourth step of forming the oxide layer 21 on the surface of the entire structure, thereby preventing the film quality of the gate insulation 13 from being penetrated by the penetration of the metal compound, and selecting the transition metal. The present invention relates to a method for forming a gate electrode having a unique effect of improving the electrical properties of the device, particularly the reliability thereof.
Description
제1도는 종래기술에 따른 MOS 트랜지스터의 단면도.1 is a cross-sectional view of a MOS transistor according to the prior art.
제2a도 내지 제2e도는 본 발명에 따른 MOS 트랜지스터의 형성 공정도.2A to 2E are process charts for forming a MOS transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12 : 필드산화막11 silicon substrate 12 field oxide film
13 : 게이트산화막 14 : 도핑된 폴리실리콘막13 gate oxide film 14 doped polysilicon film
15 : 진성 폴리실리콘막 17 : 질화막스페이서15: intrinsic polysilicon film 17: nitride film spacer
18 : 산화막스페이서 20 : 티타늄실리사이드막18 oxide film spacer 20 titanium silicide film
21 : 열산화막21: thermal oxide film
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 모스트랜지스터(MOSFET) 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOSFET.
최근에 반도체 소자의 집적도가 점점 증가됨에 따라 상대적으로 저항이 작은 게이트 전극의 형성방법이 필요하게 되었다.Recently, as the degree of integration of semiconductor devices is gradually increased, a method of forming a gate electrode having a relatively low resistance is required.
이를 위하여 종래기술에 따라 형성한 MOSFET의 단면도가 제1도에 도시되어 있으며, 이를 참조하여 종래기술을 살펴본다.To this end, a cross-sectional view of a MOSFET formed in accordance with the prior art is shown in FIG. 1, with reference to which the prior art will be described.
제1도에 도시된 바와 같이 종래에는 실리콘기판(1) 상에 필드산화막(2)을 형성하고, 게이트산화막(3) 및 불순물이 도핑된 폴리실리콘막(4)을 증착한 후 게이트 패터닝한 후, 저농도이온주입, 산화막스페이서(5) 형성, 및 고농도이온주입을 통해 소스/드레인 영역(6)을 형성한다. 이어서, 노출된 실리콘기판(1)의 소스/드레인 영역(6) 및 폴리실리콘막(4) 상부에 전이금속막인 티타늄막을 선택증착한 후, 열처리 공정을 통해 티타늄실리사이드막(7)을 형성한다.As shown in FIG. 1, a field oxide film 2 is formed on a silicon substrate 1, a gate oxide film 3 and a polysilicon film 4 doped with impurities are deposited, and then gate patterned. Source / drain regions 6 are formed through low concentration ion implantation, oxide spacer 5 formation, and high concentration ion implantation. Subsequently, a titanium film, which is a transition metal film, is selectively deposited on the source / drain region 6 and the polysilicon film 4 of the exposed silicon substrate 1, and then a titanium silicide film 7 is formed through a heat treatment process. .
그러나, 이러한 종래기술에서, 상기 전이금속막이 실리사이드막으로 변환되는 과정에서 폴리실리콘막(4)의 실리콘 원자가 소모되며, 이때 생성된 화합물(전이금속이 티타늄인 경우 TiSix화합물)이 하부의 게이트산화막(3)으로 침투하기 때문에 게이트산화막(3)의 막질(Film quality)이 저하되어 소자의 전기적 특성, 특히 신뢰도를 감소 시키는 문제점이 발생한다.However, in this prior art, the silicon atoms of the polysilicon film 4 are consumed in the process of converting the transition metal film into the silicide film, and the resulting compound (TiSi x compound if the transition metal is titanium) is a gate oxide film underneath. As it penetrates into (3), the film quality of the gate oxide film 3 is lowered, which causes a problem of reducing the electrical characteristics of the device, particularly reliability.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 전기적 특성, 특히 신뢰성을 향상시키기 위한 MOSFET 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a MOSFET manufacturing method for improving electrical characteristics, particularly reliability.
상기 목적을 달성하기 위하여 본 발명의 MOSFET 제조방법은, 반도체기판 상부에 게이트절연막, 도핑된 폴리실리콘막 및 진성 폴리실리콘막을 차례로 증착하는 제1단계; 상기 진성 폴리실리콘막 및 상기 도핑된 폴리실리콘막을 선택적으로 식각하되 과소식각에 의해 상기 도핑된 폴리실리콘막의 일부두께를 잔류시키는 제2단계; 저농도불순물이온주입에 의해 반도체기판내에 소스/드레인의 저농도확산영역을 형성하는 제3단계; 상기 제2단계에 의해 형성된 패턴의 측벽에 질화막스페이서를 형성하고 이에 의해 노출되는 상기 잔류하는 도핑된 폴리실리콘막을 식각하는 제4단계; 상기 제4단계에 의해 형성된 패턴의 측벽에 산화막스페이서를 형성하고 이에 의해 노출되는 상기 게이트절연막을 식각하는 제5단계; 고농도불순물이온주입에 의해 상기 반도체기판내에 소스/드레인의 고농도확산영역을 형성하는 제6단계; 상기 반도체기판 표면 상에 그리고 상기 진성 폴리실리콘막 상에 금속실리사이드막을 형성하는 제7단계; 및 산소 분위기에서 고온 열처리하여 상기 제7단계가 완료된 기판 전면에 열산화막을 형성하는 제8단계를 포함하여 이루어진다.In order to achieve the above object, the MOSFET manufacturing method includes a first step of sequentially depositing a gate insulating film, a doped polysilicon film, and an intrinsic polysilicon film on a semiconductor substrate; Selectively etching the intrinsic polysilicon film and the doped polysilicon film, but leaving a partial thickness of the doped polysilicon film by underetching; Forming a low concentration diffusion region of the source / drain in the semiconductor substrate by low concentration impurity ion implantation; Forming a nitride film spacer on a sidewall of the pattern formed by the second step and etching the remaining doped polysilicon film exposed by the fourth step; A fifth step of forming an oxide film spacer on sidewalls of the pattern formed by the fourth step and etching the gate insulating film exposed thereby; A sixth step of forming a high concentration diffusion region of a source / drain in the semiconductor substrate by high concentration impurity ion implantation; A seventh step of forming a metal silicide film on the surface of the semiconductor substrate and on the intrinsic polysilicon film; And an eighth step of forming a thermal oxide film on the entire surface of the substrate on which the seventh step is completed by high temperature heat treatment in an oxygen atmosphere.
이할, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain in detail enough that a person having ordinary skill in the art to which the present invention pertains can easily carry out the technical idea of the present invention, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings. Shall be.
제2a도 내지 제2e도는 본 발명의 일실시예에 따른 MOSFET 제조방법을 나타내는 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of fabricating a MOSFET according to an embodiment of the present invention.
먼저 제2a도에 도시된 바와 같이 실리콘기판(11)상에 필드산화막(12)을 예정된 부위에 형성한 다음, 문턱전압 조절을 위한 불순물을 이온주입하고, 이어 게이트산화막(13), 불순물이 도핑된 폴리실리콘막(14)을 차례로 형성한다.First, as shown in FIG. 2A, the field oxide film 12 is formed on a predetermined region on the silicon substrate 11, and then ion implantation of impurities for controlling the threshold voltage is performed, followed by the gate oxide film 13 and doping of impurities. The formed polysilicon film 14 is sequentially formed.
이어서, 제2b도에 도시된 바와 같이 전체구조 상부에 저압화학기상증착(LPCVD)으로 진성 폴리실리콘막(15)을 형성한다.Subsequently, as shown in FIG. 2B, an intrinsic polysilicon film 15 is formed on the entire structure by low pressure chemical vapor deposition (LPCVD).
계속해서, 제2c도에 도시된 바와 같이 포토리소그래피(Photo-lithography) 공정에 의한 선택적 식각으로 진성 폴리실리콘막(15)과 도핑된 폴리실리콘막(14)을 식각하되, 도핑된 폴리실리콘막(14)이 소정두께 잔류하도록 과소식각을 한다. 이어 N-형 불순물인 인(P)을 이온주입하여 N-이온주입영역(16)을 형성한다.Subsequently, as shown in FIG. 2C, the intrinsic polysilicon film 15 and the doped polysilicon film 14 are etched by selective etching by a photolithography process, and the doped polysilicon film ( 14) Underetch so that the thickness remains. Subsequently, phosphorus (P), an N-type impurity, is ion-implanted to form the N - ion implantation region 16.
이어서, 제2d도에 도시된 바와 같이 식각되어 패터닝된 진성 폴리실리콘막(15)과 도핑된 폴리실리콘막(14)의 측벽에 질화막스페이서(17)를 형성한 다음, 일부두께 남겨진 도핑된 폴리실리콘막(14)을 식각한다. 상기 질화막스페이서(17)와 일부 측면이 노출된 도핑된 폴리실리콘막(14)의 측벽에 산화막스페이서(18)를 형성한 후, 불순물인 비소(As)를 이온주입하여 N+이온주입영역(19)을 형성한다. 이때, 노출된 게이트산화막(13)은 산화막스페이서(18) 형성시 동시에 식각된다.Subsequently, a nitride film spacer 17 is formed on sidewalls of the etched and patterned intrinsic polysilicon film 15 and the doped polysilicon film 14, as shown in FIG. 2D, and then the doped polysilicon remains partially thick. The film 14 is etched. After the oxide film spacer 18 is formed on the sidewalls of the nitride film spacer 17 and the doped polysilicon film 14 having some side surfaces exposed thereto, arsenic (As), which is an impurity, is implanted into the N + ion implantation region 19. ). At this time, the exposed gate oxide layer 13 is simultaneously etched when the oxide spacer 18 is formed.
계속해서, 제2e도에 도에 도시된 바와 같이 노출된 실리콘기판(11)과 진성 폴리실리콘막(15) 상부에 전이금속인 티타늄막을 선택증착한 후, 질소 가스를 사용한 고온 열처리를 수행하여 티타늄실리사이드막(20)을 형성한다. 이어 필드산화막(12)과 산화막스페이서(18) 표면에 형성된 불필요한 티타늄층을 황산과 과산화수소의 혼합액으로 제거한 후, 산소(O2) 분위기에서 고온 열처리하여 전체구조 표면에 열산화막(21)을 형성한다. 이때, 상기 열산화막(21) 형성을 위하여 수행되는 고온 열처리시 산소(O2)가 티타늄실리사이드막(20)과 진성 폴리실리콘막(15)의 계면에 유입되어 Ti-O-Si 형태의 TiSix화합물 침투를 방지하는 경계층을 형성하게 된다. 또한, 상기 산화막(21)은 티타늄실리사이드막(20)이 이후의 공정시 다른 가스와 반응하는 것을 억제한다.Subsequently, as shown in FIG. 2E, a titanium film, which is a transition metal, is selectively deposited on the exposed silicon substrate 11 and the intrinsic polysilicon film 15, and then a high temperature heat treatment using nitrogen gas is performed to perform titanium. The silicide film 20 is formed. Subsequently, the unnecessary titanium layer formed on the surfaces of the field oxide film 12 and the oxide film spacer 18 is removed with a mixture of sulfuric acid and hydrogen peroxide, and then thermally heated at high temperature in an oxygen (O 2 ) atmosphere to form a thermal oxide film 21 on the entire structure surface. . At this time, the high temperature heat treatment during the oxygen (O 2) is carried out for the thermal oxide film 21 is formed is introduced into the interface between the titanium silicide film 20 and an intrinsic polysilicon film (15) Ti-O-Si in the form of TiSi x It forms a boundary layer that prevents compound penetration. In addition, the oxide film 21 suppresses the titanium silicide film 20 from reacting with another gas in a subsequent process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.
상기와 같이 이루어지는 본 발명은 금속 화합물의 침투에 의한 게이트산화막의 막질 저하를 방지하고, 전이금속의 선택성을 향상시켜 소자의 전기적 특성, 특히 신뢰성을 향상시킬 수 있는 특유의 효과가 있다.The present invention as described above has a unique effect of preventing the film oxide degradation of the gate oxide film due to the penetration of the metal compound, improve the selectivity of the transition metal to improve the electrical properties of the device, in particular the reliability.
Claims (3)
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| KR1019950003739A KR0172290B1 (en) | 1995-02-24 | 1995-02-24 | Method of manufacturing mos transistor |
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| KR1019950003739A KR0172290B1 (en) | 1995-02-24 | 1995-02-24 | Method of manufacturing mos transistor |
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| KR960032652A KR960032652A (en) | 1996-09-17 |
| KR0172290B1 true KR0172290B1 (en) | 1999-03-30 |
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