KR100280798B1 - Transistor manufacturing method of semiconductor device - Google Patents
Transistor manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR100280798B1 KR100280798B1 KR1019940016115A KR19940016115A KR100280798B1 KR 100280798 B1 KR100280798 B1 KR 100280798B1 KR 1019940016115 A KR1019940016115 A KR 1019940016115A KR 19940016115 A KR19940016115 A KR 19940016115A KR 100280798 B1 KR100280798 B1 KR 100280798B1
- Authority
- KR
- South Korea
- Prior art keywords
- patterned
- concentration impurity
- film
- silicon substrate
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052723 transition metal Inorganic materials 0.000 claims description 6
- 150000003624 transition metals Chemical class 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 폴리 사이드(polycide)구조의 게이트 전극이 형성될 부위의 실리콘 기판을 돌출되게 하고, 소오스 및 드레인 영역에 포켓(pocket)이온 주입영역을 형성하여 MOSFET의 유효채널 길이를 증대시키면서 전기적 특성을 향상시킬 수 있는 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, wherein the silicon substrate is formed to protrude from a region where a polycide gate electrode is to be formed, and a pocket ion implantation region is formed in the source and drain regions to form a MOSFET. The present invention relates to a method for manufacturing a transistor of a semiconductor device capable of improving the electrical characteristics while increasing the effective channel length.
Description
제1도는 종래 반도체 소자의 트랜지스터 단면도.1 is a cross-sectional view of a transistor of a conventional semiconductor device.
제2a도 내지 제2f도는 본 발명에 의한 반도체 소자의 트랜지스터를 제조하는 단계를 도시한 소자의 단면도.2A to 2F are cross-sectional views of a device, showing the steps of manufacturing a transistor of the semiconductor device according to the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11 : 실리콘 기판 12 : 제 1 열산화막11 silicon substrate 12 first thermal oxide film
13 : 제 1 감광막 14 : 제 2 열산화막13 first photosensitive film 14 second thermal oxide film
15 : 저농도 불순물 영역 16 : 게이트 산화막15 low concentration impurity region 16 gate oxide film
17 : 폴리실리콘층 18 : 질화막 스페이서17 polysilicon layer 18 nitride film spacer
19 : 고농도 불순물 영역 20 : 제 2 감광막19 high concentration impurity region 20 second photosensitive film
21 : 포켓이온주입영역 22 : 실리사이드21: pocket ion implantation area 22: silicide
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 특히 폴리사이드(polycide)구조의 게이트 전극이 형성될 부위의 실리콘 기판을 돌출되게하고, 소오스 및 드레인 영역에 포켓(pocket)이온 주입영역을 형성하여 MOSFET의 유효채널 길이를 증대시키면서 전기적 특성을 향상시킬 수 있는 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, and in particular, to protrude a silicon substrate at a portion where a polycide gate electrode is to be formed, and to form a pocket ion implantation region in a source and a drain region. The present invention relates to a transistor manufacturing method of a semiconductor device capable of improving electrical characteristics while increasing an effective channel length of a MOSFET.
최근 반도체 소자의 고집적화 추세에 따라 자기정렬된 폴리사이드 구조를 갖는 게이트 전극을 트랜지스터에 주로 적용하고 있다.Recently, with the trend of high integration of semiconductor devices, gate electrodes having self-aligned polyside structures are mainly applied to transistors.
종래의 기술에 의해 제조된 폴리사이드 구조를 갖는 MOSFET를 제1도를 참조하여 설명하기로 한다.A MOSFET having a polyside structure manufactured by the prior art will be described with reference to FIG.
실리콘 기판(1)상에 게이트 산화막(2)을 형성하고, 그 상부에 폴리실리콘을 증착한 후 게이트 전극용 마스크를 이용하여 패턴화된 폴리실리콘(3)을 형성하고, 저농도 불순물 이온을 주입하여 저농도 불순물 영역(4)을 형성하고, 상기 패턴화된 폴리실리콘층(3)의 측벽에 산화막 스페이서(5)를 형성한 다음 고농도 불순물 이온을 주입하여 고농도 불순물 영역(6)을 형성하고, 선택증착법으로 저농도 및 고농도 불순물 영역(4 및 6)으로 된 소오스 /드레인 영역과 패턴화된 폴리실리콘층(3)에 실리사이드(7)를 형성한다.Forming a gate oxide film 2 on the silicon substrate 1, depositing polysilicon on the silicon substrate 1, forming a patterned polysilicon 3 using a gate electrode mask, and implanting low concentration impurity ions. A low concentration impurity region 4 is formed, an oxide spacer 5 is formed on the sidewall of the patterned polysilicon layer 3, and then a high concentration impurity ion is implanted to form a high concentration impurity region 6, and a selective deposition method. Thus, silicides 7 are formed in the source / drain regions of the low and high concentration impurity regions 4 and 6 and the patterned polysilicon layer 3.
상기와 같은 공정으로 형성된 MOSFET는 고집적화 됨에따라 채널길이가 짧아져서 문턱전압과 파괴전압의 감소와 기판전류 증가등으로 MOSFET의 전기적 특성이 악화되는 문제점이 발생한다.As the MOSFET formed by the above process is highly integrated, the channel length is shortened, resulting in a problem that the electrical characteristics of the MOSFET are deteriorated due to a decrease in threshold voltage, breakdown voltage, and increase in substrate current.
따라서, 본 발명은 제한된 면적하에서 유효채널 길이를 증대시키면서 전기적 특성을 향상시킬 수 있는 반도체 소자의 트랜지스터를 제조하는 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a transistor of a semiconductor device capable of improving electrical characteristics while increasing an effective channel length under a limited area.
이러한 목적을 달성하기 위한 본 발명의 트랜지스터 제조방법은 실리콘 기판(11)상부에 제 1 열산화막(12)을 형성하고, 그 상부에 제 1 감광막(13)을 도포한 후 소정의 마스크를 사용한 식각공정으로 상기 제 1 감광막(13)을 패턴화하고, 패턴화된 제 1 감광막(13)을 이용한 식각공정으로 상기 제 1 열산화막(12)과 그 하부의 실리콘 기판(11)을 소정두께 식각하여 돌출된 구조의 실리콘 기판(11)을 형성하는 단계와, 상기 단계로부터 패턴화된 제 1 감광막(13)을 제거한 후 전체구조 상부에 제 2 열산화막(14)을 형성한 다음 저농도 불순물 이온을 주입하여 저농도 불순물 영역(15)을 형성하는 단계와, 상기 단계로부터 제 1 및 2 열산화막(12 및 14)을 습식식각으로 제거한 다음 전체구조 상부에 게이트 산화막(16)을 형성하고, 그 상부에 불순물이 도핑된 폴리실리콘을 증착한 후 게이트 전극용 마스크를 이용하여 실리콘 기판(11)의 돌출부를 감싸도록 패턴화된 폴리실리콘층(17)을 형성하는 단계, 상기 단계로부터 패턴화된 폴리실리콘층(17)의 측벽에 질화막 스페이서(18)를 형성한 후 고농도 불순물 이온을 주입하고, 고온의 어닐링 공정을 거쳐 고농도 불순물 영역(19)을 형성하는 단계와, 상기 단계로부터 전체구조 상부에 제 2 감광막(20)을 도포한 후 패턴화된 폴리실리콘층(17) 및 질화막 스페이서(18)의 상단이 노출되게 패턴화하고, 상기 패턴화된 제 2 감광막(20)을 식각 장벽층으로 하여 질화막 스페이서(18)를 제거한 후 포켓이온을 주입하여 포켓이온주입영역(21)을 형성하는 단계와, 상기 단계로부터 패턴화된 감광막(20)을 제거한 후 전체구조 상부에 전이금속을 증착하고 고온 열처리하여 저농도 불순물 영역(15), 고농도 불순물 영역(19) 및 포켓이온주입영역(21)으로 된 소오스/드레인 영역과 패턴화된 폴리실리콘층(17)에 실리사이드(22)를 형성하고, 실리사이드가 형성되지 않은 전이금속은 황산과 과산화수소의 혼합액으로 제거하는 단계로 이루어지는 것을 특징으로 한다.In the transistor manufacturing method of the present invention for achieving the above object, the first thermal oxide film 12 is formed on the silicon substrate 11, the first photosensitive film 13 is applied thereon, and then etching is performed using a predetermined mask. Patterning the first photoresist film 13, and etching the first thermal oxide film 12 and the silicon substrate 11 under the predetermined thickness by an etching process using the patterned first photoresist film 13. Forming a protruding silicon substrate 11, removing the patterned first photosensitive film 13 therefrom, forming a second thermal oxide film 14 over the entire structure, and then implanting low concentration impurity ions. Forming a low concentration impurity region 15 by wet etching the first and second thermal oxide films 12 and 14 from the step, and then forming a gate oxide film 16 over the entire structure, and impurity thereon. Increase the doped polysilicon And forming a patterned polysilicon layer 17 to cover the protrusion of the silicon substrate 11 by using a mask for the gate electrode, wherein the nitride film spacer is formed on the sidewall of the patterned polysilicon layer 17. Forming 18 and then implanting high concentration impurity ions, forming a high concentration impurity region 19 through a high temperature annealing process, and applying a second photoresist film 20 over the entire structure The patterned polysilicon layer 17 and the top of the nitride film spacer 18 are exposed, and the nitrided spacer 18 is removed using the patterned second photosensitive film 20 as an etch barrier layer. Forming a pocket ion implantation region 21 by implantation, removing the patterned photoresist film 20 therefrom, depositing a transition metal over the entire structure, and performing a high temperature heat treatment to form a low concentration impurity region 15 and a high concentration. The silicide 22 is formed in the source / drain region of the pure water region 19 and the pocket ion implantation region 21 and the patterned polysilicon layer 17, and the transition metal without silicide is formed of sulfuric acid and hydrogen peroxide. Characterized in that it comprises a step of removing with the mixed liquid.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2a 도 내지 제 2f 도는 본 발명에 의한 반도체 소자의 트랜지스터를 제조하는 단계를 도시한 소자의 단면도로서, 제 2a 도는 실리콘 기판(11)상부에 제 1 열산화막(12)을 예를들어 1000 ~ 1500 Å 정도의 두께로 형성하고, 그 상부에 제 1 감광막(13)을 도포한 후 소정의 마스크를 사용한 시각공정으로 상기 제1 감광막(13)을 패턴화하고, 패턴화된 제 1 감광막(13)을 이용한 식각공정으로 상기 제 1 열 산화막(12)과 그 하부의 실리콘 기판(11)을 소정두께 식각하여 돌출된 구조의 실리콘 기판(11)을 형성한 상태를 도시한 것이다.2A through 2F are cross-sectional views of a device for manufacturing a transistor of a semiconductor device according to the present invention. FIG. 2A illustrates a first thermal oxide film 12 on the silicon substrate 11. It is formed to a thickness of about 1500 kPa, the first photosensitive film 13 is applied thereon, and then the first photosensitive film 13 is patterned by a visual process using a predetermined mask, and the patterned first photosensitive film 13 is formed. Shows a state in which the silicon substrate 11 having a protruding structure is formed by etching the first thermal oxide film 12 and the silicon substrate 11 below the semiconductor substrate by a predetermined thickness.
상기에서 소정의 마스크를 패턴 크기는 후공정에서 사용될 게이트 전극용 마스크의 패턴보다 작다.The pattern size of the predetermined mask is smaller than that of the mask for the gate electrode to be used in a later process.
제 2b 도는 상기 패턴화된 제 1 감광막(13)을 제거한 후 전체구조 상부에 제 2 열산화막(14)을 예를들어 100 ~ 300Å정도의 두께로 형성한 다음 저농도 불순물 이온을 주입하여 저농도 불순물 영역(15)을 형성한 상태를 도시한 것이다.In FIG. 2B, after removing the patterned first photoresist layer 13, a second thermal oxide layer 14 is formed on the entire structure to a thickness of, for example, about 100 to about 300 microns, and then low concentration impurity ions are implanted. The state which formed (15) is shown.
상기 저농도 불순물 영역(15)을 실리콘 기판(11)에 대해 수직선의 약 7˚이내의 경사를 갖는 이온주입법으로 예를들어 N- 형인 인(P)원자를 주입하여 형성한다.The low concentration impurity region 15 is formed by implanting, for example, an N-type phosphorus (P) atom by an ion implantation method having an inclination within about 7 degrees of a vertical line with respect to the silicon substrate 11.
제 2c 도는 상기 제 1 및 2 열산화막(12 및 14)을 습식식각으로 제거한 다음 전체구조 상부에 게이트 산화막(16)을 형성하고, 그 상부에 불순물이 도핑된 폴리실리콘을 증착한 후 게이트 전극용 마스크를 이용하여 실리콘 기판(11)의 돌출부를 감싸도록 패턴화된 폴리실리콘층(17)을 형성한 상태를 도시한 것이다.In FIG. 2C, the first and second thermal oxide films 12 and 14 are removed by wet etching, and then, the gate oxide film 16 is formed on the entire structure, and the polysilicon doped with impurities is deposited on the gate electrode. The state in which the patterned polysilicon layer 17 is formed to surround the protrusion of the silicon substrate 11 by using a mask is illustrated.
제 2d 도는 상기 패턴화된 폴리실리콘층(17)의 측벽에 질화막 스페이서(18)를 형성한 후 고농도 불순물 이온을 주입하고, 고온의 어닐링 공정을 거쳐 고농도 불순물 영역(19)을 형성한 상태를 도시한 것이다.FIG. 2D illustrates a state where the nitride spacer 18 is formed on the sidewall of the patterned polysilicon layer 17 and then implanted with a high concentration of impurity ions and a high concentration of impurity region 19 is formed through a high temperature annealing process. It is.
상기 고농도 불순물 영역(19)은 예를들어 N+형인 비소(As)원자를 주입하여 형성한다.The high concentration impurity region 19 is formed by implanting, for example, an arsenic (As) atom having an N + type.
제 2e 도는 전체구조 상부에 제 2 감광막(20)을 도포한 후 패턴화된 폴리실리콘층(17) 및 질화막 스페이서(18)의 상단이 노출되게 패턴화하고, 상기 패턴화된 제 2 감광막(20)을 식각 장벽층으로 하여 인산용액에서 질화막 스페이서(18)를 제거한 후 포켓이온을 주입하여 포켓이온주입영역(21)을 형성한 상태를 도시한 것이다.After applying the second photoresist film 20 to the upper part of FIG. 2e or the entire structure, the patterned polysilicon layer 17 and the upper end of the nitride film spacer 18 are patterned to expose the patterned second photoresist film 20. ) Shows a state in which the pocket ion implantation region 21 is formed by removing the nitride spacer 18 from the phosphoric acid solution using the) as an etching barrier layer and injecting pocket ions.
상기 포켓이온주입영역(21)은 1 ×1011~ 1 ×1017원자/cm2의 농도 및 50 ~ 200KeV의 에너지로 예를들어 붕소(B)원자를 주입하여 형성한다.The pocket ion implantation region 21 is formed by injecting boron (B) atoms, for example, at a concentration of 1 × 10 11 to 1 × 10 17 atoms / cm 2 and an energy of 50 to 200 KeV.
상기에서 제 2 감광막(20)대신에 SOG막을 사용할 수 있다.In the above, an SOG film may be used instead of the second photosensitive film 20.
제 2f 도는 상기 패턴화된 감광막(20)을 제거한 후 전체구조 상부에 전이금속을 증착하고 고온 열처리하여 저농도 불순물 영역(15), 고농도 불순물 영역(19) 및포켓이온주입영역(21)으로 된 소오스/드레인 영역과 패턴화된 폴리실리콘층(17)에 실리사이드(22)를 형성하고, 실리사이드가 형성되지 않은 전이금속은 황산과 과산화수소의 혼합액으로 제거한 상태를 도시한 것이다.2F is a source formed of a low concentration impurity region 15, a high concentration impurity region 19, and a pocket ion implantation region 21 by removing the patterned photoresist film 20 and then depositing a transition metal on the entire structure and performing high temperature heat treatment. The silicide 22 is formed in the / drain region and the patterned polysilicon layer 17, and the transition metal in which the silicide is not formed is removed with a mixture of sulfuric acid and hydrogen peroxide.
상술한 바와같이 본 발명은 반도체 소자의 고집적화에 따라 줄어드는 유효채널 길이를 연장시키고, 게이트 전극의 표면에 실리사이드를 형성시키면서 포켓이온주입영역을 형성하므로써 MOSFET의 전기적 특성을 향상시킬 수 있다.As described above, the present invention can improve the electrical characteristics of the MOSFET by extending the effective channel length, which decreases with high integration of the semiconductor device, and forming the pocket ion implantation region while forming silicide on the surface of the gate electrode.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016115A KR100280798B1 (en) | 1994-07-06 | 1994-07-06 | Transistor manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016115A KR100280798B1 (en) | 1994-07-06 | 1994-07-06 | Transistor manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960005888A KR960005888A (en) | 1996-02-23 |
| KR100280798B1 true KR100280798B1 (en) | 2001-03-02 |
Family
ID=66689279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940016115A KR100280798B1 (en) | 1994-07-06 | 1994-07-06 | Transistor manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100280798B1 (en) |
-
1994
- 1994-07-06 KR KR1019940016115A patent/KR100280798B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960005888A (en) | 1996-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100225409B1 (en) | Trench di-Moose and preparation method thereof | |
| JP2862696B2 (en) | An improved method of fabricating an integrated circuit structure having a lightly doped drain (LDD) | |
| US5656518A (en) | Method for fabrication of a non-symmetrical transistor | |
| JP4018780B2 (en) | Manufacturing method of DMOS transistor | |
| JPH0846201A (en) | Semiconductor device and manufacturing method thereof | |
| US5654215A (en) | Method for fabrication of a non-symmetrical transistor | |
| US5567965A (en) | High-voltage transistor with LDD regions | |
| KR100218299B1 (en) | Manufacturing method of transistor | |
| KR950008257B1 (en) | Mos fet and its making method | |
| KR100257074B1 (en) | Mosfet and method for manufacturing the same | |
| KR0170436B1 (en) | Method of manufacturing mosfet | |
| KR100280798B1 (en) | Transistor manufacturing method of semiconductor device | |
| KR100298874B1 (en) | Formation method of transistor | |
| KR100479820B1 (en) | Manufacturing method of semiconductor device | |
| KR100313783B1 (en) | Method for fabricating metal oxide semiconductor transistor | |
| KR0146275B1 (en) | Method for manufacturing mosfet | |
| KR910009042B1 (en) | Method of manufacturing a semiconductor device | |
| KR100235629B1 (en) | Method of manufacturing mosfet | |
| KR100305205B1 (en) | Manufacturing method of semiconductor device | |
| KR100186518B1 (en) | Manufacturing method of semiconductor device | |
| KR100567047B1 (en) | MOS transistor manufacturing method | |
| KR0160917B1 (en) | Manufacturing method of self-aligned MOS transistor | |
| KR100898257B1 (en) | Manufacturing method of semiconductor device | |
| KR0122520B1 (en) | Fabrication method of semiconductor device | |
| KR100273299B1 (en) | Method for fabricating mos transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19940706 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19990302 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19940706 Comment text: Patent Application |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20000926 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20001113 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20001114 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20040810 |