JPH0536623A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0536623A JPH0536623A JP3188520A JP18852091A JPH0536623A JP H0536623 A JPH0536623 A JP H0536623A JP 3188520 A JP3188520 A JP 3188520A JP 18852091 A JP18852091 A JP 18852091A JP H0536623 A JPH0536623 A JP H0536623A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- rom
- film
- gate
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に開孔により、コード切り換えの可能なリード
・オンリー・メモリー（以下ＲＯＭと略称）を含む半導
体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a read-only memory (hereinafter abbreviated as ROM) whose code can be switched by opening a hole.
【０００２】[0002]
【従来の技術】従来、この種のＲＯＭを含む半導体装置
は図４（ａ）に示すように半導体基板１の表面にゲート
絶縁膜４を介してゲート被膜５を形成し、このゲート被
膜５をマスクに選択的にドレイン拡散層２及びソース拡
散層３を形成し、ゲート被膜５を覆うように層間絶縁膜
６を形成する。その後、図４（ｂ）に示すようにＲＯＭ
の構成を形定する開孔９を行い、図４（ｃ）に示すよう
に、相互配線７を形成するという製造方法が採用されて
きた。2. Description of the Related Art Conventionally, in a semiconductor device including this type of ROM, a gate film 5 is formed on the surface of a semiconductor substrate 1 via a gate insulating film 4 as shown in FIG. The drain diffusion layer 2 and the source diffusion layer 3 are selectively formed on the mask, and the interlayer insulating film 6 is formed so as to cover the gate coating 5. Then, as shown in FIG.
The manufacturing method has been adopted in which the opening 9 for defining the above-mentioned structure is formed and the interconnection 7 is formed as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この従
来の半導体装置の製造方法ではＲＯＭを構成し、半導体
装置を製造するのに、まず開孔を形成し、その後相互配
線を形成するという製造方法が採られ、少なくとも２回
のフォトレジストパターンを形成する必要があった。そ
の為に従来の半導体装置の製造方法ではＲＯＭ構成後の
工期をこれ以上短縮することは困難であった。However, in this conventional method for manufacturing a semiconductor device, in order to form the ROM and manufacture the semiconductor device, the manufacturing method is first to form the openings and then to form the interconnections. It was necessary to form the photoresist pattern at least twice. Therefore, it is difficult for the conventional method of manufacturing a semiconductor device to further shorten the work period after the ROM configuration.
【０００４】本発明の目的は上記欠点を解決し、工期の
短いＲＯＭを含む半導体装置の製造方法を提供すること
にある。An object of the present invention is to solve the above drawbacks and to provide a method of manufacturing a semiconductor device including a ROM having a short construction period.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板表面に第１の絶縁膜を介してゲー
ト被膜を形成する工程と、このゲート被膜を覆う第２の
絶縁膜を形成する工程と、この第２の絶縁膜上に配線被
膜を形成する工程と、前記ゲート被膜又は不純物拡散領
域との電気的接合を行う為の開孔を形成する工程と、こ
の開孔に導電性の物質を埋め込む工程とを含んで構成さ
れる。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate film on a surface of a semiconductor substrate via a first insulating film and a second insulating film covering the gate film. A step of forming, a step of forming a wiring film on the second insulating film, a step of forming an opening for electrical connection with the gate film or the impurity diffusion region, and a step of forming a conductive film in the opening. And a step of embedding a sexual substance.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例により形成された半導体装
置の断面図であり、図２および図３は本発明の一実施例
を説明するために工程順に示した半導体装置の断面図で
ある。The present invention will be described below with reference to the drawings. 1 is a cross-sectional view of a semiconductor device formed according to an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of the semiconductor device shown in the order of steps for explaining the embodiment of the present invention.
【０００７】まず、図２（ａ）に示すように半導体基板
１上に、ゲート絶縁膜４を形成し、次に、ゲート被膜５
を形成すると図２（ｂ）に示すようになる。これをフォ
トレジストパターンによりゲート被膜５とゲート絶縁膜
４をエッチングすると図２（ｃ）になる。その後図２
（ｄ）に示すようにゲート被膜５と自己整合させて、ソ
ース拡散層３，ドレイン拡散層２を形成する。First, as shown in FIG. 2A, a gate insulating film 4 is formed on a semiconductor substrate 1, and then a gate film 5 is formed.
2B is formed as shown in FIG. 2C is obtained by etching the gate coating 5 and the gate insulating film 4 with a photoresist pattern. Then Figure 2
As shown in (d), the source diffusion layer 3 and the drain diffusion layer 2 are formed by self-aligning with the gate coating 5.
【０００８】次に、図３（ａ），（ｂ）に示すように、
層間絶縁膜６を被着し、相互配線７をアルミニウム等の
金属により行う。その後、図３（ｃ），（ｄ）に示すよ
うに、相互配線７の形成後に開孔９を行い、埋め込みコ
ンタクト８を選択ＣＶＤ法等により形成し、ＭＯＳトラ
ンジスタを形成する。Next, as shown in FIGS. 3 (a) and 3 (b),
The interlayer insulating film 6 is deposited, and the interconnection 7 is made of metal such as aluminum. After that, as shown in FIGS. 3C and 3D, an opening 9 is formed after the interconnection 7 is formed, and a buried contact 8 is formed by a selective CVD method or the like to form a MOS transistor.
【０００９】以上説明したように、本発明はコンタクト
孔の開孔を相互配線形成後に行い、選択ＣＶＤ法により
埋め込みコンタクトを形成する為、従来コンタクト孔の
開孔を行い相互配線を形成するという製造法よりも、Ｒ
ＯＭ構成後の工期を短縮することができる効果を持つ。As described above, according to the present invention, since the contact hole is formed after the interconnection is formed and the buried contact is formed by the selective CVD method, the conventional contact hole is formed to form the interconnection. R than law
This has the effect of shortening the construction period after the OM configuration.
【００１０】[0010]
【発明の効果】以上説明したように、本発明はコンタク
ト孔の開孔を相互配線形成後に行い、埋め込みコンタク
トを行うことにより、コンタクトによりＲＯＭを構成す
る半導体装置のＲＯＭ構成後の製造を、従来コンタクト
孔の開孔と交互配線の為２度のフォトレジストのパター
ニングが必要であったものが、１度で形成できるので、
ＲＯＭ構成後の工期を短縮できるという効果を有する。As described above, according to the present invention, the contact hole is formed after the interconnection is formed, and the buried contact is formed, so that the semiconductor device in which the ROM is formed by the contact is manufactured after the ROM structure is formed. Since it was necessary to pattern the photoresist twice because of the opening of the contact hole and the alternate wiring, it can be formed once.
This has the effect of shortening the construction period after ROM construction.
【００１１】また、埋め込みコンタクト法を用いること
により、従来コンタクト孔を開孔する際、相互配線のカ
バレッヂの問題からコンタクト孔にテーパーをつける必
要性があった。この為コンタクト孔をゲートから離さな
ければならなかったが、テーパーをつける必要性がなく
なり、同じ容量を持つＲＯＭであっても占有面積を縮小
できるという効果も有している。Further, by using the buried contact method, it has been necessary to taper the contact hole when the contact hole is opened, due to the problem of coverage of interconnections. For this reason, the contact hole had to be separated from the gate, but it was not necessary to taper the contact hole, and it has an effect that the occupied area can be reduced even in a ROM having the same capacity.
【図１】本発明の一実施例により形成された半導体装置
の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device formed according to an embodiment of the present invention.
【図２】本発明の一実施例を説明するために工程順に示
した一部工程の半導体装置の断面図である。FIG. 2 is a cross-sectional view of a partial process semiconductor device shown in the order of processes for explaining an embodiment of the present invention.
【図３】本発明の一実施例を説明するために工程順に示
した図２に続く工程の断面図である。FIG. 3 is a cross-sectional view showing a step that follows FIG. 2 and is shown in the order of steps for explaining the embodiment of the present invention.
【図４】従来の半導体装置の製造方法を説明するために
工程順に示した半導体装置の断面図である。FIG. 4 is a cross-sectional view of a semiconductor device, which is shown in order of steps for explaining a conventional method for manufacturing a semiconductor device.
１ 半導体基板 ２ ドレイン拡散層 ３ ソース拡散層 ４ ゲート絶縁膜 ５ ゲート被膜 ６ 層間絶縁膜 ７ 相互配線 ８ 埋め込みコンタクト ９ 開孔 1 Semiconductor Substrate 2 Drain Diffusion Layer 3 Source Diffusion Layer 4 Gate Insulation Film 5 Gate Film 6 Interlayer Insulation Film 7 Mutual Wiring 8 Buried Contact 9 Opening
Claims (1)
ゲート被膜を形成する工程と、前記ゲート被膜を覆う第
２の絶縁膜を形成する工程と、前記第２の絶縁膜上に配
線被膜を形成する工程と、前記ゲート被膜又は不純物拡
散領域との電気的接合を行う為の開孔を形成する工程
と、前記開孔に導電性の物質を埋め込む工程とを有する
ことを特徴とする半導体装置の製造方法。Claims: What is claimed is: 1. A step of forming a gate film on a surface of a semiconductor substrate with a first insulating film interposed therebetween, a step of forming a second insulating film covering the gate film, and a second step of forming the second insulating film. A step of forming a wiring film on the insulating film, a step of forming an opening for electrical connection with the gate film or the impurity diffusion region, and a step of embedding a conductive substance in the opening. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188520A JPH0536623A (en) | 1991-07-29 | 1991-07-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188520A JPH0536623A (en) | 1991-07-29 | 1991-07-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0536623A true JPH0536623A (en) | 1993-02-12 |
Family
ID=16225153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3188520A Pending JPH0536623A (en) | 1991-07-29 | 1991-07-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536623A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009182222A (en) * | 2008-01-31 | 2009-08-13 | Tokyo Electron Ltd | Substrate cleaning apparatus, substrate cleaning method, program, and computer storage medium |
| US9654104B2 (en) | 2007-07-17 | 2017-05-16 | Apple Inc. | Resistive force sensor with capacitive discrimination |
| US9977518B2 (en) | 2001-10-22 | 2018-05-22 | Apple Inc. | Scrolling based on rotational movement |
| US10139870B2 (en) | 2006-07-06 | 2018-11-27 | Apple Inc. | Capacitance sensing electrode with integrated I/O mechanism |
| US10180732B2 (en) | 2006-10-11 | 2019-01-15 | Apple Inc. | Gimballed scroll wheel |
| US10353565B2 (en) | 2002-02-25 | 2019-07-16 | Apple Inc. | Input apparatus and button arrangement for handheld device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250477A (en) * | 1988-08-12 | 1990-02-20 | Sony Corp | Memory device |
| JPH0268952A (en) * | 1988-09-02 | 1990-03-08 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1991
- 1991-07-29 JP JP3188520A patent/JPH0536623A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250477A (en) * | 1988-08-12 | 1990-02-20 | Sony Corp | Memory device |
| JPH0268952A (en) * | 1988-09-02 | 1990-03-08 | Toshiba Corp | Semiconductor device and manufacture thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9977518B2 (en) | 2001-10-22 | 2018-05-22 | Apple Inc. | Scrolling based on rotational movement |
| US10353565B2 (en) | 2002-02-25 | 2019-07-16 | Apple Inc. | Input apparatus and button arrangement for handheld device |
| US10139870B2 (en) | 2006-07-06 | 2018-11-27 | Apple Inc. | Capacitance sensing electrode with integrated I/O mechanism |
| US10359813B2 (en) | 2006-07-06 | 2019-07-23 | Apple Inc. | Capacitance sensing electrode with integrated I/O mechanism |
| US10890953B2 (en) | 2006-07-06 | 2021-01-12 | Apple Inc. | Capacitance sensing electrode with integrated I/O mechanism |
| US10180732B2 (en) | 2006-10-11 | 2019-01-15 | Apple Inc. | Gimballed scroll wheel |
| US9654104B2 (en) | 2007-07-17 | 2017-05-16 | Apple Inc. | Resistive force sensor with capacitive discrimination |
| JP2009182222A (en) * | 2008-01-31 | 2009-08-13 | Tokyo Electron Ltd | Substrate cleaning apparatus, substrate cleaning method, program, and computer storage medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19971007 |