KR0161729B1 - Semiconductor device & manufacture method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In a semiconductor device in which a defect occurs in which neighboring word lines are short-circuited with each other, one word line is used as it is and only one word line is used in place of the auxiliary word line. Since the number of auxiliary word lines in each memory block can be reduced, it is advantageous for high integration of the device, the replacement process of the shorted word lines is simple, and the defective rate due to the shorted word lines can be reduced, thereby improving the process yield.

Description

Semiconductor device and manufacturing method

1 is a schematic diagram for explaining a word line replacement circuit of a general semiconductor device.

2 is a schematic diagram for explaining a word line replacing process of a semiconductor device.

* Explanation of symbols for the main parts of the drawings

1: active area 2: bit line contact

3: sense amplifier 4: capacitor contact

10: memory cell area XA0, XA1, XA2: word line

F0, F1, F2: Fuse BL1, BL2: Bit line

BL1 #, BL2 #: Bit line bar XR: Auxiliary word line

INV: Inverter R: Resistance

T1, T2, T11, T12, TR1, TR2: Transistor

0 / 1.0 / 2,1 / 1,1 / 2,2 / 1,2 / 2, R / 1, R / 2: address of cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, in a semiconductor device in which two adjacent word lines are shorted, only one word line is repaired and the other is used as it is, thereby increasing the repair efficiency to increase the process yield. The present invention relates to a semiconductor device capable of improving and a method of manufacturing the same.

As semiconductor devices are highly integrated due to the development of general micropattern forming technology, in the case of DRAM devices, when the memory capacity is increased by four times, the size of the chip is also increased by about two times. Therefore, since the rate of partial defects is increased, the yield of a complete chip without any defects in the manufactured chips is reduced and productivity is decreased. Therefore, an extra memory cell is formed in the chips, and the chips are replaced with cells in which the defects occur during the manufacturing process. By using it increases the yield of the chip.

1 is a schematic diagram for explaining a word line replacement process of a general semiconductor device, and is an example of a memory block having one auxiliary word line.

First, a memory cell region 10, which is a memory block having a plurality of word lines XA1, XA2, ... connected to a plurality of memory cells, is formed on one side of a semiconductor substrate. One auxiliary word line XR is formed in contact with one side.

A word line replacement circuit is formed below the memory cell region 10.

The word line replacement circuit includes transistors T1, T2, ... connected to respective word lines XA0, XA1, XA2, ... and share an output terminal, and the transistors T1, T1, A series of transistors (T11, T12, ...) connected to the gate of each gate, and fuses (F0, F1) connected to the transistors (T11, T12, ...) Inverter INV, two transistors TR1 and TR2 and a resistor (F2, ...), connected to the transistors T11, T12, ... to operate the auxiliary word line XR. It consists of a predetermined selection circuit having R).

The word line replacement process will now be described with reference to the drawings.

First, in a state where a failure does not occur, all the fuses F1, F2, ... are connected, and C0 is high to select word line XA0, and C1 and C2 are low. Shall be. At this time, T1 and T11 go high, Nodes B and TR1 go low, TR2 goes high, and the potential of Φ X crosses TR2 and T1 to select word line XA0. In this manner, each word line XA1, XA2, ... is selected.

If the word line XA0 is defective, the fuse F0 is blown using a laser to replace the word line XA0 with the auxiliary word line XR. At this time, in order to select the auxiliary word line XR instead of the word line XA0, C0 is set high and C1 and C2 are set low. At this time, T1 and T11 are high, and node B and TR1 are high because the fuse F0 is not connected, and TR2 is low, and the potential of ΦX crosses TR1 and the auxiliary word line XR is selected.

By improving the process yield by replacing the defective word line with the auxiliary word line by the above method, it is possible to replace with the same method by providing two or more auxiliary word lines even when two or more word lines are defective.

Referring to FIG. 2, a method of replacing a word line in a semiconductor device in which two word lines are short-circuited is as follows.

2 is a schematic diagram illustrating a word line replacement process of a semiconductor device, and is an example of a folded bit line method in which bit lines and bit line bars are connected to one sense amplifier in one memory cell block.

First, in the folded bit line method, a plurality of rectangular active regions 1 are arranged in a matrix such that they are alternate with each other, and have a predetermined protrusion at a central portion of the active region 1 and a bit line contact at an upper side thereof. 2) is formed.

In addition, a series of word lines XA0, XA1, XA2, ... passing through both sides of the bit line contact 2 extend in an up-down direction, and in a left-right direction between the active regions 1. Bit lines BL1, BL2, ... and bit line bars BL1 #, BL2 #, ... are alternately extended to orthogonal to the word lines XA0, XA1, XA2, ... The bit lines BL1, BL2, ..., and bit line bars BL1 #, BL2 #, ... are connected to one sense amplifier 3.

In addition, two capacitor contacts 4 are formed at portions beyond the word lines XA0, XA1, XA2, ... on both sides of the active region 1, so that each cell (0/1, 1/1, ...) is formed. And the auxiliary word line XR is formed on one side of the memory block to form the auxiliary cells R1 / 1, R1 / 2, ....

When two adjacent word lines sharing bit line contacts, for example, XA0 and XA1 are shorted during the manufacturing process in the folded bit line type semiconductor device, different data are stored in cells 0/1 and 1/1. If one of the word lines XA0 and XA1 is selected when inputting, two word lines are selected together to input the same data into cells 0/1 and 1/1. Therefore, both word lines must be replaced.

In addition, when XA1 and XA2 having different bit line contacts are short-circuited, when different data are input to cells 1/2 and 2/1, if either word line XA1 or XA2 is selected, two word lines are connected. Selected together, the same data is entered into cells 1/2 and 2/1. Therefore, both word lines must be replaced.

Instead of the folded bit line method as described above, two active bit regions are arranged in the shape of a checker board, and two bit lines and bit line bars formed in different memory cell blocks are connected to one sense amplifier. All shorted word lines of are replaced with the auxiliary word lines.

As described above, shorting of adjacent word lines may short-circuit the gate electrodes, or short-circuit strap lines, which are metal wires, to prevent time delay of the word lines.

The semiconductor device using the word line replacement method by the conventional method as described above is prepared when two word lines are shorted because both word lines should be replaced by an auxiliary word line when two adjacent word lines are shorted. Since the auxiliary word line is insufficient, the entire semiconductor device must be poorly processed, resulting in a decrease in process yield.

In order to solve this problem, a plurality of auxiliary word lines may be provided. However, this method has a plurality of memory cell blocks in the case of highly integrated semiconductor devices, which increases the area occupied by the auxiliary word lines, thereby preventing high integration of the devices.

The present invention is to solve the above problems, and the object of the present invention is to use one word line as it is when two adjacent word lines are short-circuited, and replace only one word line with an auxiliary word line. The present invention provides a semiconductor device that can reduce the number of word lines, thereby facilitating high integration, or improve process yield by reducing defective rates due to word line short circuits.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the process yield by simplifying the word line replacement process by replacing only one word line with an auxiliary word line when two adjacent word lines are shorted. have.

A feature of the semiconductor device according to the present invention for achieving the above object is that a bit line and a bit line bar formed in one memory block are connected to one sense amplifier, and share a single active area. In a folded bit line type semiconductor device in which two word lines are shorted, one of the shorted word lines is used as it is and a fuse connected to the other shorted word line is cut and replaced by an auxiliary word line. .

Another characteristic of the semiconductor device according to the present invention is an open bit line type semiconductor in which bit lines and bit line bars formed in different memory blocks are connected to one sense amplifier, and two adjacent word lines are short-circuited. In the device, one of the shorted word lines is used as it is and the other shorted word line is replaced by an auxiliary word line.

A feature of the semiconductor device manufacturing method according to the present invention is a folded bit line method in which two adjacent word lines are short-circuited and a bit line and a bit line bar formed in one memory block are connected to one sense amplifier. In the method of manufacturing a semiconductor device of the present invention, one of the shorted word lines is used as it is, and a step of cutting a fuse connected to the other shorted word line and replacing the auxiliary word line is provided.

Another feature of the method of fabricating a semiconductor device according to the present invention is an off-bit line method in which two adjacent word lines are short-circuited and bit lines and bit line bars formed in different memory blocks are connected to one sense amplifier. In the method of manufacturing a semiconductor device, one of the shorted word lines is used as it is, and the fuse connected to the other shorted word line is cut and replaced with an auxiliary word line.

Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

A folded bit line semiconductor device and a method of fabricating the same according to an embodiment of the present invention will be described with reference to FIG. 2 which is a word line replacement process diagram of a folded bit line method.

First, in the semiconductor device, the configuration of one memory block is arranged in a staggered matrix shape to form active regions 1, bit line contacts 2 formed at a central portion thereof, and both sides of the active region 1. Alternatingly arranged word lines XA0, XA1, XA2, ..., and bit lines BL1, BL2, ... orthogonal to the word lines XA0, XA1, XA2, ... And bit line bars (BL1 #, BL2 #, ...) and the bit lines (BL1, BL2, ...) and bit line bars (BL1 #, BL2 #, ...) A sense amplifier 3, and an auxiliary word line XR formed on one side of the block.

In the folded bit line type semiconductor device, when two adjacent word lines sharing the bit line contact 2, for example, XA0 and XA1 are shorted during the manufacturing process, one of the word lines XA0 or XA1 is selected. If the fuse is cut and replaced with the auxiliary word line XR, and the other word line is used as it is, the cells 0 / 1,0 / 2, ... or 1/1, 1/2, ... are not used. Since the cells become chips, the chip operates normally.

That is, when inputting different data into cells 0/1 and 1/1, if either word line XA0 or XA1 is selected, each of BL1 and BL1 # or BL2 and BL2 # connected to one sense amplifier 3 is mutually selected. The opposite data is sent and works normally.

On the other hand, when adjacent word lines XA1 and XA2 that do not share the bit line contacts 2 are short-circuited, when different data is input into cells 1/1 and 2/1, one of the word lines XA1 and XA2 is selected. In this case, since word lines XA1 and XA2 are short-circuited, both word lines are defectively processed.

That is, if only one word line is replaced with an auxiliary word line, when selecting word line XA1 or XA2, BL1 and BL1 # or BL2 and BL2 # connected to one sense amplifier 3 transmit the same data, so that two short circuits are performed. All the word lines should be replaced with the auxiliary word lines.

Therefore, in the folded bit line type semiconductor device, the probability that the adjacent word line is shorted and only one word line can be replaced with the auxiliary word line is when two adjacent word lines sharing the bit line contact 2 are shorted. This is not applicable to the case where the adjacent word line which does not share the bit line contact 2 is short-circuited and thus is 50%.

Although not shown, in the case of an open bit line type semiconductor device in which bit lines and bit line bars formed in different memory cell blocks are connected to one sense amplifier, one adjacent word line is shorted. Since the bit lines and bit line bars connected to the sense amplifiers are located in different memory blocks, replacing only one of the word lines shorted with the auxiliary word line, the chip operates normally.

The word line short circuit may occur at both the gate electrode and the strap line, and the idea of the present invention may be applied to both cases.

As described above, according to the inventive concept of replacing only one word line with an auxiliary word line when a neighboring word line is shorted, in a folded bit line type semiconductor device, a single word line is formed by shorting a neighboring word line. There is a 50% chance of replacing the bay with an auxiliary word line, and the probability is 100% for the open bitline method.

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, in a semiconductor device in which a defect occurs in which neighboring word lines are short-circuited with each other, one word line is used as it is and only one word line is an auxiliary word. Since it is used in place of the line, the number of auxiliary word lines in each memory block can be reduced, which is advantageous for high integration of the device, and the replacement process of the shorted word line is simple, and the defective rate by the shorted word line is reduced, thereby improving the process yield. There is an advantage that can be improved.

Claims (5)

In a folded bit line type semiconductor device in which a bit line and a bit line bar formed in one memory block are connected to one sense amplifier, and two adjacent word lines that share one active region are short-circuited. And one of the shorted word lines is used as it is and the other shorted word line is replaced with an auxiliary word line. The semiconductor device according to claim 1, wherein the shorted word line is a short of a gate electrode, a strap line, or both. In an open bit line type semiconductor device in which bit lines and bit line bars formed in different memory blocks are connected to one sense amplifier, and two adjacent word lines are shorted, one of the shorted word lines is provided. Is used as is, and another shorted word line is replaced with an auxiliary word line. A method of manufacturing a folded bit line semiconductor device in which two adjacent word lines are short-circuited and bit lines and bit line bars formed in one memory block are connected to one sense amplifier. A method of manufacturing a semiconductor device, the method comprising: using one of the lines as it is and cutting the fuse connected to the other shorted word line to replace the auxiliary word line. In an open bit line type semiconductor device manufacturing method in which two adjacent word lines are short-circuited and bit lines and bit line bars formed in different memory blocks are connected to one sense amplifier, the shorted word lines A method of manufacturing a semiconductor device, the method comprising: using one of them and cutting a fuse connected to another shorted word line and replacing the fuse with an auxiliary word line.