CN114357926A - Layout method of electric fuse unit array - Google Patents

Abstract

The invention provides a layout method of an electric fuse unit array, which comprises the following steps: an electrical fuse cell pair structure comprising, two electrical fuse cells; the first electric fuse unit comprises a first transistor and a first electric fuse unit; the second electric fuse unit comprises a second transistor and a second electric fuse unit; the first electric fuse unit is connected across the first transistor and the second transistor; the second electrical fuse unit is connected across the second transistor and the first transistor. Therefore, the invention can achieve the technical effect that the area of the layout can be reduced compared with the layout in the prior art under the condition of not changing various performances.

Description

Layout method of electric fuse cell array

technical field

The invention relates to an integrated circuit layout technology, in particular to a layout layout method of an electric fuse unit array.

Background technique

The electric fuse (eFuse) is based on the electromigration (EM) principle, and realizes the on-chip programming function with high reliability through the principle of blowing the fuse. As the market demands higher and higher chip area, eFuse, as a dedicated module (IP) inside the chip for parameter setting, has become one of the main design indicators. In the eFuse module, the array composed of eFuse units occupies more than half of the entire module area. Therefore, reducing the area of the eFuse unit array is to increase the eFuse. One of the main means of module competitiveness.

In the layout design of the electric fuse (eFuse), the array composed of the electric fuse (eFuse) unit occupies more than half of the overall area. The electric fuse (eFuse) unit consists of a fuse and a selection tube. In a conventional design, the array area is formed by splicing the area of individual eFuse units, that is, the product of the area of a single eFuse unit and the number of units.

Referring to FIG. 1A , the storage area of an electric fuse in the prior art is composed of an array of electric fuse cells, as shown in FIG. 1 , wherein the storage cells in the array already appear in the form of a combination of independent electric fuse cells , this arrangement is for the convenience of layout design and the combination of different capacities.

Referring to FIG. 1B , there is an electric fuse unit 01 in a layout of an electric fuse layout in the prior art. The total area of the electric fuse array = the layout area of a single electric fuse unit X the number of rows X the number of columns. As shown in 1C, a unit pair directly spliced by two independent electric fuse units 01 is used as the basic unit form, which can share and save peripheral wiring. 1D shows a schematic diagram of one of the electric fuses and transistor paths of the two independent electric fuse units 01 in FIG. 1C , which is shown in the solid line box in FIG. 1B , and the lines with arrows are used to indicate the conditions of the paths. Referring to FIG. 1E , taking the electric fuse unit of the 28nm process platform as an example, the area of the NMOS tube and the electric fuse is 14.4 μm ² , and the combined area of the two units is 28.8 μm ² .

The problem existing in the prior art is that the above two methods are not optimal in terms of layout area and efficiency.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is: how to further reduce the layout area and improve the utilization efficiency of the layout area.

In order to solve the above technical problems, the present invention provides a layout method of an electric fuse unit array, which aims to improve the layout method of the electric fuse unit array and reduce the area of the electric fuse module.

In order to achieve the above object, the present invention provides a layout layout method of an electric fuse unit array, including: an electric fuse unit pair structure, which includes two electric fuse transistor units;

The first electric fuse transistor unit includes: a first transistor and a first electric fuse unit;

The second electric fuse transistor unit includes: a second transistor and a second electric fuse unit;

The first electric fuse unit is connected across the first transistor and the second transistor;

The second electrical fuse unit is connected across the second transistor and the first transistor.

Preferably, the first electric fuse unit includes a first anode pad, a first fuse, and a first cathode pad, and both ends of the first fuse are connected to the first anode pad and the first cathode pad;

The second electric fuse unit includes a second anode pad, a second fuse, and a second cathode pad, and both ends of the second fuse are connected to the second anode pad and the second cathode pad;

The first anode pad-first fuse-first cathode pad is arranged parallel to the second cathode pad-second fuse-second anode pad along the first direction,

In a second direction perpendicular to the first direction, the first anode pad is aligned with the second cathode pad, and the first cathode pad is aligned with the second anode pad.

Preferably, the first anode pad is located at the second transistor, and the first cathode pad is located at the first transistor;

a second anode pad is located at the first transistor, and a second cathode pad is located at the second transistor;

The first transistor and the second transistor are arranged cross-symmetrically.

Preferably, the first transistor and the second transistor are MOS transistors.

Preferably, the first transistor and the second transistor are NMOS transistors.

Preferably, the first anode pad and the first cathode pad are in a plate shape, the first fuse is in a strip shape, and the width of the first anode pad and the first cathode pad is much larger than the width of the first fuse;

The second anode pad and the second cathode pad are plate-shaped, the second fuse is strip-shaped, and the widths of the second anode pad and the second cathode pad are much larger than the width of the second fuse.

Preferably, the first anode pad and the second anode pad are formed by using a third metal layer;

The first fuse and the second fuse are formed by using a second metal layer;

The first cathode pad and the second cathode pad are formed by using the second metal layer;

the first anode pad is connected from the third metal layer to the second metal layer of the first fuse through the first via hole;

The second anode pad is connected from the third metal layer to the second metal layer of the second fuse through the second via hole.

Preferably, the second metal layer is arranged along the first direction, and the third metal layer is arranged along the second direction;

The first bit line and the second bit line are respectively formed by the third metal layer;

The word lines are formed through the second metal layer.

Preferably, the equivalent circuit formed includes:

The first line located in the third metal layer is connected to the first anode pad located in the third metal layer, connected to the first fuse located in the second metal layer through the first communication hole, and then connected to the first fuse located in the second metal layer. a first cathode pad;

The second bit line located in the third metal layer is connected to the second anode pad located in the third metal layer, connected to the second fuse located in the second metal layer through the second via hole, and then connected to the second fuse located in the second metal layer. a second cathode pad;

the first anode pad is located at the first transistor, and the first cathode pad is located at the second transistor;

a second anode pad is located at the second transistor, and a second cathode pad is located at the first transistor;

The first transistor and the second transistor are arranged cross-symmetrically;

The source, drain and gate of the first transistor and the second transistor are connected by a second metal layer;

The equivalent circuit formed also includes:

The source or drain of the first transistor is connected to the first cathode pad, the drain or source of the first transistor is grounded, and the gate of the first transistor is connected to the word line;

The source or drain of the second transistor is connected to the second cathode pad, the drain or source of the second transistor is grounded, and the gate of the second transistor is connected to the word line.

Preferably, an integrated integrated circuit is formed by combining the electric fuse units provided by the method with the structure array.

Compared with the prior art, the present invention provides a layout layout method of an electric fuse unit array, including: an electric fuse unit pair structure, which includes two electric fuse units; the first electric fuse unit includes a first transistor and a first electric fuse unit; the second electric fuse unit includes a second transistor and a second electric fuse unit; the first electric fuse unit is connected across the first transistor and the second transistor; the second The electrical fuse unit is connected across the second transistor and the first transistor. Accordingly, the technical effect that the present invention can achieve is that the layout area can be reduced compared with the prior art under the condition that various performances remain unchanged.

Description of drawings

FIG. 1A shows an integrated circuit layout diagram of one embodiment of a prior art electrical fuse arrangement.

FIG. 1B shows an integrated circuit layout diagram of yet another embodiment of a prior art electrical fuse arrangement.

FIG. 1C shows the two electric fuse cells employed as basic cells in the integrated circuit layout of FIG. 1B.

FIG. 1D shows a schematic diagram of an electrical fuse, transistor path in the two electrical fuse units in FIG. 1B .

FIG. 1E shows a schematic diagram of the layout area occupied by one e-fuse and one transistor of the e-fuse unit in FIG. 1B on the 28nm technology node process platform.

FIG. 2A shows a schematic diagram of the arrangement of a pair of electric fuses in the electric fuse unit pair structure provided in the layout layout method of the electric fuse unit array provided by the present invention.

FIG. 2B shows an equivalent circuit diagram of the arrangement of the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention.

FIG. 3A shows a schematic diagram of the arrangement of the electric fuse unit pair structure provided in the layout layout method of the electric fuse unit array provided by the present invention.

3B shows an equivalent circuit diagram of the arrangement of the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention.

3C shows a schematic diagram of an electric fuse and a transistor path in the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention.

3D shows a schematic diagram of an equivalent circuit of an electric fuse and a transistor path in the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention.

Description of reference numbers.

current technology:

01 Electric fuse unit;

this invention:

10 Electric fuse unit pair structure

11 The first electric fuse transistor unit

12 Second E-Fuse Transistor Unit

13 First transistor

14 The first electric fuse unit

15 Second transistor

16 Second electric fuse unit

17 First anode pad

18 First fuse

19 First cathode pad

20 Second anode pad

21 Second fuse

22 Second cathode pad

23 Third metal layer

24 Second metal layer

25 The first communication hole

26 Second communication hole

27 first line

28 Second bit line

29 word lines

30 The source or drain of the first transistor

31 Drain or source of the first transistor

32 places

33 Gate of the first transistor

34 Source or drain of the second transistor

35 Drain or source of the second transistor

36 Gate of the second transistor.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIGS. 2A and 3A , a layout layout method of an electric fuse unit array provided by the present invention includes: an electric fuse unit pair structure 10 . The electric fuse unit pair structure 10 includes: two electric fuse transistor units 11 and 12 . The first electric fuse transistor unit 11 includes: a first transistor 13 and a first electric fuse unit 14 . The second electric fuse transistor unit 12 includes: a second transistor 15 and a second electric fuse unit 16 . The first electric fuse unit 14 is connected across the first transistor 13 and the second transistor 15 . The second electric fuse unit 16 is connected across the second transistor 15 and the first transistor 13 .

The first electric fuse unit 14 (Link1) includes: a first anode pad 17 (Pad pad), a first fuse 18, a first cathode pad 19 (Pad pad), and both ends of the first fuse 18 are connected to the first anode pad 17 and the first cathode pad 19.

The second electric fuse unit 16 (Link2) includes a second anode pad 20 (Pad pad), a second fuse 21 , and a second cathode pad 22 (Pad pad), and both ends of the second fuse 21 are connected to the second anode pad 20 and the second cathode pad 22 .

The first anode pad 17 - the first fuse 18 - the first cathode pad 19 are arranged in the first direction X parallel to the second cathode pad 22 - the second fuse 21 - the second anode pad 20 . The first direction X is also the longitudinal direction of the first fuse 18 and the second fuse 21 .

In the second direction Y perpendicular to the first direction X, the first anode pad 17 is aligned with the second cathode pad 22 and the first cathode pad 19 is aligned with the second anode pad 20 .

The first anode pad 17 is located at the second transistor 15 and the first cathode pad 19 is located at the first transistor 13 .

The second anode pad 20 is located at the first transistor 13 and the second cathode pad 22 is located at the second transistor 15 .

The first transistor 13 and the second transistor 15 are arranged cross-symmetrically.

The first transistor 13 and the second transistor 15 are MOS transistors.

The first transistor 13 and the second transistor 15 are NMOS transistors (NMOS1 and NMOS2 respectively). The NMOS tube is used as the selection tube.

The first anode pad 17 and the first cathode pad 19 are in a plate shape, and the first fuse 18 is in a strip shape.

The second anode pad 20 and the second cathode pad 22 are in a plate shape, and the second fuse 21 is in a strip shape. Accordingly, when the thickness of the metal layer is the same, the cross-sectional area per unit length of the electric fuse is smaller, and the resistance per unit length is larger for fusing.

The first anode pad 17 and the second anode pad 20 are formed by using the third metal layer 23 (M3).

The first fuse 18 and the second fuse 21 are formed using the second metal layer 24 (M2).

The first cathode pad 19 and the second cathode pad 22 are formed by using the second metal layer 24 (M2).

The first anode pad 17 is connected from the third metal layer 23 to the second metal layer 24 of the first fuse 18 through a first communication hole 25 (Via).

The second anode pad 20 is connected from the third metal layer 23 to the second metal layer 24 of the second fuse 18 through a second communication hole 26 (Via).

The second metal layer 24 is arranged along the first direction X. The third metal layer 23 is arranged along the second direction Y.

The first bit line 27 ( BL1 ) and the second bit line 28 ( BL2 ) are respectively formed by the third metal layer 23 .

Word lines 29 (WL) are formed through the second metal layer 24 .

Referring to Figure 2B, an equivalent circuit is formed, including, as described below.

The first line 27 located in the third metal layer is connected to the first anode pad 17 located in the third metal layer, connected to the first fuse 18 located in the second metal layer through the first communication hole 25, and then connected to the first fuse 18 located in the second metal layer. The first cathode pad 19 of the two metal layers.

The second bit line 28 located in the third metal layer is connected to the second anode pad 20 located in the third metal layer, connected to the second fuse 21 located in the second metal layer through the second via hole 26, and then connected to the second fuse 21 located in the second metal layer. The second cathode pad 22 of the two metal layers.

The first anode pad 17 is located at the second transistor 15 and the first cathode pad 19 is located at the first transistor 13 .

The second anode pad 20 is located at the first transistor 13 and the second cathode pad 22 is located at the second transistor 15 .

The first transistor 13 and the second transistor 15 are arranged cross-symmetrically.

The source, drain and gate of the first transistor 13 and the second transistor 15 are connected by the second metal layer 24 .

Referring to Figure 3B, an equivalent circuit is formed, which also includes, as described below.

The source or drain 30 of the first transistor is connected to the first cathode pad 19 , the drain or source 31 of the first transistor is connected to ground 32 (GND), and the gate 33 of the first transistor is connected to the word line 29 .

The source or drain 34 of the second transistor is connected to the second cathode pad 22 , the drain or source 35 of the second transistor is connected to ground 32 (GND), and the gate 36 of the second transistor is connected to the word line 29 .

The electric fuse unit provided by the method is paired with a structure array to form an integrated integrated circuit.

The layout method of the electric fuse cell array can be applied to the memory (Memory), which has been tested and verified by the Technology Qualification Vehicle (TQV, Technology Qualification Vehicle), and is an optimized module (IP).

3C shows a schematic diagram of an electric fuse and a transistor path in the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention. 3D shows a schematic diagram of an equivalent circuit of an electric fuse and a transistor path in the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention. The lines with arrows in FIG. 3C and FIG. 3D represent the condition of the path, passing through the first fuse unit 14 and the first transistor 13, and passing through the first bit line 27, the first anode pad 17, the first fuse 18, The first cathode pad 19 , the first transistor 13 , the ground formed at the second metal layer 24 , the word line 29 , and the like.

The above is a specific embodiment of the layout method of the electric fuse cell array provided by the present invention. Accordingly, the technical effect that the present invention can achieve is that, compared with the arrangement of the electronic electric fuse unit array of the second embodiment of the prior art shown in FIG. 1E , the independent arrangement of transistors and electric fuse units is changed to Interactive arrangement, so that in the 28nm process platform, the electric fuse unit pair structure shown in FIG. 3A of the present invention also realizes the ability to store 2 bits (bit, bit) information (corresponding to the prior art in FIG. 1E ) two graphic areas), the actual layout area is reduced by 25%.

The above-mentioned specific embodiments and accompanying drawings are merely illustrative to illustrate the technical solutions and technical effects of the present invention, but are not intended to limit the present invention. Any person skilled in the art who is familiar with this technology can modify or change the above-mentioned embodiments within the scope of protection of the claims without violating the technical principle and spirit of the present invention, which all belong to the protection of the rights of the present invention. scope.

Claims (10)

1. A layout method of an electric fuse unit array is characterized by comprising the following steps: an eFuse cell pair structure comprising, two eFuse transistor cells;

the first electrical fuse transistor unit includes: a first transistor and a first electrical fuse unit;

the second electrical-fuse transistor unit includes: a second transistor and a second electrical fuse unit;

the first electric fuse unit is connected across the first transistor and the second transistor;

the second electrical fuse unit is connected across the second transistor and the first transistor.

2. The layout method of an electric fuse cell array as claimed in claim 1,

the first electric fuse unit comprises a first anode pad, a first fuse wire and a first cathode pad, wherein two ends of the first fuse wire are connected with the first anode pad and the first cathode pad;

the second electric fuse unit comprises a second anode pad, a second fuse wire and a second cathode pad, wherein two ends of the second fuse wire are connected with the second anode pad and the second cathode pad;

the first anode pad-first fuse-first cathode pad is arranged in parallel to the second cathode pad-second fuse-second anode pad along a first direction,

in a second direction perpendicular to the first direction, the first anode pad is aligned with the second cathode pad, and the first cathode pad is aligned with the second anode pad.

3. The layout method of an electric fuse cell array according to claim 2,

a first anode pad at the second transistor and a first cathode pad at the first transistor;

a second anode pad at the first transistor and a second cathode pad at the second transistor;

the first transistor and the second transistor are arranged in a cross-symmetrical manner.

4. The layout method of an efuse cell array according to claim 1, wherein the first transistor and the second transistor are MOS transistors.

5. The layout method of an efuse cell array according to claim 4, wherein the first transistor and the second transistor are NMOS transistors.

6. The layout method of an electric fuse cell array according to claim 2,

the first anode pad and the first cathode pad are platy, the first fuse wire is in a strip shape, and the width of the first anode pad and the width of the first cathode pad are far larger than that of the first fuse wire;

the second anode pad and the second cathode pad are shaped like a plate, the second fuse is shaped like a strip, and the width of the second anode pad and the width of the second cathode pad are far larger than that of the second fuse.

7. The layout method of an electric fuse cell array according to claim 2,

the first anode pad and the second anode pad are formed by adopting a third metal layer;

the first fuse wire and the second fuse wire are formed by adopting a second metal layer;

the first cathode pad and the second cathode pad are formed by adopting a second metal layer;

the first anode pad is connected to the second metal layer of the first fuse from the third metal layer through the first via hole;

the second anode pad is connected to the second metal layer of the second fuse from the third metal layer through the second communication hole.

8. The layout method of an electrical fuse cell array according to claim 7,

the second metal layer is arranged along the first direction, and the third metal layer is arranged along the second direction;

the first bit line and the second bit line are respectively formed by a third metal layer;

the word line is formed through the second metal layer.

9. The layout method of an electrical fuse cell array according to claim 8,

forming an equivalent circuit comprising:

the first bit line on the third metal layer is connected with the first anode pad on the third metal layer, connected with the first fuse on the second metal layer through the first communication hole, and connected with the first cathode pad on the second metal layer;

the second bit line positioned in the third metal layer is connected with the second anode pad positioned in the third metal layer, is connected with the second fuse positioned in the second metal layer through the second communication hole and is connected with the second cathode pad positioned in the second metal layer;

a first anode pad at the first transistor and a first cathode pad at the second transistor;

a second anode pad at the second transistor and a second cathode pad at the first transistor;

the first transistor and the second transistor are arranged in a crossed symmetrical mode;

the source electrode, the drain electrode and the grid electrode of the first transistor and the second transistor are connected by adopting a second metal layer;

the formed equivalent circuit also comprises:

the source electrode or the drain electrode of the first transistor is connected with the first cathode pad, the drain electrode or the source electrode of the first transistor is grounded, and the grid electrode of the first transistor is connected with the word line;

the source or the drain of the second transistor is connected with the second cathode pad, the drain or the source of the second transistor is grounded, and the gate of the second transistor is connected with the word line.

10. The method for layout of an efuse cell array according to claim 1, wherein the efuse cell pair structure array provided by the method forms an integrated circuit.

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