KR0146257B1 - Method for manufacturing the insulation film of semiconductor device - Google Patents
Method for manufacturing the insulation film of semiconductor deviceInfo
- Publication number
- KR0146257B1 KR0146257B1 KR1019940037488A KR19940037488A KR0146257B1 KR 0146257 B1 KR0146257 B1 KR 0146257B1 KR 1019940037488 A KR1019940037488 A KR 1019940037488A KR 19940037488 A KR19940037488 A KR 19940037488A KR 0146257 B1 KR0146257 B1 KR 0146257B1
- Authority
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- South Korea
- Prior art keywords
- film
- insulating film
- semiconductor device
- pattern
- semiconductor substrate
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000009413 insulation Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 12
- 238000002955 isolation Methods 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000001976 improved effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 절연막을 형성하고 상기 반도체기판의 비활성영역에만 감광막패턴을 형성한 다음, 상기 감광막패턴을 이용한 식각공정으로 상기 절연막을 식각하고 상기 감광막패턴을 제거한 다음, 전체표면상부에 상기 절연막의 두께보다 두껍게 도전층을 형성하고 에치백 공정으로 상기 도전층을 식각하여 상기 절연막과 같은 높이로 평탄화시킴으로써 버즈빅이 발생되지 않아 트랜지스터의 특성을 향상시키고, 후공정에서 발생되는 나칭을 방지할 수 있으며 공정을 단축시켜 반도체소자의 신뢰성 및 수율을 향상시키고 반도체소자의 생산성을 향상시키는 기술이다.The present invention relates to a method of manufacturing a semiconductor device, wherein an insulating film is formed on a semiconductor substrate, a photoresist pattern is formed only in an inactive region of the semiconductor substrate, and then the insulating film is etched by an etching process using the photoresist pattern and the photoresist pattern After removing the oxide, the conductive layer is formed on the entire surface of the insulating layer to be thicker than the thickness of the insulating layer, and the conductive layer is etched by the etch back process to planarize to the same height as the insulating layer, thereby improving the characteristics of the transistor. It is a technology that can prevent naching generated in a later process, shorten the process, improve the reliability and yield of the semiconductor device, and improve the productivity of the semiconductor device.
Description
제1(a)도 내지 제1(e)도는 종래 기술에 따른 반도체소자의 소자분리절연막 제조공정을 도시한 단면도.1 (a) to 1 (e) are cross-sectional views showing a device isolation insulating film manufacturing process of a semiconductor device according to the prior art.
제2(a)도 내지 제1(d)도는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 제조공정을 도시한 단면도.2 (a) to 1 (d) are cross-sectional views showing a device isolation insulating film manufacturing process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,31 : 반도체기판 13,13',33 : 산화막11,31: semiconductor substrate 13,13 ', 33: oxide film
15,39 : 감광막 17,41 : 마스크15,39 photosensitive film 17,41 mask
19,35 : 다결정실리콘막 37 : 실리콘질화막19,35 polysilicon film 37 silicon nitride film
43 : 광원 45 : 소자분리절연막43: light source 45: device isolation insulating film
본 발명은 반도체소자의 소자분리절연막 제조방법에 관한 것으로, 특히 반도체기판 상부에 마스크를 이용하여 절연막패턴을 형성하고 상기 절연막패턴과 같은 높이로 다결정실리콘막을 형성함으로써 상부 구조를 평탄화시켜 후공정을 용이하게 하는 반도체소자의 소자분리절연막 제조 기술에 관한 것이다.The present invention relates to a method for manufacturing a device isolation insulating film of a semiconductor device, and in particular, an insulating film pattern is formed on a semiconductor substrate using a mask, and a polysilicon film is formed at the same height as the insulating film pattern to planarize the upper structure, thereby facilitating post-processing. The present invention relates to a device isolation insulating film manufacturing technology for semiconductor devices.
종래 기술은, 반도체기판 상부에 산화막, 다결정실리콘막 및 실리콘질화막을 순차적으로 형성한다. 그리고, 소자분리절연막을 형성하기 위한 마스크를 이용하여 상기 실리콘질화막, 다결정실리콘막 및 산화막을 순차적으로 식각한다. 그리고, 소자분리절연막을 성장시켜 형성한다. 이때, 상기 소자분리절연막은 에지 부분에는 버즈빅(bird's beak)이 형성되고 중심부분은 볼록하게 형성된다.In the prior art, an oxide film, a polycrystalline silicon film and a silicon nitride film are sequentially formed on a semiconductor substrate. The silicon nitride film, the polycrystalline silicon film, and the oxide film are sequentially etched using a mask for forming a device isolation insulating film. Then, the device isolation insulating film is grown. In this case, a bird's beak is formed at an edge portion of the device isolation insulating layer, and a central portion thereof is formed convexly.
그러나, 종래 기술은 응력이 큰 실리콘질화막을 사용함으로써 결정결함이 발생된다. 그리고, 상기 버즈빅이 발생되어 반도체소자의 특성을 저하시킨다. 그리고, 상기 볼록한 소자분리절연막에 의하여 후공정에서 마스크를 이용한 노광공정시 상기 볼록한 부분에서 광원이 반사되어 균일한 감광막패턴을 형성하지 못하고 나칭(nothing)이 발생된 불량 감광막패턴이 형성된다.However, in the prior art, crystal defects are generated by using a silicon nitride film having a large stress. In addition, the buzz is generated to reduce the characteristics of the semiconductor device. The convex element isolation insulating film is used to reflect a light source at the convex portion during an exposure process using a mask in a later process to form a uniform photoresist pattern, and to form a poor photoresist pattern in which nothing occurs.
이로 인하여, 종래 기술을 이용하여 반도체소자를 형성하는 경우, 반도체소자의 신뢰성이 저하되고, 반도체소자의 수율이 저하되는 문제점이 있다.For this reason, when the semiconductor device is formed using the conventional technology, there is a problem that the reliability of the semiconductor device is lowered and the yield of the semiconductor device is lowered.
제1(a)도 내지 제1(e)도는 종래 기술에 따른 반도체소자의 소자분리절연막 형성공정을 도시한 단면도이다.1 (a) to 1 (e) are cross-sectional views showing a device isolation insulating film forming process of a semiconductor device according to the prior art.
제1(a)도를 참조하면, 반도체기판(31) 상부에 패드산화막인 산화막(33)과, 다결정실리콘막(35) 및 실리콘질화막(37)을 순차적으로 형성한다.Referring to FIG. 1A, an oxide film 33, which is a pad oxide film, a polycrystalline silicon film 35, and a silicon nitride film 37 are sequentially formed on the semiconductor substrate 31.
제1(b)도를 참조하면, 상기 실리콘질화막(37) 상부에 감광막을 형성한 후, 소자분리절연막(도시 안됨)을 형성하기 위한 마스크(41)를 이용하여 상기 감광막(39)을 빛을 광원(43)으로 하여 선택노광한다.Referring to FIG. 1B, after the photoresist layer is formed on the silicon nitride layer 37, the photoresist layer 39 is lighted by using a mask 41 for forming an isolation layer (not shown). Selective exposure is made with the light source 43.
제1(c)도를 참조하면, 상기 제1(b)도의 공정후에 상기 감광막(39)을 현상하여 감광막(39)패턴을 형성한다. 그리고, 상기 감광막(39)패턴을 마스크로 하여 상기 실리콘질화막(37), 다결정실리콘막(35) 및 산화막(33)을 순차적으로 식각한다. 이로 인하여, 상기 반도체기판(31)의 비활성영역이 노출된다. 그리고, 상기 감광막(39)패턴을 제거한다.Referring to FIG. 1 (c), after the process of FIG. 1 (b), the photoresist film 39 is developed to form a photoresist 39 pattern. The silicon nitride film 37, the polycrystalline silicon film 35, and the oxide film 33 are sequentially etched using the photosensitive film 39 pattern as a mask. As a result, the inactive region of the semiconductor substrate 31 is exposed. Then, the photoresist 39 pattern is removed.
제1(d)도를 참조하면, 상기 노출된 반도체기판(31)을 상에 산화막을 열성장시켜 소자분리절연막(45)을 형성한다. 이때, 상기 소자분리절연막(45)은 상기 반도체기판(31)의 활성영역 쪽으로 버즈빅이 형성된다. 상기 버즈빅으로 인하여 트랜지스터(transistor)의 특성이 저하된다. 그리고, 상기 소자분리절연막(45)은 중앙 부분이 볼록하게 형성된다. 그로 인하여, 후공정에서 노광 및 현상공정시 나칭의 문제점이 발생할 수 있다.Referring to FIG. 1 (d), an isolation film 45 is formed by thermally growing an oxide film on the exposed semiconductor substrate 31. In this case, the device isolation insulating layer 45 has a buzz bend toward the active region of the semiconductor substrate 31. Due to the buzz big, the characteristics of the transistor are degraded. In addition, a center portion of the device isolation insulating film 45 is formed to be convex. Therefore, a problem of naching may occur during the exposure and development processes in a later process.
따라서, 본 발명은 종래 기술의 문제점을 해결하기 위하여, 반도체기판 상부에 마스크를 이용한 식각공정으로 경사면이 없는 산화막을 형성하고 상기 산화막과 같은 높이로 도전층을 형성함으로써 후공정을 용이하게 실시할 수 있어 반도체소자의 신뢰성 및 수율을 향상시킬 수 있는 반도체소자의 소자분리절연막 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the post-process can be easily performed by forming an oxide film having no inclined surface in the etching process using a mask on the semiconductor substrate and forming a conductive layer at the same height as the oxide film. Accordingly, an object of the present invention is to provide a method for manufacturing a device isolation insulating film of a semiconductor device capable of improving the reliability and yield of the semiconductor device.
이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 절연막을 형성하는 공정과, 상기 절연막 상부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로 하여 상기 절연막을 식각하여 절연막패턴을 형성하는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면상부에 도전층을 형성하는 공정과, 상기 도전층을 식각 함으로써 상기 절연막패턴이 노출되도록 평탄화하는 것이다.A feature of the present invention for achieving the above object is a step of forming an insulating film on the semiconductor substrate, a step of forming a photosensitive film pattern on the insulating film, and etching the insulating film using the photosensitive film pattern as a mask to form an insulating film pattern A process of forming, a process of removing the photoresist pattern, a process of forming a conductive layer on the entire surface, and a planarization so that the insulating film pattern is exposed by etching the conductive layer.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도 내지 제2(d)도는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성공정을 도시한 단면도이다.2 (a) to 2 (d) are cross-sectional views illustrating a process of forming a device isolation insulating film of a semiconductor device according to an embodiment of the present invention.
제2(a)도를 참조하면, 반도체기판(11) 상부에 산화막(13)을 형성한다. 이때, 상기 산화막(13)은 패드산화막으로서 상기 반도체기판(11)을 산화시켜 형성된 실리콘산화막이다. 그 다음에, 상기 산화막(13) 상부에 감광막(15)을 형성한다. 그리고, 종래 기술에서 사용된 마스크(41)와는 광차단막 패턴의 상이 반전된 마스크(17)를 이용하여 상기 감광막(15)을 선택노광한다.Referring to FIG. 2A, an oxide film 13 is formed on the semiconductor substrate 11. In this case, the oxide film 13 is a silicon oxide film formed by oxidizing the semiconductor substrate 11 as a pad oxide film. Next, a photosensitive film 15 is formed on the oxide film 13. Then, the photosensitive film 15 is selectively exposed using a mask 17 in which the image of the light blocking film pattern is inverted from that of the mask 41 used in the related art.
제2(b)도를 참조하면, 상기 노광된 감광막(15)을 현상하여 감광막(15)패턴을 형성한다. 그리고, 상기 감광막(15)패턴을 마스크로 하여 상기 산화막(13)을 식각하여 산화막패턴(13')을 형성한다. 그리고, 상기 감광막(15)패턴을 제거한다.Referring to FIG. 2B, the exposed photosensitive film 15 is developed to form a photosensitive film 15 pattern. The oxide film 13 is etched using the photosensitive film 15 pattern as a mask to form an oxide film pattern 13 ′. Then, the photosensitive film 15 pattern is removed.
제2(c)도를 참조하면, 전체표면상부에 다결정실리콘막(19)을 형성한다. 여기서는 상기 산화막(13)보다 두껍게 형성한다.Referring to FIG. 2 (c), a polysilicon film 19 is formed over the entire surface. It is formed thicker than the oxide film 13 here.
제2(d)도를 참조하면, 상기 다결정실리콘막(19)을 에치백(etch back) 공정으로 상기 산화막패턴(13')이 노출되도록 상부구조를 평탄화시킨다. 그리고, 후공정에서 상기 산화막패턴(13')을 소자분리절연막으로 사용한다.Referring to FIG. 2 (d), the upper structure is planarized so that the oxide film pattern 13 ′ is exposed by etching back the polysilicon film 19. In the later step, the oxide film pattern 13 ′ is used as a device isolation insulating film.
후속공정을 실시함으로써 효과가 향상된 반도체소자를 용이하게 형성할 수 있다.By performing the subsequent steps, it is possible to easily form a semiconductor device having an improved effect.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리절연막 제조방법은, 반도체기판 상부에 절연막을 형성하고 그 상부에 감광막을 형성한 다음, 마스크를 이용한 식각공정으로 상기 반도체기판의 비활성영역에만 절연막을 형성하고 전체표면상부에 도전층을 두껍게 형성한 다음, 이를 에치백하여 평탄화시킴으로써 후공정을 용이하게 하고 실리콘질화막을 사용하지 않음으로써 결정결함이 발생되지 않고 후공정에서도 나칭 발생의 염려가 없어 반도체소자의 신뢰성 및 수율을 향상시킬 수 있고 공정을 단축시킴으로써 생산성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a device isolation insulating film of a semiconductor device according to the present invention, an insulating film is formed on the semiconductor substrate, a photoresist film is formed on the semiconductor substrate, and an etching process using a mask is used to insulate the insulating film only in the inactive region of the semiconductor substrate. And a thick conductive layer on the entire surface, and then etched back to planarize to facilitate post-processing, and by not using a silicon nitride film, crystal defects do not occur and there is no fear of naching in the post-process. The reliability and yield of the device can be improved and the productivity can be improved by shortening the process.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037488A KR0146257B1 (en) | 1994-12-27 | 1994-12-27 | Method for manufacturing the insulation film of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037488A KR0146257B1 (en) | 1994-12-27 | 1994-12-27 | Method for manufacturing the insulation film of semiconductor device |
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| KR960026568A KR960026568A (en) | 1996-07-22 |
| KR0146257B1 true KR0146257B1 (en) | 1998-11-02 |
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| KR1019940037488A KR0146257B1 (en) | 1994-12-27 | 1994-12-27 | Method for manufacturing the insulation film of semiconductor device |
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