[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPWO2006062195A1 - Semiconductor mounting board - Google Patents

Semiconductor mounting board Download PDF

Info

Publication number
JPWO2006062195A1
JPWO2006062195A1 JP2006546774A JP2006546774A JPWO2006062195A1 JP WO2006062195 A1 JPWO2006062195 A1 JP WO2006062195A1 JP 2006546774 A JP2006546774 A JP 2006546774A JP 2006546774 A JP2006546774 A JP 2006546774A JP WO2006062195 A1 JPWO2006062195 A1 JP WO2006062195A1
Authority
JP
Japan
Prior art keywords
wiring pattern
semiconductor
semiconductor chip
resin
dummy wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006546774A
Other languages
Japanese (ja)
Inventor
理仁 川端
理仁 川端
義人 冨士原
義人 冨士原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Publication of JPWO2006062195A1 publication Critical patent/JPWO2006062195A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

本発明の課題は、半導体実装基板の非電極配置部に、電極配線と同じ配線を設けることで、樹脂封止を均一化し、半導体チップのフリップチップ実装の高信頼性を実現することである。 実装基板（１００）に、半導体チップの電極パッド（１０６）の存在しない辺の中央部に、電極配線を構成する配線パターン（１０１）と同じ仕様のダミー配線パターン（１０３）を設けることにより、封止樹脂（１０５）の半導体チップ（１０４）端面への這い上がりを良好にしたことで、封止樹脂の不濡れを防止し、確実な封止を可能にする。An object of the present invention is to provide the same wiring as the electrode wiring in the non-electrode arrangement portion of the semiconductor mounting substrate, thereby uniformizing the resin sealing and realizing high reliability of flip chip mounting of the semiconductor chip. A dummy wiring pattern (103) having the same specifications as the wiring pattern (101) constituting the electrode wiring is provided on the mounting substrate (100) at the center of the side where the electrode pad (106) of the semiconductor chip does not exist, thereby sealing the mounting substrate (100). Since the creeping of the stop resin (105) to the end face of the semiconductor chip (104) is made good, non-wetting of the sealing resin is prevented and reliable sealing is possible.

Description

本発明は、半導体実装基板に係り、特に半導体チップを実装するプリント配線基板の配線パターンに関するものである。  The present invention relates to a semiconductor mounting board, and more particularly to a wiring pattern of a printed wiring board on which a semiconductor chip is mounted.

半導体装置の高密度化、小型化を達成するため、半導体チップの基板への実装にフリップチップ実装が多く採用されている。フリップチップ実装は、半導体チップをベアのまま基板配線パターン上にフェイスダウン状態で実装する方式である。  In order to achieve higher density and smaller size of semiconductor devices, flip chip mounting is often used for mounting semiconductor chips on a substrate. Flip chip mounting is a method in which a semiconductor chip is mounted in a face-down state on a substrate wiring pattern while being bare.

この半導体チップの電極配置は、外周部に１列、乃至、２列にペリフェラル配置（４辺全辺配置）しているものが、大部分であるが、固体撮像素子やＲＡＭ・ＲＯＭなどは、対向する２辺のみに配置されていたり、コの字状に配置されているものもある。例えば一例を図５に示すように、実装基板３００には、電極配線を構成する配線パターン３０１のみ存在しており、半導体チップ側に電極が形成されていない領域にはパターンが存在しない。  Most of the electrode arrangement of this semiconductor chip is one row on the outer peripheral part or peripheral arrangement (two sides on all sides) in two rows, but the solid-state imaging device, RAM / ROM, etc. Some are arranged only on two opposite sides, or arranged in a U-shape. For example, as shown in FIG. 5, for example, only the wiring pattern 301 constituting the electrode wiring exists on the mounting substrate 300, and no pattern exists in a region where no electrode is formed on the semiconductor chip side.

このようなペリフェラル配置でない、半導体チップを実装基板に実装し、接続領域周辺を樹脂封止する場合、図６（ａ）および（ｂ）に示すように、電極パッド３０６が存在する辺と電極パッドが存在しない辺で、封止形状が非対称性となったり、封止樹脂３０５がうまく半導体チップ３０４端面に濡れあがらないという問題があった。
この問題を避けるため、例えば２辺のみに電極配置された固体撮像素子の実装において、電極のない部分にダミー配線をチップ端面と平行に配置する方法（特許文献１）が提案されている。When a semiconductor chip that is not in such a peripheral arrangement is mounted on a mounting substrate and the periphery of the connection region is resin-sealed, as shown in FIGS. 6A and 6B, the side where the electrode pad 306 exists and the electrode pad There is a problem that the sealing shape becomes asymmetrical on the side where no sigma exists, or the sealing resin 305 does not wet well on the end face of the semiconductor chip 304.
In order to avoid this problem, for example, in mounting a solid-state imaging device in which electrodes are arranged on only two sides, a method (Patent Document 1) is proposed in which dummy wirings are arranged in parallel with the chip end face in a portion without electrodes.

これは一例を、図７に示すように、基板４００には、半導体チップの電極パッドと相対向するように設けられる電極配線を構成する配線パターン４０１以外に半導体の端面に平行になるようにダミー配線パターン４０３を設ける手法である。この場合、図８（ａ）および（ｂ）に示すように、シート状またはペースト状の封止樹脂４０５を先に実装基板４００上に供給し、その後、半導体チップ４０４を熱圧着方式で実装する方法で行われている。このようなダミー配線を設けた場合、電極パッドを形成しない辺に沿って連続的にダミーパターンが形成されており、熱圧着時の樹脂の温度がダミー配線パターン４０３を伝わって放熱し、また、熱伝導が良いダミー配線部から高温になり、開口部４０２の周縁で樹脂が硬化してしまうため、依然として半導体チップ４０４端面に濡れあがるように形成することは困難であった。  As an example, as shown in FIG. 7, a dummy is provided on a substrate 400 so as to be parallel to the end face of the semiconductor other than the wiring pattern 401 constituting the electrode wiring provided to face the electrode pad of the semiconductor chip. This is a method of providing a wiring pattern 403. In this case, as shown in FIGS. 8A and 8B, a sheet-like or paste-like sealing resin 405 is first supplied onto the mounting substrate 400, and then the semiconductor chip 404 is mounted by a thermocompression bonding method. Is done in the way. When such a dummy wiring is provided, a dummy pattern is continuously formed along the side where the electrode pad is not formed, and the temperature of the resin at the time of thermocompression is transmitted through the dummy wiring pattern 403 to dissipate heat. Since the temperature of the dummy wiring portion having good heat conduction becomes high and the resin is cured at the periphery of the opening 402, it is still difficult to form the resin so as to wet the end surface of the semiconductor chip 404.

特許第３２０７３１９号Japanese Patent No. 3307319

上述したように、電極パッドの形成されていない辺に対向する領域には何も設けない従来の方法では、図６に工程フローを示す通り、封止樹脂３０５は、凹部で半導体チップ３０４にうまく濡れあがらないため、気泡（ボイド）Ｖとなり、封止がうまくいかない。  As described above, in the conventional method in which nothing is provided in the region facing the side where the electrode pad is not formed, the sealing resin 305 is applied to the semiconductor chip 304 at the recess as shown in the process flow in FIG. Since it does not get wet, it becomes a void (Void) V and sealing is not successful.

また、特許文献１の方法では、図８に示した工程フローの通り、封止樹脂４０５には、凹部がほとんど存在しないため、封止樹脂４０５は、容易にチップ４０４へ濡れあがるが、熱圧着工程でダミー配線４０３へ熱が逃げてしまい、かつダミー配線パターン４０３が最も高温となるため、封止樹脂４０５が、局部的に高温となり、粘度が低下してしまうため、半導体チップ４０４端面への這い上がり量が小さくなり、樹脂封止が均等にならない。さらに、前記熱の逃げのため、樹脂温度を狙い値（１００〜２５０℃）まで上げるためには、半導体チップ４０４の加熱温度を必要以上に高く設定する必要がある。これは、樹脂そのものに歪みを生じさせるばかりでなく、チップに耐熱性という制約を与えることになる。  Further, in the method of Patent Document 1, as shown in the process flow shown in FIG. 8, the sealing resin 405 has almost no recess, and the sealing resin 405 easily wets the chip 404. Since the heat escapes to the dummy wiring 403 in the process and the dummy wiring pattern 403 is the highest temperature, the sealing resin 405 is locally high temperature and the viscosity is lowered. The amount of scooping is reduced and the resin sealing is not even. Furthermore, in order to increase the resin temperature to a target value (100 to 250 ° C.) for the heat escape, it is necessary to set the heating temperature of the semiconductor chip 404 higher than necessary. This not only causes distortion in the resin itself, but also imposes a restriction of heat resistance on the chip.

このように、従来の方法では、ダミー配線を設けた場合にも、ダミー配線が実装条件を制約し、品質の良い半導体実装構造を実現できなかった。
本発明は、前記実情に鑑みてなされたもので、実装条件の制約を排除し、効率よく接着および樹脂封止を行うことができ、高品質の半導体実装構造を実現する半導体実装基板を実現することを目的とする。As described above, in the conventional method, even when the dummy wiring is provided, the dummy wiring restricts the mounting conditions, and a high-quality semiconductor mounting structure cannot be realized.
The present invention has been made in view of the above circumstances, and realizes a semiconductor mounting substrate that eliminates restrictions on mounting conditions, can efficiently perform adhesion and resin sealing, and realizes a high-quality semiconductor mounting structure. For the purpose.

そこで本発明の半導体実装基板は、ベアの半導体チップをフェースダウンでフリップチップ実装する半導体実装基板であって、前記半導体チップの電極配置部に対向するとともに外部接続のなされる配線パターンと、前記半導体チップの非電極配置部に、前記半導体チップの辺に対して所定の角度をなすように設けられたダミー配線パターンとをしたことを特徴とする。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が半導体チップの端部側面（以下端面）に均一に這い上がり、かつ、実装を熱圧着方式で行った場合は、封止樹脂への熱伝導が均一になるので、半導体チップ全周の樹脂封止を均一に実現することができ、高品質の半導体実装構造を実現できる。ここで半導体チップの辺に対して所定の角度をなすようにとは、辺に平行とならないようにダミー配線パターンを形成することをいうものとする。望ましくは辺に直交するような形状にする。これによりダミー配線パターン周辺領域すなわち、ダミー配線パターンのない領域も存在することになり、ダミー配線パターンで高さを均一にするとともに、ダミー配線パターンの両サイドと半導体チップとの間の領域では、熱圧着時に配線パターンを介して樹脂温度が低下するのが抑制され、半導体チップの周縁部に効率よく樹脂の這い上がりを実現する。これに対し各辺に沿って平行にダミー配線パターンを設けた場合、ダミー配線パターンに沿った領域でダミー配線パターンによる放熱により、樹脂温度が低下し、その結果十分な封止強度を得ることができないことがある。Accordingly, the semiconductor mounting substrate of the present invention is a semiconductor mounting substrate for flip-chip mounting a bare semiconductor chip face down, a wiring pattern facing the electrode placement portion of the semiconductor chip and being externally connected, and the semiconductor The non-electrode arrangement portion of the chip is provided with a dummy wiring pattern provided so as to form a predetermined angle with respect to the side of the semiconductor chip.
With this configuration, when the semiconductor mounting is performed using the sealing resin, the sealing resin crawls uniformly on the end side surface (hereinafter referred to as the end surface) of the semiconductor chip, and when the mounting is performed by a thermocompression bonding method, Since the heat conduction to the sealing resin becomes uniform, the resin sealing around the entire circumference of the semiconductor chip can be realized uniformly, and a high-quality semiconductor mounting structure can be realized. Here, to make a predetermined angle with respect to the side of the semiconductor chip means to form a dummy wiring pattern so as not to be parallel to the side. Desirably, the shape is orthogonal to the side. As a result, there is a dummy wiring pattern peripheral region, that is, a region without a dummy wiring pattern, and the dummy wiring pattern has a uniform height, and in the region between both sides of the dummy wiring pattern and the semiconductor chip, It is possible to suppress the resin temperature from being lowered through the wiring pattern during thermocompression bonding, and to efficiently creep up the resin at the peripheral portion of the semiconductor chip. On the other hand, when a dummy wiring pattern is provided in parallel along each side, the resin temperature decreases due to heat radiation by the dummy wiring pattern in the region along the dummy wiring pattern, and as a result, sufficient sealing strength can be obtained. There are things that cannot be done.

また、本発明の半導体実装基板は、前記ダミー配線パターンが、前記配線パターンと対称となる方向に設けられたものを含む。
この構成によれば、配線パターンの形成された辺と同様の樹脂封止形状を得ることができる。また、形状も対称であるのが望ましいくこれにより、配線パターンのある辺とダミー配線パターンの形成された辺（配線パターンのない辺）とで同様の状態をつくり出すことができる。In addition, the semiconductor mounting substrate of the present invention includes a substrate in which the dummy wiring pattern is provided in a direction symmetrical to the wiring pattern.
According to this configuration, it is possible to obtain a resin sealing shape similar to the side where the wiring pattern is formed. Further, it is desirable that the shapes are also symmetric, so that a similar state can be created between a side having a wiring pattern and a side having a dummy wiring pattern (side having no wiring pattern).

また、本発明の半導体実装基板は、前記ダミー配線パターンが、前記配線パターンと同様に同一工程で形成されたものを含む。
この構成によれば、エッチングに用いられるマスクを一部変更するのみで容易に形成でき、より配線パターンの形成された辺と近い状態の樹脂封止形状を得ることができる。In addition, the semiconductor mounting substrate of the present invention includes a substrate in which the dummy wiring pattern is formed in the same process as the wiring pattern.
According to this configuration, it is possible to easily form the mask used for etching only by partially changing it, and it is possible to obtain a resin-sealed shape that is closer to the side where the wiring pattern is formed.

また、本発明の半導体実装基板は、前記半導体チップが、相対向する２辺に電極配置部を具備しており、前記ダミー配線パターンが、前記２辺を除く２辺の中央部に設けられたものを含む。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できるため、高品質の半導体実装構造を実現できる。かつ、実装を熱圧着方式で行った場合は、熱伝導が最も高い基板配線からの熱の逃げが最小限に抑制できるので、半導体チップの加熱温度を低く設定でき、半導体チップへの熱ストレス緩和と、熱歪みの少ない半導体実装構造を実現できる。Further, in the semiconductor mounting substrate of the present invention, the semiconductor chip has an electrode arrangement portion on two opposite sides, and the dummy wiring pattern is provided in a central portion of two sides excluding the two sides. Including things.
With this configuration, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl, and the resin sealing of the entire circumference of the semiconductor chip can be realized with a voidless, high quality The semiconductor mounting structure can be realized. In addition, when mounting by thermocompression bonding, the heat escape from the substrate wiring with the highest thermal conductivity can be minimized, so the heating temperature of the semiconductor chip can be set low, and the thermal stress on the semiconductor chip can be reduced. A semiconductor mounting structure with less thermal distortion can be realized.

また、本発明の半導体装置実装基板は、前記半導体チップが、コの字形状をなすように３辺に電極配置部を具備しており、前記ダミー配線パターンは、残る１辺のほぼ中央部に、設けられたものを含む。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できるので、品質の良い半導体実装構造を実現できる。かつ、実装を熱圧着方式で行った場合は、熱伝導が最も高い基板配線からの熱の逃げが最小限に抑制できるので、半導体チップの加熱温度を低く設定でき、半導体チップへの熱ストレス緩和と、熱歪みの少ない半導体実装構造を実現できる。In the semiconductor device mounting substrate of the present invention, the semiconductor chip has an electrode arrangement portion on three sides so that the U-shape is formed in a U shape, and the dummy wiring pattern is substantially at the center of the remaining one side. , Including those provided.
With this configuration, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl up, and the resin sealing of the entire circumference of the semiconductor chip can be realized in a voidless manner. A good semiconductor mounting structure can be realized. In addition, when mounting by thermocompression bonding, the heat escape from the substrate wiring with the highest thermal conductivity can be minimized, so the heating temperature of the semiconductor chip can be set low, and the thermal stress on the semiconductor chip can be reduced. A semiconductor mounting structure with less thermal distortion can be realized.

また、本発明の半導体実装基板は、ベアの半導体チップをフェースダウンでフリップチップ実装する基板において、前記半導体チップの非電極配置部に対向する前記基板の配線パターンが、非電極配置辺に複数本あることを特徴とする。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できるので、品質の良い半導体実装構造を実現できる。Further, the semiconductor mounting substrate of the present invention is a substrate on which a bare semiconductor chip is flip-chip mounted face down, and a plurality of wiring patterns of the substrate facing the non-electrode arrangement portion of the semiconductor chip are provided on the non-electrode arrangement side. It is characterized by being.
With this configuration, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl up, and the resin sealing of the entire circumference of the semiconductor chip can be realized in a voidless manner. A good semiconductor mounting structure can be realized.

また、本発明の半導体実装基板は、前記ダミー配線パターンが、各辺に複数本設けられるものを含む。  In addition, the semiconductor mounting substrate of the present invention includes one in which a plurality of the dummy wiring patterns are provided on each side.

また、本発明の半導体実装基板は、前記ダミー配線パターンが、各辺の中央部に１本のみ設けられるものを含む。  In addition, the semiconductor mounting substrate of the present invention includes one in which only one dummy wiring pattern is provided at the center of each side.

本発明によれば、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できる。  According to the present invention, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl up, and the resin sealing of the entire circumference of the semiconductor chip can be realized with a voidless.

また、本発明によれば、封止樹脂を用いて半導体実装熱圧着方式で行った場合は、熱伝導が最も高い基板配線からの熱の逃げが最小限に抑制できるので、半導体チップの加熱温度を低く設定でき、半導体チップへの熱ストレス緩和と、熱歪みの少ない半導体実装構造を実現することができる。
上記効果から、本発明によれば、高品質の半導体実装構造を実現できる。Further, according to the present invention, when the semiconductor mounting thermocompression bonding method is performed using the sealing resin, the heat escape from the substrate wiring having the highest heat conduction can be suppressed to the minimum, so that the heating temperature of the semiconductor chip Can be set low, and it is possible to realize a semiconductor mounting structure with less thermal stress and less thermal strain on the semiconductor chip.
From the above effects, according to the present invention, a high-quality semiconductor mounting structure can be realized.

本発明の第１の実施の形態を示した半導体実装上面図および断面図である。It is the semiconductor mounting top view and sectional drawing which showed the 1st Embodiment of this invention. 本発明の第１の実施の形態を示した実装工程断面図である。It is mounting process sectional drawing which showed the 1st Embodiment of this invention. 本発明の第２の実施の形態を示した基板上面図である。It is the board | substrate top view which showed the 2nd Embodiment of this invention. 本発明の第２の実施の形態を示した実装工程断面図である。It is mounting process sectional drawing which showed the 2nd Embodiment of this invention. 従来技術における基板上面図である。It is a board | substrate top view in a prior art. 従来技術における実装工程断面図である。It is mounting process sectional drawing in a prior art. 従来技術における特許文献１の場合を示した基板上面図である。It is the board | substrate top view which showed the case of the patent document 1 in a prior art. 従来技術における特許文献１の場合を示した実装工程断面図である。It is mounting process sectional drawing which showed the case of patent document 1 in a prior art.

符号の説明Explanation of symbols

１００、２００、３００、４００・・・半導体実装基板
１０１、２０１、３０１、４０１・・・配線パターン
１０２、２０２、３０２、４０２・・・半導体実装基板開口部
１０３、２０３、４０３・・・ダミー配線パターン
１０４、２０４、３０４、４０４・・・半導体チップ
１０５、２０５、３０５、４０５・・・封止樹脂
１０６、２０６、３０６、４０６・・・半導体チップの電極パッド
Ｖ・・・ボイド100, 200, 300, 400 ... Semiconductor mounting substrate 101, 201, 301, 401 ... Wiring pattern 102, 202, 302, 402 ... Semiconductor mounting substrate opening 103, 203, 403 ... Dummy wiring Pattern 104, 204, 304, 404 ... Semiconductor chip 105, 205, 305, 405 ... Sealing resin 106, 206, 306, 406 ... Electrode pad of semiconductor chip V ... Void

以下、本発明の実施の形態について、図面を参照しつつ詳細に説明する。
（実施の形態１）
本実施の形態１の半導体実装基板の要部説明図を図１に示す。
この半導体実装基板は、ベアの半導体チップ１０４をフェースダウンでフリップチップ実装する基板１００において、前記半導体チップ１０４の電極パッド１０６配置部に対向する配線パターン１０１を設け、かつ、前記半導体チップ１０４の非電極配置部にも、前記配線パターン１０１と同等のパターンからなるダミー配線パターン１０３、すなわち、各辺に対して垂直な配線パターンと同様の形状であってかつ同一工程で形成されたパターンを設けた。このダミー配線パターン１０３はこの半導体チップとも外部端子とも電気的接続がなされず浮遊状態になっている。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is an explanatory diagram of a main part of the semiconductor mounting substrate according to the first embodiment.
The semiconductor mounting substrate is a substrate 100 on which a bare semiconductor chip 104 is flip-chip mounted face down, and a wiring pattern 101 facing the electrode pad 106 placement portion of the semiconductor chip 104 is provided, and the semiconductor chip 104 is not mounted. The electrode arrangement portion is also provided with a dummy wiring pattern 103 having a pattern equivalent to the wiring pattern 101, that is, a pattern having the same shape as the wiring pattern perpendicular to each side and formed in the same process. . The dummy wiring pattern 103 is in a floating state without being electrically connected to either the semiconductor chip or the external terminal.

ここでは、前記半導体チップ１０４が、二の字形状に相対向する２辺に電極配置されており、前記半導体実装基板には、半導体チップ１０４の非電極配置辺には、非電極配置辺部に対向する領域の中央部に位置し、かつ１本のみのダミー配線パターン１０３が、配置されている。  Here, the semiconductor chip 104 is electrode-arranged on two sides opposite to each other in a two-letter shape, and the semiconductor mounting substrate has a non-electrode arrangement side on the non-electrode arrangement side. Only one dummy wiring pattern 103 is disposed in the center of the opposing region.

また、半導体実装基板１００は、有機樹脂ベース（ガラスエポキシ、アラミドエポキシ、ＢＴレジン、ポリイミド、液晶ポリマーなど）または、無機材質ベース（ガラス、セラミックなど）からなる。配線電極を構成する配線パターン１０１は、めっき法による配線形成の場合、圧延または電解Ｃｕ箔をベースにＮｉとＡｕを表面にめっき（電解または無電解）されており、配線高さは、２０〜８０μｍである。半導体実装基板１００には、中空実装するための開口部１０２が設けられている。なおこの開口部１０２を形成することなく平板状の半導体実装基板にも適用可能であることはいうまでもない。  The semiconductor mounting substrate 100 is made of an organic resin base (glass epoxy, aramid epoxy, BT resin, polyimide, liquid crystal polymer, etc.) or an inorganic material base (glass, ceramic, etc.). In the case of wiring formation by plating, the wiring pattern 101 constituting the wiring electrode is plated with Ni and Au on the surface of rolled or electrolytic Cu foil (electrolytic or electroless), and the wiring height is 20 to 20 80 μm. The semiconductor mounting substrate 100 is provided with an opening 102 for hollow mounting. Needless to say, the present invention can be applied to a flat semiconductor mounting substrate without forming the opening 102.

ここで、半導体チップ１０４の非電極配置辺に設けたダミー配線パターン１０３は、その形成仕様は、配線電極を構成する配線パターン１０１と同一の仕様（配線材構成、配線厚み、配線幅、表面めっき方法など）であることを特徴としている。  Here, the dummy wiring pattern 103 provided on the non-electrode placement side of the semiconductor chip 104 has the same specifications as the wiring pattern 101 constituting the wiring electrode (wiring material configuration, wiring thickness, wiring width, surface plating). Method).

一方、従来の方法では、図５に示すように基板３００には、電極配線を構成する配線パターン３０１のみ存在しており、ダミー配線パターン（１０３）に相当する配線そのものが存在しないか、図７に示すように、基板４００には、配線電極を構成する配線パターン４０１以外に半導体チップの端面に平行になるようにダミー配線パターン４０３を設ける手法が取られているという違いがある。  On the other hand, in the conventional method, as shown in FIG. 5, only the wiring pattern 301 constituting the electrode wiring exists on the substrate 300, and there is no wiring itself corresponding to the dummy wiring pattern (103). As shown in FIG. 5, the substrate 400 is different from the wiring pattern 401 constituting the wiring electrode in that a dummy wiring pattern 403 is provided so as to be parallel to the end face of the semiconductor chip.

次に、半導体チップ１０４は、Ｓｉ、ＳｉＣ、ＧａＡｓなどからなり、厚みは、０．１〜０．７ｍｍである。半導体チップ１０４の電極パッド１０６は、Ａｕ、Ｃｕ、Ｎｉなどからなり、電極形成方法は、めっき法（電解または無電解）を用い、高さは、５〜２０μｍである。  Next, the semiconductor chip 104 is made of Si, SiC, GaAs or the like and has a thickness of 0.1 to 0.7 mm. The electrode pad 106 of the semiconductor chip 104 is made of Au, Cu, Ni, or the like. The electrode forming method uses a plating method (electrolysis or electroless), and the height is 5 to 20 μm.

そして、半導体チップ１０４は、半導体実装基板１００への実装時、封止樹脂１０５を用いて封止される。この封止樹脂１０５は、エポキシ、イミド、シリコーン、アクリルなどをベースとしており、樹脂を供給する形態は、粘度２０〜１５０Ｐａ・ｓのペースト状もしくは、Ｂステージ化されたフイルム状である。半導体チップ１０４を熱圧着する条件は、１００〜２５０℃を樹脂温度のピークとして、２〜２０秒間圧着する。  The semiconductor chip 104 is sealed with a sealing resin 105 when mounted on the semiconductor mounting substrate 100. The sealing resin 105 is based on epoxy, imide, silicone, acrylic, etc., and the form of supplying the resin is a paste form having a viscosity of 20 to 150 Pa · s or a B-stage film form. The conditions for thermocompression bonding of the semiconductor chip 104 are pressure bonding for 2 to 20 seconds with a resin temperature peak at 100 to 250 ° C.

この電極配置での半導体チップ実装工程のフロー図を図２に示す。
接続用の電極パッド１０６を形成した半導体チップ１０４を、配線パターン１０１に加えて、電極パッドの存在しない辺にダミー配線パターン１０３を設けた、半導体実装基板１００へ実装するフローを示している。A flow chart of the semiconductor chip mounting process with this electrode arrangement is shown in FIG.
A flow is shown in which a semiconductor chip 104 on which connection electrode pads 106 are formed is mounted on a semiconductor mounting substrate 100 in which a dummy wiring pattern 103 is provided on a side where no electrode pad exists in addition to the wiring pattern 101.

ここで、半導体実装基板１００には、あらかじめ、封止樹脂１０５が供給されており、配線パターン１０１およびダミー配線パターン１０３の有無に応じて、封止樹脂１０５は、高さに凹凸ができる。高さの凹凸は配線パターン１０１およびダミー配線パターン１０３に従ったものであり、電極高さ２０〜８０μｍに相当する。封止樹脂１０５は、樹脂厚みが、３０〜１００μｍで、電極高さの和相当となるように供給している。  Here, the sealing resin 105 is supplied to the semiconductor mounting substrate 100 in advance, and the sealing resin 105 can be uneven in height depending on the presence or absence of the wiring pattern 101 and the dummy wiring pattern 103. The height unevenness is in accordance with the wiring pattern 101 and the dummy wiring pattern 103 and corresponds to an electrode height of 20 to 80 μm. The sealing resin 105 is supplied such that the resin thickness is 30 to 100 μm and corresponds to the sum of the electrode heights.

次に、半導体チップ１０４を半導体実装基板１００に載置し（図２（ａ））、熱圧着方式で実装する（図２（ｂ））。この時、封止樹脂１０５の凹凸が電極パッド１０６の高さよりも小さい場合、封止樹脂１０５は、凹部で半導体チップ１０４に濡れあがらないが、配線パターン１０１の間にダミー配線パターン１０３を設けたため、その部分は、樹脂が凸になっており、半導体チップ１０４に濡れあがり、その後は、濡れ広がり、半導体チップ１０４の端面全面を覆う状態となる。  Next, the semiconductor chip 104 is mounted on the semiconductor mounting substrate 100 (FIG. 2A) and mounted by a thermocompression bonding method (FIG. 2B). At this time, when the unevenness of the sealing resin 105 is smaller than the height of the electrode pad 106, the sealing resin 105 does not wet the semiconductor chip 104 by the recess, but the dummy wiring pattern 103 is provided between the wiring patterns 101. The resin is convex in the portion, wets the semiconductor chip 104, and then wets and spreads to cover the entire end face of the semiconductor chip 104.

（実施の形態２）
次に本発明の実施の形態２について説明する。
本実施の形態２の半導体装置の要部説明図を図３に示す。
本実施の形態では、前記半導体チップ２０２が、二の字形状に電極配置されており、非電極配置辺に対向する前記半導体実装基板２００に配線パターン２０１と同一工程で形成されたダミー配線パターン２０３が、各非電極配置辺に３本設けられている。(Embodiment 2)
Next, a second embodiment of the present invention will be described.
FIG. 3 is an explanatory diagram of a main part of the semiconductor device according to the second embodiment.
In the present embodiment, the semiconductor chip 202 has electrodes arranged in a two-letter shape, and the dummy wiring pattern 203 formed in the same process as the wiring pattern 201 on the semiconductor mounting substrate 200 facing the non-electrode arrangement side. Are provided at each non-electrode arrangement side.

ここで、Ａ−Ａ´ラインにおいて配線パターン２０１の上下間距離Ｄを複数のダミー配線パターン２０３で均等に割って配置している。
また、配置するダミー配線パターン２０３の本数は、封止樹脂のチップへの濡れ上がりを均一にするために必要な最小限の数としている。Here, the vertical distance D of the wiring pattern 201 is equally divided by the plurality of dummy wiring patterns 203 in the AA ′ line.
Further, the number of dummy wiring patterns 203 to be arranged is set to a minimum number necessary to make the wetting of the sealing resin to the chip uniform.

この電極配置での半導体チップ実装工程フロー図を図４に示す。
電極パッド２０６を形成した半導体チップ２０４を、電極パッド２０６の存在しない部分に複数のダミー配線パターン２０３を設けた配線パターン２０１を有する半導体実装基板２００に実装するフローを示している。FIG. 4 shows a flow chart of a semiconductor chip mounting process with this electrode arrangement.
A flow of mounting the semiconductor chip 204 on which the electrode pads 206 are formed on the semiconductor mounting substrate 200 having the wiring pattern 201 in which a plurality of dummy wiring patterns 203 are provided in a portion where the electrode pads 206 do not exist is shown.

ここで、基板２００には、あらかじめ、封止樹脂２０５が供給されており、配線パターン２０１の有無に応じて、封止樹脂２０５は、高さに凹凸ができる。高さの凹凸は配線パターン２０１、ダミー配線パターン２０３に従ったものであり、電極高さ２０〜８０μｍに相当する。封止樹脂２０５は、樹脂厚みが、３０〜１００μｍで、電極高さの和相当で供給している。  Here, the sealing resin 205 is supplied to the substrate 200 in advance, and the height of the sealing resin 205 can be uneven depending on the presence or absence of the wiring pattern 201. The height unevenness is in accordance with the wiring pattern 201 and the dummy wiring pattern 203 and corresponds to an electrode height of 20 to 80 μm. The sealing resin 205 has a resin thickness of 30 to 100 μm and is supplied corresponding to the sum of the electrode heights.

次に、半導体チップ２０４を半導体実装基板２００に熱圧着方式で実装する。この時、封止樹脂２０５の凹凸が電極パッド２０６の高さよりも小さい場合、封止２０５は、凹部で半導体チップ２０４に濡れあがらないが、配線パターン２０１の間に複数のダミー配線パターン２０３を設けたため、その部分は、樹脂が凸になっており、半導体チップ２０４に濡れあがり、その後は、濡れ広がり、半導体チップ２０４の端面全面を覆う状態となる。  Next, the semiconductor chip 204 is mounted on the semiconductor mounting substrate 200 by a thermocompression bonding method. At this time, when the unevenness of the sealing resin 205 is smaller than the height of the electrode pad 206, the sealing 205 does not wet the semiconductor chip 204 by the recess, but a plurality of dummy wiring patterns 203 are provided between the wiring patterns 201. For this reason, the resin is convex in that portion, wets the semiconductor chip 204, and then wets and spreads to cover the entire end face of the semiconductor chip 204.

なおダミー配線パターンと配線パターンは対称となるように形成されるのが望ましいが方向のみ対称となるようにしてもよい。すなわち、ダミー配線パターンの形成された辺と配線パターンの形成された辺とは対称となるようにするのが望ましい。  The dummy wiring pattern and the wiring pattern are preferably formed so as to be symmetric, but may be symmetric only in the direction. That is, it is desirable that the side on which the dummy wiring pattern is formed and the side on which the wiring pattern is formed be symmetrical.

本発明を詳細にまた特定の実施態様を参照して説明したが、本発明の精神と範囲を逸脱することなく様々な変更や修正を加えることができることは当業者にとって明らかである。
本出願は、２００４年１２月９日出願の日本特許出願、出願番号２００４−３５６６８９に基づくものであり、その内容はここに参照として取り込まれる。Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.
This application is based on Japanese Patent Application No. 2004-356589 filed on Dec. 9, 2004, the contents of which are incorporated herein by reference.

本発明の半導体実装基板は、半導体電極配置が均等でないあらゆる半導体チップの実装・封止品質の向上を実現しており、特に２辺にしか電極を配置していない場合の多い、固体撮像素子やＲＡＭ・ＲＯＭなどメモリーチップへの利用が有効である。また、確実に安定して実装可能であるため、積層化が求められるＳＩＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）などの半導体パッケージに利用可能である。さらに、高周波モジュール部品や、光モジュール部品など、電極数の少ない半導体チップに対しても、均等に樹脂封止を行なう目的において有効である。  The semiconductor mounting substrate of the present invention realizes improvement in mounting and sealing quality of any semiconductor chip in which the semiconductor electrode arrangement is not uniform, in particular, a solid-state imaging device or the like that often has electrodes arranged only on two sides. Use in memory chips such as RAM and ROM is effective. In addition, since it can be mounted stably and reliably, it can be used for semiconductor packages such as SIP (System in Package) that require stacking. Furthermore, it is effective for the purpose of evenly resin-sealing even a semiconductor chip having a small number of electrodes such as a high-frequency module component or an optical module component.

本発明は、半導体実装基板に係り、特に半導体チップを実装するプリント配線基板の配線パターンに関するものである。   The present invention relates to a semiconductor mounting board, and more particularly to a wiring pattern of a printed wiring board on which a semiconductor chip is mounted.

半導体装置の高密度化、小型化を達成するため、半導体チップの基板への実装にフリップチップ実装が多く採用されている。フリップチップ実装は、半導体チップをベアのまま基板配線パターン上にフェイスダウン状態で実装する方式である。   In order to achieve higher density and smaller size of semiconductor devices, flip chip mounting is often used for mounting semiconductor chips on a substrate. Flip chip mounting is a method in which a semiconductor chip is mounted in a face-down state on a substrate wiring pattern while being bare.

この半導体チップの電極配置は、外周部に１列、乃至、２列にペリフェラル配置（４辺全辺配置）しているものが、大部分であるが、固体撮像素子やＲＡＭ・ＲＯＭなどは、対向する２辺のみに配置されていたり、コの字状に配置されているものもある。例えば一例を図５に示すように、実装基板３００には、電極配線を構成する配線パターン３０１のみ存在しており、半導体チップ側に電極が形成されていない領域にはパターンが存在しない。   Most of the electrode arrangement of this semiconductor chip is one row on the outer peripheral part or peripheral arrangement (two sides on all sides) in two rows, but the solid-state imaging device, RAM / ROM, etc. Some are arranged only on two opposite sides, or arranged in a U-shape. For example, as shown in FIG. 5, for example, only the wiring pattern 301 constituting the electrode wiring exists on the mounting substrate 300, and no pattern exists in a region where no electrode is formed on the semiconductor chip side.

このようなペリフェラル配置でない、半導体チップを実装基板に実装し、接続領域周辺を樹脂封止する場合、図６（ａ）および（ｂ）に示すように、電極パッド３０６が存在する辺と電極パッドが存在しない辺で、封止形状が非対称性となったり、封止樹脂３０５がうまく半導体チップ３０４端面に濡れあがらないという問題があった。
この問題を避けるため、例えば２辺のみに電極配置された固体撮像素子の実装において、電極のない部分にダミー配線をチップ端面と平行に配置する方法（特許文献１）が提案されている。 When a semiconductor chip that is not in such a peripheral arrangement is mounted on a mounting substrate and the periphery of the connection region is resin-sealed, as shown in FIGS. 6A and 6B, the side where the electrode pad 306 exists and the electrode pad There is a problem that the sealing shape becomes asymmetrical on the side where no sigma exists, or the sealing resin 305 does not wet well on the end face of the semiconductor chip 304.
In order to avoid this problem, for example, in mounting a solid-state imaging device in which electrodes are arranged on only two sides, a method (Patent Document 1) is proposed in which dummy wirings are arranged in parallel with the chip end face in a portion without electrodes.

これは一例を、図７に示すように、基板４００には、半導体チップの電極パッドと相対向するように設けられる電極配線を構成する配線パターン４０１以外に半導体の端面に平行になるようにダミー配線パターン４０３を設ける手法である。この場合、図８（ａ）および（ｂ）に示すように、シート状またはペースト状の封止樹脂４０５を先に実装基板４００上に供給し、その後、半導体チップ４０４を熱圧着方式で実装する方法で行われている。このようなダミー配線を設けた場合、電極パッドを形成しない辺に沿って連続的にダミーパターンが形成されており、熱圧着時の樹脂の温度がダミー配線パターン４０３を伝わって放熱し、また、熱伝導が良いダミー配線部から高温になり、開口部４０２の周縁で樹脂が硬化してしまうため、依然として半導体チップ４０４端面に濡れあがるように形成することは困難であった。   As an example, as shown in FIG. 7, a dummy is provided on a substrate 400 so as to be parallel to the end face of the semiconductor other than the wiring pattern 401 constituting the electrode wiring provided to face the electrode pad of the semiconductor chip. This is a method of providing a wiring pattern 403. In this case, as shown in FIGS. 8A and 8B, a sheet-like or paste-like sealing resin 405 is first supplied onto the mounting substrate 400, and then the semiconductor chip 404 is mounted by a thermocompression bonding method. Is done in the way. When such a dummy wiring is provided, a dummy pattern is continuously formed along the side where the electrode pad is not formed, and the temperature of the resin at the time of thermocompression is transmitted through the dummy wiring pattern 403 to dissipate heat. Since the temperature of the dummy wiring portion having good heat conduction becomes high and the resin is cured at the periphery of the opening 402, it is still difficult to form the resin so as to wet the end surface of the semiconductor chip 404.

特許第３２０７３１９号Japanese Patent No. 3307319

上述したように、電極パッドの形成されていない辺に対向する領域には何も設けない従来の方法では、図６に工程フローを示す通り、封止樹脂３０５は、凹部で半導体チップ３０４にうまく濡れあがらないため、気泡（ボイド）Ｖとなり、封止がうまくいかない。   As described above, in the conventional method in which nothing is provided in the region facing the side where the electrode pad is not formed, the sealing resin 305 is applied to the semiconductor chip 304 at the recess as shown in the process flow in FIG. Since it does not get wet, it becomes a void (Void) V and sealing is not successful.

また、特許文献１の方法では、図８に示した工程フローの通り、封止樹脂４０５には、凹部がほとんど存在しないため、封止樹脂４０５は、容易にチップ４０４へ濡れあがるが、熱圧着工程でダミー配線４０３へ熱が逃げてしまい、かつダミー配線パターン４０３が最も高温となるため、封止樹脂４０５が、局部的に高温となり、粘度が低下してしまうため、半導体チップ４０４端面への這い上がり量が小さくなり、樹脂封止が均等にならない。さらに、前記熱の逃げのため、樹脂温度を狙い値（１００〜２５０℃）まで上げるためには、半導体チップ４０４の加熱温度を必要以上に高く設定する必要がある。これは、樹脂そのものに歪みを生じさせるばかりでなく、チップに耐熱性という制約を与えることになる。   Further, in the method of Patent Document 1, as shown in the process flow shown in FIG. 8, the sealing resin 405 has almost no recess, and the sealing resin 405 easily wets the chip 404. Since the heat escapes to the dummy wiring 403 in the process and the dummy wiring pattern 403 is the highest temperature, the sealing resin 405 is locally high temperature and the viscosity is lowered. The amount of scooping is reduced and the resin sealing is not even. Furthermore, in order to increase the resin temperature to a target value (100 to 250 ° C.) for the heat escape, it is necessary to set the heating temperature of the semiconductor chip 404 higher than necessary. This not only causes distortion in the resin itself, but also imposes a restriction of heat resistance on the chip.

このように、従来の方法では、ダミー配線を設けた場合にも、ダミー配線が実装条件を制約し、品質の良い半導体実装構造を実現できなかった。
本発明は、前記実情に鑑みてなされたもので、実装条件の制約を排除し、効率よく接着および樹脂封止を行うことができ、高品質の半導体実装構造を実現する半導体実装基板を実現することを目的とする。 As described above, in the conventional method, even when the dummy wiring is provided, the dummy wiring restricts the mounting conditions, and a high-quality semiconductor mounting structure cannot be realized.
The present invention has been made in view of the above circumstances, and realizes a semiconductor mounting substrate that eliminates restrictions on mounting conditions, can efficiently perform adhesion and resin sealing, and realizes a high-quality semiconductor mounting structure. For the purpose.

そこで本発明の半導体実装基板は、ベアの半導体チップをフェースダウンでフリップチップ実装及び中空実装する半導体実装基板であって、前記半導体チップの電極配置部に対向するとともに外部接続のなされる配線パターンと、前記半導体チップの非電極配置部に、前記半導体チップの辺に対して所定の角度をなすように設けられたダミー配線パターンと、前記配線パターン及び前記ダミー配線パターンに周囲を囲まれている開口部と、をしたことを特徴とする。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が半導体チップの端部側面（以下端面）に均一に這い上がり、かつ、実装を熱圧着方式で行った場合は、封止樹脂への熱伝導が均一になるので、半導体チップ全周の樹脂封止を均一に実現することができ、高品質の半導体実装構造を実現できる。ここで半導体チップの辺に対して所定の角度をなすようにとは、辺に平行とならないようにダミー配線パターンを形成することをいうものとする。望ましくは辺に直交するような形状にする。これによりダミー配線パターン周辺領域すなわち、ダミー配線パターンのない領域も存在することになり、ダミー配線パターンで高さを均一にするとともに、ダミー配線パターンの両サイドと半導体チップとの間の領域では、熱圧着時に配線パターンを介して樹脂温度が低下するのが抑制され、半導体チップの周縁部に効率よく樹脂の這い上がりを実現する。これに対し各辺に沿って平行にダミー配線パターンを設けた場合、ダミー配線パターンに沿った領域でダミー配線パターンによる放熱により、樹脂温度が低下し、その結果十分な封止強度を得ることができないことがある。 Accordingly, the semiconductor mounting substrate of the present invention is a semiconductor mounting substrate for flip-chip mounting and hollow mounting of bare semiconductor chips face down, and a wiring pattern that faces the electrode placement portion of the semiconductor chip and is externally connected. A dummy wiring pattern provided in the non-electrode arrangement portion of the semiconductor chip so as to form a predetermined angle with respect to a side of the semiconductor chip, and an opening surrounded by the wiring pattern and the dummy wiring pattern It is characterized by having made a part.
With this configuration, when the semiconductor mounting is performed using the sealing resin, the sealing resin crawls uniformly on the end side surface (hereinafter referred to as the end surface) of the semiconductor chip, and when the mounting is performed by a thermocompression bonding method, Since the heat conduction to the sealing resin becomes uniform, the resin sealing around the entire circumference of the semiconductor chip can be realized uniformly, and a high-quality semiconductor mounting structure can be realized. Here, to make a predetermined angle with respect to the side of the semiconductor chip means to form a dummy wiring pattern so as not to be parallel to the side. Desirably, the shape is orthogonal to the side. As a result, there is a dummy wiring pattern peripheral region, that is, a region without a dummy wiring pattern, and the dummy wiring pattern has a uniform height, and in the region between both sides of the dummy wiring pattern and the semiconductor chip, It is possible to suppress the resin temperature from being lowered through the wiring pattern during thermocompression bonding, and to efficiently creep up the resin at the peripheral portion of the semiconductor chip. On the other hand, when a dummy wiring pattern is provided in parallel along each side, the resin temperature decreases due to heat radiation by the dummy wiring pattern in the region along the dummy wiring pattern, and as a result, sufficient sealing strength can be obtained. There are things that cannot be done.

また、本発明の半導体実装基板は、前記ダミー配線パターンが、前記配線パターンと対称となる方向に設けられたものを含む。
この構成によれば、配線パターンの形成された辺と同様の樹脂封止形状を得ることができる。また、形状も対称であるのが望ましいくこれにより、配線パターンのある辺とダミー配線パターンの形成された辺（配線パターンのない辺）とで同様の状態をつくり出すことができる。 In addition, the semiconductor mounting substrate of the present invention includes a substrate in which the dummy wiring pattern is provided in a direction symmetrical to the wiring pattern.
According to this configuration, it is possible to obtain a resin sealing shape similar to the side where the wiring pattern is formed. Further, it is desirable that the shapes are also symmetric, so that a similar state can be created between a side having a wiring pattern and a side having a dummy wiring pattern (side having no wiring pattern).

また、本発明の半導体実装基板は、前記ダミー配線パターンが、前記配線パターンと同様に同一工程で形成されたものを含む。
この構成によれば、エッチングに用いられるマスクを一部変更するのみで容易に形成でき、より配線パターンの形成された辺と近い状態の樹脂封止形状を得ることができる。 In addition, the semiconductor mounting substrate of the present invention includes a substrate in which the dummy wiring pattern is formed in the same process as the wiring pattern.
According to this configuration, it is possible to easily form the mask used for etching only by partially changing it, and it is possible to obtain a resin-sealed shape that is closer to the side where the wiring pattern is formed.

また、本発明の半導体実装基板は、前記半導体チップが、相対向する２辺に電極配置部を具備しており、前記ダミー配線パターンが、前記２辺を除く２辺の中央部に設けられたものを含む。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できるため、高品質の半導体実装構造を実現できる。かつ、実装を熱圧着方式で行った場合は、熱伝導が最も高い基板配線からの熱の逃げが最小限に抑制できるので、半導体チップの加熱温度を低く設定でき、半導体チップへの熱ストレス緩和と、熱歪みの少ない半導体実装構造を実現できる。 Further, in the semiconductor mounting substrate of the present invention, the semiconductor chip has an electrode arrangement portion on two opposite sides, and the dummy wiring pattern is provided in a central portion of two sides excluding the two sides. Including things.
With this configuration, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl, and the resin sealing of the entire circumference of the semiconductor chip can be realized with a voidless, high quality The semiconductor mounting structure can be realized. In addition, when mounting by thermocompression bonding, the heat escape from the substrate wiring with the highest thermal conductivity can be minimized, so the heating temperature of the semiconductor chip can be set low, and the thermal stress on the semiconductor chip can be reduced. A semiconductor mounting structure with less thermal distortion can be realized.

また、本発明の半導体装置実装基板は、前記半導体チップが、コの字形状をなすように３辺に電極配置部を具備しており、前記ダミー配線パターンは、残る１辺のほぼ中央部に、設けられたものを含む。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できるので、品質の良い半導体実装構造を実現できる。かつ、実装を熱圧着方式で行った場合は、熱伝導が最も高い基板配線からの熱の逃げが最小限に抑制できるので、半導体チップの加熱温度を低く設定でき、半導体チップへの熱ストレス緩和と、熱歪みの少ない半導体実装構造を実現できる。 In the semiconductor device mounting substrate of the present invention, the semiconductor chip has an electrode arrangement portion on three sides so that the U-shape is formed in a U shape, and the dummy wiring pattern is substantially at the center of the remaining one side. , Including those provided.
With this configuration, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl up, and the resin sealing of the entire circumference of the semiconductor chip can be realized in a voidless manner. A good semiconductor mounting structure can be realized. In addition, when mounting by thermocompression bonding, the heat escape from the substrate wiring with the highest thermal conductivity can be minimized, so the heating temperature of the semiconductor chip can be set low, and the thermal stress on the semiconductor chip can be reduced. A semiconductor mounting structure with less thermal distortion can be realized.

また、本発明の半導体実装基板は、ベアの半導体チップをフェースダウンでフリップチップ実装する基板において、前記半導体チップの非電極配置部に対向する前記基板の配線パターンが、非電極配置辺に複数本あることを特徴とする。
この構成により、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できるので、品質の良い半導体実装構造を実現できる。 Further, the semiconductor mounting substrate of the present invention is a substrate on which a bare semiconductor chip is flip-chip mounted face down, and a plurality of wiring patterns of the substrate facing the non-electrode arrangement portion of the semiconductor chip are provided on the non-electrode arrangement side. It is characterized by being.
With this configuration, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip that is most difficult to crawl up, and the resin sealing of the entire circumference of the semiconductor chip can be realized in a voidless manner. A good semiconductor mounting structure can be realized.

また、本発明の半導体実装基板は、前記ダミー配線パターンが、各辺に複数本設けられるものを含む。   In addition, the semiconductor mounting substrate of the present invention includes one in which a plurality of the dummy wiring patterns are provided on each side.

また、本発明の半導体実装基板は、前記ダミー配線パターンが、各辺の中央部に１本のみ設けられるものを含む。   In addition, the semiconductor mounting substrate of the present invention includes one in which only one dummy wiring pattern is provided at the center of each side.

本発明によれば、封止樹脂を用いて半導体実装を行った時、封止樹脂が最も這い上がりにくい半導体チップの端面に這い上がり、半導体チップ全周の樹脂封止がボイドレスで実現できる。   According to the present invention, when semiconductor mounting is performed using a sealing resin, the sealing resin crawls up to the end face of the semiconductor chip which is most difficult to crawl up, and the resin sealing of the entire circumference of the semiconductor chip can be realized with a voidless.

また、本発明によれば、封止樹脂を用いて半導体実装熱圧着方式で行った場合は、熱伝導が最も高い基板配線からの熱の逃げが最小限に抑制できるので、半導体チップの加熱温度を低く設定でき、半導体チップへの熱ストレス緩和と、熱歪みの少ない半導体実装構造を実現することができる。
上記効果から、本発明によれば、高品質の半導体実装構造を実現できる。 Further, according to the present invention, when the semiconductor mounting thermocompression bonding method is performed using the sealing resin, the heat escape from the substrate wiring having the highest heat conduction can be suppressed to the minimum, so that the heating temperature of the semiconductor chip Can be set low, and it is possible to realize a semiconductor mounting structure with less thermal stress and less thermal strain on the semiconductor chip.
From the above effects, according to the present invention, a high-quality semiconductor mounting structure can be realized.

以下、本発明の実施の形態について、図面を参照しつつ詳細に説明する。
（実施の形態１）
本実施の形態１の半導体実装基板の要部説明図を図１に示す。
この半導体実装基板は、ベアの半導体チップ１０４をフェースダウンでフリップチップ実装する基板１００において、前記半導体チップ１０４の電極パッド１０６配置部に対向する配線パターン１０１を設け、かつ、前記半導体チップ１０４の非電極配置部にも、前記配線パターン１０１と同等のパターンからなるダミー配線パターン１０３、すなわち、各辺に対して垂直な配線パターンと同様の形状であってかつ同一工程で形成されたパターンを設けた。このダミー配線パターン１０３はこの半導体チップとも外部端子とも電気的接続がなされず浮遊状態になっている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is an explanatory diagram of a main part of the semiconductor mounting substrate according to the first embodiment.
The semiconductor mounting substrate is a substrate 100 on which a bare semiconductor chip 104 is flip-chip mounted face down, and a wiring pattern 101 facing the electrode pad 106 placement portion of the semiconductor chip 104 is provided, and the semiconductor chip 104 is not mounted. The electrode arrangement portion is also provided with a dummy wiring pattern 103 having a pattern equivalent to the wiring pattern 101, that is, a pattern having the same shape as the wiring pattern perpendicular to each side and formed in the same process. . The dummy wiring pattern 103 is in a floating state without being electrically connected to either the semiconductor chip or the external terminal.

ここでは、前記半導体チップ１０４が、二の字形状に相対向する２辺に電極配置されており、前記半導体実装基板には、半導体チップ１０４の非電極配置辺には、非電極配置辺部に対向する領域の中央部に位置し、かつ１本のみのダミー配線パターン１０３が、配置されている。   Here, the semiconductor chip 104 is electrode-arranged on two sides opposite to each other in a two-letter shape, and the semiconductor mounting substrate has a non-electrode arrangement side on the non-electrode arrangement side. Only one dummy wiring pattern 103 is disposed in the center of the opposing region.

また、半導体実装基板１００は、有機樹脂ベース（ガラスエポキシ、アラミドエポキシ、ＢＴレジン、ポリイミド、液晶ポリマーなど）または、無機材質ベース（ガラス、セラミックなど）からなる。配線電極を構成する配線パターン１０１は、めっき法による配線形成の場合、圧延または電解Ｃｕ箔をベースにＮｉとＡｕを表面にめっき（電解または無電解）されており、配線高さは、２０〜８０μｍである。半導体実装基板１００には、中空実装するための開口部１０２が設けられている。なおこの開口部１０２を形成することなく平板状の半導体実装基板にも適用可能であることはいうまでもない。   The semiconductor mounting substrate 100 is made of an organic resin base (glass epoxy, aramid epoxy, BT resin, polyimide, liquid crystal polymer, etc.) or an inorganic material base (glass, ceramic, etc.). In the case of wiring formation by plating, the wiring pattern 101 constituting the wiring electrode is plated with Ni and Au on the surface of rolled or electrolytic Cu foil (electrolytic or electroless), and the wiring height is 20 to 20 80 μm. The semiconductor mounting substrate 100 is provided with an opening 102 for hollow mounting. Needless to say, the present invention can be applied to a flat semiconductor mounting substrate without forming the opening 102.

ここで、半導体チップ１０４の非電極配置辺に設けたダミー配線パターン１０３は、その形成仕様は、配線電極を構成する配線パターン１０１と同一の仕様（配線材構成、配線厚み、配線幅、表面めっき方法など）であることを特徴としている。   Here, the dummy wiring pattern 103 provided on the non-electrode placement side of the semiconductor chip 104 has the same specifications as the wiring pattern 101 constituting the wiring electrode (wiring material configuration, wiring thickness, wiring width, surface plating). Method).

一方、従来の方法では、図５に示すように基板３００には、電極配線を構成する配線パターン３０１のみ存在しており、ダミー配線パターン（１０３）に相当する配線そのものが存在しないか、図７に示すように、基板４００には、配線電極を構成する配線パターン４０１以外に半導体チップの端面に平行になるようにダミー配線パターン４０３を設ける手法が取られているという違いがある。   On the other hand, in the conventional method, as shown in FIG. 5, only the wiring pattern 301 constituting the electrode wiring exists on the substrate 300, and there is no wiring itself corresponding to the dummy wiring pattern (103). As shown in FIG. 5, the substrate 400 is different from the wiring pattern 401 constituting the wiring electrode in that a dummy wiring pattern 403 is provided so as to be parallel to the end face of the semiconductor chip.

次に、半導体チップ１０４は、Ｓｉ、ＳｉＣ、ＧａＡｓなどからなり、厚みは、０.１〜０.７ｍｍである。半導体チップ１０４の電極パッド１０６は、Ａｕ、Ｃｕ、Ｎｉなどからなり、電極形成方法は、めっき法（電解または無電解）を用い、高さは、５〜２０μｍである。   Next, the semiconductor chip 104 is made of Si, SiC, GaAs or the like and has a thickness of 0.1 to 0.7 mm. The electrode pad 106 of the semiconductor chip 104 is made of Au, Cu, Ni, or the like. The electrode forming method uses a plating method (electrolysis or electroless), and the height is 5 to 20 μm.

そして、半導体チップ１０４は、半導体実装基板１００への実装時、封止樹脂１０５を用いて封止される。この封止樹脂１０５は、エポキシ、イミド、シリコーン、アクリルなどをベースとしており、樹脂を供給する形態は、粘度２０〜１５０Ｐａ・ｓのペースト状もしくは、Ｂステージ化されたフイルム状である。半導体チップ１０４を熱圧着する条件は、１００〜２５０℃を樹脂温度のピークとして、２〜２０秒間圧着する。   The semiconductor chip 104 is sealed with a sealing resin 105 when mounted on the semiconductor mounting substrate 100. This sealing resin 105 is based on epoxy, imide, silicone, acrylic, etc., and the form of supplying the resin is a paste form having a viscosity of 20 to 150 Pa · s or a B-stage film form. The conditions for thermocompression bonding of the semiconductor chip 104 are pressure bonding for 2 to 20 seconds with a resin temperature peak at 100 to 250 ° C.

この電極配置での半導体チップ実装工程のフロー図を図２に示す。
接続用の電極パッド１０６を形成した半導体チップ１０４を、配線パターン１０１に加えて、電極パッドの存在しない辺にダミー配線パターン１０３を設けた、半導体実装基板１００へ実装するフローを示している。 A flow chart of the semiconductor chip mounting process with this electrode arrangement is shown in FIG.
A flow is shown in which a semiconductor chip 104 on which connection electrode pads 106 are formed is mounted on a semiconductor mounting substrate 100 in which a dummy wiring pattern 103 is provided on a side where no electrode pad exists in addition to the wiring pattern 101.

ここで、半導体実装基板１００には、あらかじめ、封止樹脂１０５が供給されており、配線パターン１０１およびダミー配線パターン１０３の有無に応じて、封止樹脂１０５は、高さに凹凸ができる。高さの凹凸は配線パターン１０１およびダミー配線パターン１０３に従ったものであり、電極高さ２０〜８０μｍに相当する。封止樹脂１０５は、樹脂厚みが、３０〜１００μｍで、電極高さの和相当となるように供給している。   Here, the sealing resin 105 is supplied to the semiconductor mounting substrate 100 in advance, and the sealing resin 105 can be uneven in height depending on the presence or absence of the wiring pattern 101 and the dummy wiring pattern 103. The height unevenness is in accordance with the wiring pattern 101 and the dummy wiring pattern 103 and corresponds to an electrode height of 20 to 80 μm. The sealing resin 105 is supplied such that the resin thickness is 30 to 100 μm and corresponds to the sum of the electrode heights.

次に、半導体チップ１０４を半導体実装基板１００に載置し（図２（ａ））、熱圧着方式で実装する（図２（ｂ））。この時、封止樹脂１０５の凹凸が電極パッド１０６の高さよりも小さい場合、封止樹脂１０５は、凹部で半導体チップ１０４に濡れあがらないが、配線パターン１０１の間にダミー配線パターン１０３を設けたため、その部分は、樹脂が凸になっており、半導体チップ１０４に濡れあがり、その後は、濡れ広がり、半導体チップ１０４の端面全面を覆う状態となる。   Next, the semiconductor chip 104 is mounted on the semiconductor mounting substrate 100 (FIG. 2A) and mounted by a thermocompression bonding method (FIG. 2B). At this time, when the unevenness of the sealing resin 105 is smaller than the height of the electrode pad 106, the sealing resin 105 does not wet the semiconductor chip 104 by the recess, but the dummy wiring pattern 103 is provided between the wiring patterns 101. The resin is convex in the portion, wets the semiconductor chip 104, and then wets and spreads to cover the entire end face of the semiconductor chip 104.

（実施の形態２）
次に本発明の実施の形態２について説明する。
本実施の形態２の半導体装置の要部説明図を図３に示す。
本実施の形態では、前記半導体チップ２０２が、二の字形状に電極配置されており、非電極配置辺に対向する前記半導体実装基板２００に配線パターン２０１と同一工程で形成されたダミー配線パターン２０３が、各非電極配置辺に３本設けられている。 (Embodiment 2)
Next, a second embodiment of the present invention will be described.
FIG. 3 is an explanatory diagram of a main part of the semiconductor device according to the second embodiment.
In the present embodiment, the semiconductor chip 202 has electrodes arranged in a two-letter shape, and the dummy wiring pattern 203 formed in the same process as the wiring pattern 201 on the semiconductor mounting substrate 200 facing the non-electrode arrangement side. Are provided at each non-electrode arrangement side.

ここで、Ａ−Ａ´ラインにおいて配線パターン２０１の上下間距離Ｄを複数のダミー配線パターン２０３で均等に割って配置している。
また、配置するダミー配線パターン２０３の本数は、封止樹脂のチップへの濡れ上がりを均一にするために必要な最小限の数としている Here, the vertical distance D of the wiring pattern 201 is equally divided by the plurality of dummy wiring patterns 203 in the AA ′ line.
Further, the number of dummy wiring patterns 203 to be arranged is set to the minimum number necessary for making the wetting of the sealing resin to the chip uniform.

この電極配置での半導体チップ実装工程フロー図を図４に示す。
電極パッド２０６を形成した半導体チップ２０４を、電極パッド２０６の存在しない部分に複数のダミー配線パターン２０３を設けた配線パターン２０１を有する半導体実装基板２００に実装するフローを示している。 FIG. 4 shows a flow chart of a semiconductor chip mounting process with this electrode arrangement.
A flow of mounting the semiconductor chip 204 on which the electrode pads 206 are formed on the semiconductor mounting substrate 200 having the wiring pattern 201 in which a plurality of dummy wiring patterns 203 are provided in a portion where the electrode pads 206 do not exist is shown.

ここで、基板２００には、あらかじめ、封止樹脂２０５が供給されており、配線パターン２０１の有無に応じて、封止樹脂２０５は、高さに凹凸ができる。高さの凹凸は配線パターン２０１、ダミー配線パターン２０３に従ったものであり、電極高さ２０〜８０μｍに相当する。封止樹脂２０５は、樹脂厚みが、３０〜１００μｍで、電極高さの和相当で供給している。   Here, the sealing resin 205 is supplied to the substrate 200 in advance, and the height of the sealing resin 205 can be uneven depending on the presence or absence of the wiring pattern 201. The height unevenness is in accordance with the wiring pattern 201 and the dummy wiring pattern 203 and corresponds to an electrode height of 20 to 80 μm. The sealing resin 205 has a resin thickness of 30 to 100 μm and is supplied corresponding to the sum of the electrode heights.

次に、半導体チップ２０４を半導体実装基板２００に熱圧着方式で実装する。この時、封止樹脂２０５の凹凸が電極パッド２０６の高さよりも小さい場合、封止２０５は、凹部で半導体チップ２０４に濡れあがらないが、配線パターン２０１の間に複数のダミー配線パターン２０３を設けたため、その部分は、樹脂が凸になっており、半導体チップ２０４に濡れあがり、その後は、濡れ広がり、半導体チップ２０４の端面全面を覆う状態となる。   Next, the semiconductor chip 204 is mounted on the semiconductor mounting substrate 200 by a thermocompression bonding method. At this time, when the unevenness of the sealing resin 205 is smaller than the height of the electrode pad 206, the sealing 205 does not wet the semiconductor chip 204 by the recess, but a plurality of dummy wiring patterns 203 are provided between the wiring patterns 201. For this reason, the resin is convex in that portion, wets the semiconductor chip 204, and then wets and spreads to cover the entire end face of the semiconductor chip 204.

なおダミー配線パターンと配線パターンは対称となるように形成されるのが望ましいが方向のみ対称となるようにしてもよい。すなわち、ダミー配線パターンの形成された辺と配線パターンの形成された辺とは対称となるようにするのが望ましい。   The dummy wiring pattern and the wiring pattern are preferably formed so as to be symmetric, but may be symmetric only in the direction. That is, it is desirable that the side on which the dummy wiring pattern is formed and the side on which the wiring pattern is formed be symmetrical.

本発明を詳細にまた特定の実施態様を参照して説明したが、本発明の精神と範囲を逸脱することなく様々な変更や修正を加えることができることは当業者にとって明らかである。
本出願は、2004年12月9日出願の日本特許出願、出願番号2004-356689に基づくものであり、その内容はここに参照として取り込まれる。 Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.
This application is based on Japanese Patent Application No. 2004-356689 filed on Dec. 9, 2004, the contents of which are incorporated herein by reference.

本発明の半導体実装基板は、半導体電極配置が均等でないあらゆる半導体チップの実装・封止品質の向上を実現しており、特に２辺にしか電極を配置していない場合の多い、固体撮像素子やＲＡＭ・ＲＯＭなどメモリーチップへの利用が有効である。また、確実に安定して実装可能であるため、積層化が求められるＳＩＰ（System in Package）などの半導体パッケージに利用可能である。さらに、高周波モジュール部品や、光モジュール部品など、電極数の少ない半導体チップに対しても、均等に樹脂封止を行なう目的において有効である。   The semiconductor mounting substrate of the present invention realizes improvement in mounting and sealing quality of any semiconductor chip in which the semiconductor electrode arrangement is not uniform, in particular, a solid-state imaging device or the like that often has electrodes arranged only on two sides. Use in memory chips such as RAM and ROM is effective. In addition, since it can be mounted stably and reliably, it can be used for a semiconductor package such as SIP (System in Package) which requires stacking. Furthermore, it is effective for the purpose of evenly resin-sealing even a semiconductor chip having a small number of electrodes, such as a high-frequency module component or an optical module component.

本発明の第１の実施の形態を示した半導体実装上面図および断面図である。It is the semiconductor mounting top view and sectional drawing which showed the 1st Embodiment of this invention. 本発明の第１の実施の形態を示した実装工程断面図である。It is mounting process sectional drawing which showed the 1st Embodiment of this invention. 本発明の第２の実施の形態を示した基板上面図である。It is the board | substrate top view which showed the 2nd Embodiment of this invention. 本発明の第２の実施の形態を示した実装工程断面図である。It is mounting process sectional drawing which showed the 2nd Embodiment of this invention. 従来技術における基板上面図である。It is a board | substrate top view in a prior art. 従来技術における実装工程断面図である。It is mounting process sectional drawing in a prior art. 従来技術における特許文献１の場合を示した基板上面図である。It is the board | substrate top view which showed the case of the patent document 1 in a prior art. 従来技術における特許文献１の場合を示した実装工程断面図である。It is mounting process sectional drawing which showed the case of patent document 1 in a prior art.

符号の説明Explanation of symbols

１００、２００、３００、４００・・・半導体実装基板
１０１、２０１、３０１、４０１・・・配線パターン
１０２、２０２、３０２、４０２・・・半導体実装基板開口部
１０３、２０３、４０３・・・ダミー配線パターン
１０４、２０４、３０４、４０４・・・半導体チップ
１０５、２０５、３０５、４０５・・・封止樹脂
１０６、２０６、３０６、４０６・・・半導体チップの電極パッド
Ｖ・・・ボイド 100, 200, 300, 400 ... Semiconductor mounting substrate 101, 201, 301, 401 ... Wiring pattern 102, 202, 302, 402 ... Semiconductor mounting substrate opening 103, 203, 403 ... Dummy wiring Pattern 104, 204, 304, 404 ... Semiconductor chip 105, 205, 305, 405 ... Sealing resin 106, 206, 306, 406 ... Electrode pad of semiconductor chip V ... Void

Claims (7)

ベアの半導体チップをフェースダウンでフリップチップ実装する半導体実装基板であって、
前記半導体チップの電極配置部に対向するとともに外部接続のなされる配線パターンと、前記半導体チップの非電極配置部に、前記半導体チップの辺に対して所定の角度をなすように設けられたダミー配線パターンとを具備した半導体実装基板。A semiconductor mounting substrate for flip-chip mounting a bare semiconductor chip face down,
A wiring pattern facing the electrode placement portion of the semiconductor chip and externally connected, and a dummy wiring provided at a non-electrode placement portion of the semiconductor chip so as to form a predetermined angle with respect to the side of the semiconductor chip A semiconductor mounting board having a pattern. 請求項１に記載の半導体実装基板であって、
前記ダミー配線パターンが、前記配線パターンと対称となる方向に設けられた半導体実装基板。The semiconductor mounting board according to claim 1,
A semiconductor mounting board in which the dummy wiring pattern is provided in a direction symmetrical to the wiring pattern. 請求項１に記載の半導体実装基板であって、
前記ダミー配線パターンが、前記配線パターンと同様に同一工程で形成された半導体実装基板。The semiconductor mounting board according to claim 1,
A semiconductor mounting substrate in which the dummy wiring pattern is formed in the same process as the wiring pattern. 請求項１乃至３のいずれかに記載の半導体実装基板であって、
前記半導体チップが、相対向する２辺に電極配置部を具備しており、
前記ダミー配線パターンが、前記２辺を除く２辺の中央部に設けられた半導体実装基板。A semiconductor mounting substrate according to any one of claims 1 to 3,
The semiconductor chip has electrode arrangement portions on two opposite sides,
A semiconductor mounting board in which the dummy wiring pattern is provided at the center of two sides excluding the two sides. 請求項１乃至４のいずれかに記載の半導体実装基板であって、
前記半導体チップが、コの字形状をなすように３辺に電極配置部を具備しており、
前記ダミー配線パターンは、残る１辺のほぼ中央部に設けられた半導体実装基板。A semiconductor mounting substrate according to any one of claims 1 to 4,
The semiconductor chip has electrode placement portions on three sides so as to form a U shape,
The dummy wiring pattern is a semiconductor mounting board provided at substantially the center of the remaining one side. 請求項１乃至５のいずれかに記載の半導体実装基板であって、
前記ダミー配線パターンは、各辺に複数本設けられる半導体実装基板。A semiconductor mounting substrate according to any one of claims 1 to 5,
A plurality of the dummy wiring patterns are provided on a semiconductor mounting substrate on each side. 請求項１乃至５のいずれかに記載の半導体実装基板であって、
前記ダミー配線パターンは、各辺の中央部に１本のみ設けられる半導体実装基板。A semiconductor mounting substrate according to any one of claims 1 to 5,
Only one dummy wiring pattern is provided in the central portion of each side.
JP2006546774A 2004-12-09 2005-12-09 Semiconductor mounting board Pending JPWO2006062195A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004356689 2004-12-09
JP2004356689 2004-12-09
PCT/JP2005/022678 WO2006062195A1 (en) 2004-12-09 2005-12-09 Semiconductor package substrate

Publications (1)

Publication Number Publication Date
JPWO2006062195A1 true JPWO2006062195A1 (en) 2008-06-12

Family

ID=36578015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006546774A Pending JPWO2006062195A1 (en) 2004-12-09 2005-12-09 Semiconductor mounting board

Country Status (2)

Country Link
JP (1) JPWO2006062195A1 (en)
WO (1) WO2006062195A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180006070A1 (en) 2015-02-13 2018-01-04 Sony Corporation Image sensor, method of manufacturing the same, and electronic apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799214A (en) * 1993-05-28 1995-04-11 Toshiba Corp Mounting device for photoelectric transducer and its production
JPH08335593A (en) * 1995-06-08 1996-12-17 Matsushita Electron Corp Semiconductor device and its manufacture
JP2001250889A (en) * 2000-03-06 2001-09-14 Matsushita Electric Ind Co Ltd Mounting structure of optical element and its manufacturing method
JP2003092382A (en) * 2001-09-18 2003-03-28 Sony Corp Semiconductor device and method for manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3779789B2 (en) * 1997-01-31 2006-05-31 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
JP3442989B2 (en) * 1998-02-23 2003-09-02 松下電器産業株式会社 Semiconductor device, method of manufacturing the same, and semiconductor carrier
JP3613098B2 (en) * 1998-12-21 2005-01-26 セイコーエプソン株式会社 Circuit board and display device and electronic device using the same
JP4287987B2 (en) * 2000-06-16 2009-07-01 パナソニック株式会社 Electronic component mounting method and electronic component mounting body

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799214A (en) * 1993-05-28 1995-04-11 Toshiba Corp Mounting device for photoelectric transducer and its production
JPH08335593A (en) * 1995-06-08 1996-12-17 Matsushita Electron Corp Semiconductor device and its manufacture
JP2001250889A (en) * 2000-03-06 2001-09-14 Matsushita Electric Ind Co Ltd Mounting structure of optical element and its manufacturing method
JP2003092382A (en) * 2001-09-18 2003-03-28 Sony Corp Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
WO2006062195A1 (en) 2006-06-15

Similar Documents

Publication Publication Date Title
JP5259560B2 (en) Semiconductor device
US9520374B2 (en) Semiconductor device, substrate and semiconductor device manufacturing method
JP2002368188A (en) Semiconductor device and method for manufacturing the same
US8592968B2 (en) Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method
JP2003338518A (en) Bump of semiconductor chip and method of manufacturing the same
TWI509756B (en) Chip-on-film package structure
US11094561B2 (en) Semiconductor package structure
JP5381175B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP3695458B2 (en) Semiconductor device, circuit board and electronic equipment
JP4417974B2 (en) Manufacturing method of stacked semiconductor device
WO2015103968A1 (en) Electronic device interconnector
JPWO2006062195A1 (en) Semiconductor mounting board
JP3997903B2 (en) Circuit board and semiconductor device
US8050049B2 (en) Semiconductor device
WO2017043480A1 (en) Semiconductor package
JP5078631B2 (en) Semiconductor device
JP3879319B2 (en) Semiconductor device and manufacturing method thereof
JP2020136624A (en) Semiconductor device
TWI290759B (en) Semiconductor package and its fabricating process
JP4995764B2 (en) Lead supported semiconductor package
TW201019426A (en) Leadless semiconductor package and its assembly for improving heat dissipation
JP2003068922A (en) Semiconductor chip mounting substrate and semiconductor device using the same
JP2001015557A (en) Semiconductor device and manufacture thereof
JPH11251473A (en) Insulating substrate, semiconductor device and semiconductor mounting device
JP2000299399A (en) Semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100420

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100817