JP2001250889A - Mounting structure of optical element and its manufacturing method - Google Patents
Mounting structure of optical element and its manufacturing methodInfo
- Publication number
- JP2001250889A JP2001250889A JP2000059921A JP2000059921A JP2001250889A JP 2001250889 A JP2001250889 A JP 2001250889A JP 2000059921 A JP2000059921 A JP 2000059921A JP 2000059921 A JP2000059921 A JP 2000059921A JP 2001250889 A JP2001250889 A JP 2001250889A
- Authority
- JP
- Japan
- Prior art keywords
- optical element
- semiconductor chip
- circuit board
- light receiving
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 189
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000011347 resin Substances 0.000 claims abstract description 141
- 229920005989 resin Polymers 0.000 claims abstract description 141
- 239000004065 semiconductor Substances 0.000 claims abstract description 134
- 238000007789 sealing Methods 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000009736 wetting Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 239000011889 copper foil Substances 0.000 claims description 9
- 238000013016 damping Methods 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 238000003892 spreading Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000866 electrolytic etching Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 101100219325 Phaseolus vulgaris BA13 gene Proteins 0.000 description 1
- 239000004927 clay Substances 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば、ＣＣＤ
（Charge Coupled Device）のような光素子をフリップ
チップ実装した光素子の実装構造体およびその製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a mounting structure of an optical element in which an optical element such as a (Charge Coupled Device) is flip-chip mounted and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、回路基板の入出力端子電極に半導
体装置を実装する際には、半田付けを用いたワイヤボン
ディング方法がよく利用されてきた。しかし、近年、半
導体装置のパッケージの小型化と接続端子数の増加によ
り接続端子の間隔が狭くなり、従来の半田付け技術で対
処することが次第に困難になってきたそこで、最近で
は、集積回路チップ等の半導体装置を回路基板の入出力
端子電極上に直接実装することにより実装面積を小型化
して効率的使用を図ろうとする方法が提案されてきた。2. Description of the Related Art Conventionally, when a semiconductor device is mounted on input / output terminal electrodes of a circuit board, a wire bonding method using soldering has been often used. However, in recent years, the space between the connection terminals has become narrower due to the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals, and it has become increasingly difficult to deal with the conventional soldering technology. A method has been proposed in which a semiconductor device such as the above is directly mounted on input / output terminal electrodes of a circuit board to reduce the mounting area for efficient use.
【０００３】なかでも、半導体装置を回路基板にフェイ
スダウン状態でフリップチップ実装する方法は、半導体
装置と回路基板との電気的接続が一括してできること、
および接続後の機械的強度が強いことから有用な方法で
あるとされている。In particular, a method of flip-chip mounting a semiconductor device on a circuit board in a face-down state is that electrical connection between the semiconductor device and the circuit board can be made collectively.
It is considered to be a useful method because of its high mechanical strength after connection.
【０００４】[0004]
【発明が解決しようとする課題】ここで、端子電極のあ
る側に受光領域を有する光素子半導体チップを、回路基
板にフリップチップ実装する場合には、回路基板には、
前記受光領域に対応する開口部を形成して実装すること
になるが、光素子半導体チップと回路基板との接続を補
強するための封止樹脂を注入する際に、その封止樹脂が
前記開口部から流れ出たり、あるいは、前記封止樹脂
が、光素子半導体チップの受光領域にまで広がって受光
領域を汚してしまって所望の特性が得られないといった
難点がある。Here, when an optical element semiconductor chip having a light receiving region on a side having a terminal electrode is flip-chip mounted on a circuit board, the circuit board has:
An opening corresponding to the light receiving region is formed and mounted. When a sealing resin for reinforcing the connection between the optical element semiconductor chip and the circuit board is injected, the sealing resin is filled with the opening. There is a problem that the desired characteristics cannot be obtained because the sealing resin spreads out from the portion or spreads to the light receiving region of the optical element semiconductor chip and contaminates the light receiving region.
【０００５】本発明は、上述の点に鑑みてなされたもの
であって、光素子半導体チップをフリップチップ実装す
る光素子の実装構造体において、受光領域などへの封止
樹脂による影響を防止することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to prevent an influence of a sealing resin on a light receiving area and the like in a mounting structure of an optical element in which an optical element semiconductor chip is flip-chip mounted. The purpose is to:
【０００６】[0006]
【課題を解決するための手段】本発明では、上述の目的
を達成するために、次のように構成している。In order to achieve the above-mentioned object, the present invention is configured as follows.
【０００７】すなわち、本発明は、受光領域および接続
端子が同一面側に形成されている光素子半導体チップ
を、前記受光領域に相対する領域に開口部が形成された
回路基板にフリップチップ実装してなる光素子の実装構
造体であって、前記光素子半導体チップの前記受光領域
の周囲および前記回路基板の前記開口部の周囲の少なく
とも一方には、前記光素子半導体チップと前記回路基板
との間に注入される封止樹脂を堰き止めるダム部を設け
たものである。That is, according to the present invention, an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface is flip-chip mounted on a circuit board having an opening formed in a region facing the light receiving region. Wherein the optical element semiconductor chip and the circuit board have at least one of a periphery of the light receiving region of the optical element semiconductor chip and a periphery of the opening of the circuit board. A dam portion is provided for blocking the sealing resin injected therebetween.
【０００８】本発明によれば、光素子半導体チップの受
光領域の周囲および回路基板の開口部の周囲の少なくと
も一方には、封止樹脂を堰き止めるダム部を設けている
ので、封止樹脂が、光素子半導体チップの受光領域へ流
れ込んだり、回路基板の開口部から流れ出すのを防止す
ることができ、良好な光素子の実装構造体を得ることが
できる。According to the present invention, at least one of the periphery of the light receiving region of the optical element semiconductor chip and the periphery of the opening of the circuit board is provided with a dam portion for blocking the sealing resin. Also, it is possible to prevent the optical element from flowing into the light receiving region of the semiconductor chip and from flowing out of the opening of the circuit board, and to obtain a good optical element mounting structure.
【０００９】[0009]
【発明の実施形態】本発明の請求項１に記載の発明は、
受光領域および接続端子が同一面側に形成されている光
素子半導体チップを、前記受光領域に相対する領域に開
口部が形成された回路基板にフリップチップ実装してな
る光素子の実装構造体であって、前記光素子半導体チッ
プの前記受光領域の周囲および前記回路基板の前記開口
部の周囲の少なくとも一方には、前記光素子半導体チッ
プと前記回路基板との間に注入される封止樹脂を堰き止
めるダム部を設けたものであり、このダム部によって、
封止樹脂が、光素子半導体チップの受光領域へ流れ込ん
だり、回路基板の開口部から流れ出すのを防止すること
ができ、良好な光素子の実装構造体を得ることができ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention described in claim 1 of the present invention is as follows.
An optical element mounting structure in which an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface side is flip-chip mounted on a circuit board having an opening formed in a region corresponding to the light receiving region. A sealing resin injected between the optical element semiconductor chip and the circuit board is provided on at least one of the periphery of the light receiving region of the optical element semiconductor chip and the periphery of the opening of the circuit board. A dam section for damming is provided. By this dam section,
It is possible to prevent the sealing resin from flowing into the light receiving region of the optical element semiconductor chip and from flowing out of the opening of the circuit board, and to obtain a good optical element mounting structure.
【００１０】請求項２に記載の発明は、請求項１記載の
発明において、前記ダム部は、前記封止樹脂の注入時に
流動特性を有さない材料からなり、所望の形状のダム部
を形成できる。According to a second aspect of the present invention, in the first aspect of the present invention, the dam portion is made of a material having no flow characteristics when the sealing resin is injected to form a dam portion having a desired shape. it can.
【００１１】請求項３に記載の発明は、請求項２記載の
発明において、前記材料が、レジストであり、光素子半
導体チップあるいは回路基板の製造工程において、容易
にダム部を形成できる。According to a third aspect of the present invention, in the second aspect, the material is a resist, and a dam portion can be easily formed in a process of manufacturing an optical element semiconductor chip or a circuit board.
【００１２】請求項４に記載の発明は、請求項２記載の
発明において、前記材料として、回路基板の配線形成用
の銅箔を用いて電気回路構成を担うことなく前記ダム部
とするものであり、配線形成と同時にダム部を形成でき
る。According to a fourth aspect of the present invention, in the second aspect of the present invention, the dam portion is formed by using a copper foil for forming wiring of a circuit board as the material without taking an electric circuit configuration. Yes, a dam portion can be formed at the same time as wiring formation.
【００１３】請求項５に記載の発明は、請求項４記載の
発明において、前記銅箔からなるダム部の表面にメッキ
を施さずに酸化層が形成されているものであり、この酸
化層によって封止樹脂のぬれ性が阻害され、封止樹脂を
一層効果的に堰き止めることができる。According to a fifth aspect of the present invention, in the fourth aspect, an oxide layer is formed on the surface of the dam portion made of the copper foil without plating. The wettability of the sealing resin is hindered, and the sealing resin can be more effectively blocked.
【００１４】請求項６に記載の発明は、受光領域および
接続端子が同一面側に形成されている光素子半導体チッ
プを、前記受光領域に相対する領域に開口部が形成され
た回路基板にフリップチップ実装してなる光素子の実装
構造体であって、前記光素子半導体チップの前記受光領
域の周囲および前記回路基板の前記開口部の周囲の少な
くとも一方には、前記光素子半導体チップと前記回路基
板との間に注入される封止樹脂のぬれ性を阻害するぬれ
不良領域を設けたものであり、このぬれ不良領域によっ
て封止樹脂が、光素子半導体チップの受光領域あるいは
回路基板の開口部へぬれ広がるのを防ぐことができ、良
好な光素子の実装構造体を得ることができる。According to a sixth aspect of the present invention, an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface is flipped to a circuit board having an opening formed in a region facing the light receiving region. A mounting structure of an optical element mounted on a chip, wherein at least one of a periphery of the light receiving region of the optical element semiconductor chip and a periphery of the opening of the circuit board includes the optical element semiconductor chip and the circuit. A wetting failure region that inhibits the wettability of the sealing resin injected between the substrate and the substrate is provided. The wetting failure region allows the sealing resin to be used as a light receiving region of the optical element semiconductor chip or an opening of the circuit board. It is possible to prevent the wet-spreading from spreading, and it is possible to obtain a good optical element mounting structure.
【００１５】請求項７に記載の発明は、請求項６記載の
発明において、前記光素子半導体チップの前記受光領域
の周囲または前記回路基板の前記開口部の周囲の一方に
は、前記ぬれ不良領域を設け、他方には、前記封止樹脂
をせき止めるダム部を設けたものであり、ぬれ不良領域
およびダム部によって、封止樹脂が、光素子半導体チッ
プの受光領域へ流れ込んだり、回路基板の開口部から流
れ出すのを一層効果的に防止することができる。According to a seventh aspect of the present invention, in the invention according to the sixth aspect, one of the periphery of the light receiving area of the optical element semiconductor chip and the periphery of the opening of the circuit board has the wetting failure area. And a dam portion for damping the sealing resin is provided on the other side, and the sealing resin flows into the light receiving region of the optical element semiconductor chip due to the wetting failure region and the dam portion, or the opening of the circuit board is opened. It can be more effectively prevented from flowing out of the part.
【００１６】請求項８に記載の発明は、受光領域および
接続端子が同一面側に形成されている光素子半導体チッ
プを、前記受光領域に相対する領域に開口部が形成され
た回路基板にフリップチップ実装してなる光素子の実装
構造体であって、前記光素子半導体チップの前記受光領
域の周囲には、該光素子半導体チップと前記回路基板と
を繋ぐ隔離壁が設けられるものであり、この隔離壁は、
光素子半導体チップと前記回路基板との間に亘って設け
られるので、封止樹脂が、光素子半導体チップの受光領
域へ流れ込んだり、回路基板の開口部から流れ出すのを
一層確実に防止することができる。According to an eighth aspect of the present invention, an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface is flipped to a circuit board having an opening formed in a region facing the light receiving region. A mounting structure of an optical element mounted on a chip, wherein an isolation wall connecting the optical element semiconductor chip and the circuit board is provided around the light receiving region of the optical element semiconductor chip, This isolation wall
Since the sealing resin is provided between the optical element semiconductor chip and the circuit board, it is possible to more reliably prevent the sealing resin from flowing into the light receiving region of the optical element semiconductor chip or flowing out from the opening of the circuit board. it can.
【００１７】請求項９に記載の発明は、請求項８記載の
発明において、前記隔離壁が、絶縁性樹脂からなり、光
素子半導体チップを回路基板に電気的に接続する際に、
前記絶縁性樹脂を硬化させて隔離壁を形成できる。According to a ninth aspect of the present invention, in the invention of the eighth aspect, when the isolation wall is made of an insulating resin and the optical element semiconductor chip is electrically connected to the circuit board,
The isolation wall can be formed by curing the insulating resin.
【００１８】請求項１０に記載の発明は、請求項９記載
の発明において、前記絶縁性樹脂が、前記光素子半導体
チップと前記回路基板との間に注入される封止樹脂の硬
化前に、該封止樹脂よりも粘度の高い樹脂またはフィル
ム状に形成された樹脂であり、隔離壁を容易に形成でき
る。According to a tenth aspect of the present invention, in the ninth aspect of the present invention, the insulating resin is cured before a sealing resin injected between the optical element semiconductor chip and the circuit board is cured. It is a resin having a higher viscosity than the sealing resin or a resin formed in a film shape, and can easily form the isolation wall.
【００１９】請求項１１に記載の発明は、受光領域およ
び接続端子が同一面側に形成されている光素子半導体チ
ップを、前記受光領域に相対する領域に開口部が形成さ
れた回路基板にフリップチップ実装してなる光素子の実
装構造体であって、前記受光領域に対応する領域が開口
されたフィルム状の封止樹脂を硬化させて前記光素子半
導体チップと前記回路基板との間の封止を行うものであ
り、フィルム状に加工した封止樹脂を用いることによ
り、封止樹脂の硬化時の広がりを抑制することが可能と
なり、光素子半導体チップの受光領域へ流れ込んだり、
回路基板の開口部から流れ出すのを防止することができ
る。According to an eleventh aspect of the present invention, an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface is flipped to a circuit board having an opening formed in a region facing the light receiving region. A mounting structure of an optical element mounted on a chip, wherein a film-shaped sealing resin having an area corresponding to the light receiving area is cured to seal the optical element semiconductor chip and the circuit board. By using the sealing resin processed into a film shape, it is possible to suppress the spread of the sealing resin during curing, it flows into the light receiving area of the optical element semiconductor chip,
It can be prevented from flowing out of the opening of the circuit board.
【００２０】請求項１２に記載の発明は、請求項１１記
載の発明において、前記封止樹脂が異方性導電膜であ
り、封止とともに、光素子半導体チップと回路基板との
電気的接続を行える。According to a twelfth aspect of the present invention, in the eleventh aspect of the present invention, the sealing resin is an anisotropic conductive film, and the sealing and the electrical connection between the optical element semiconductor chip and the circuit board are performed. I can do it.
【００２１】請求項１３に記載の発明は、前記受光領域
の周囲に、封止樹脂を堰き止めるダム部が形成された光
素子半導体チップを、前記受光領域と相対する領域に開
口部が形成されている回路基板にフリップチップ実装
し、フリップチップ実装後に前記封止樹脂を注入して硬
化させるものであり、ダム部によって封止樹脂が、光素
子半導体チップの受光領域へ流れ込むのを防止すること
ができる。According to a thirteenth aspect of the present invention, an optical element semiconductor chip having a dam portion for damping a sealing resin is formed around the light receiving region, and an opening is formed in a region opposed to the light receiving region. Flip-chip mounting on a circuit board that has been performed, and after the flip-chip mounting, the sealing resin is injected and cured, and the damping portion prevents the sealing resin from flowing into the light receiving region of the optical element semiconductor chip. Can be.
【００２２】請求項１４に記載の発明は、光素子半導体
チップの受光領域と相対する領域に開口部が形成される
とともに、前記開口部の周囲に、封止樹脂を堰き止める
ダム部が形成されている回路基板に、前記光素子半導体
チップをフリップチップ実装し、フリップチップ実装後
に封止樹脂を注入して硬化させるものであり、ダム部に
よって、封止樹脂が、回路基板の開口部から流れ出すの
を防止することができる。According to a fourteenth aspect of the present invention, an opening is formed in a region facing the light receiving region of the optical element semiconductor chip, and a dam portion for damping a sealing resin is formed around the opening. The optical element semiconductor chip is flip-chip mounted on the circuit board, and the sealing resin is injected and cured after the flip-chip mounting. The sealing resin flows out of the opening of the circuit board by the dam portion. Can be prevented.
【００２３】請求項１５に記載の発明は、受光領域の周
囲に、封止樹脂とのぬれ性を阻害するぬれ不良領域が形
成された光素子半導体チップを、前記受光領域と相対す
る領域に開口部が形成されている回路基板に、フリップ
チップ実装し、フリップチップ実装後に前記封止樹脂を
注入して硬化させるものであり、ぬれ不良領域によって
封止樹脂が、光素子半導体チップの受光領域へ濡れ広が
るのを防ぐことができる。According to a fifteenth aspect of the present invention, an optical element semiconductor chip having a non-wetting area formed around a light-receiving area, which impairs wettability with a sealing resin, is formed in an area facing the light-receiving area. Flip chip mounting is performed on the circuit board on which the portion is formed, and after the flip chip mounting, the sealing resin is injected and cured, and the wetting failure area causes the sealing resin to reach the light receiving area of the optical element semiconductor chip. It can be prevented from spreading.
【００２４】請求項１６に記載の発明は、光素子半導体
チップの受光領域と相対する領域に開口部が形成される
とともに、前記開口部の周囲に、封止樹脂のぬれ性を阻
害するぬれ不良領域が形成された回路基板に、前記光素
子半導体チップをフリップチップ実装し、フリップチッ
プ実装後に前記封止樹脂を注入して硬化させるものであ
り、ぬれ不良領域によって封止樹脂が、回路基板の開口
部へ濡れ広がるのを防ぐことができる。According to the present invention, an opening is formed in a region opposite to a light receiving region of the optical element semiconductor chip, and a wetting defect that hinders the wettability of a sealing resin is formed around the opening. The optical element semiconductor chip is flip-chip mounted on the circuit board on which the region is formed, and the sealing resin is injected and cured after the flip-chip mounting. Spreading to the opening can be prevented.
【００２５】請求項１７に記載の発明は、光素子半導体
チップの受光領域と相対する領域に開口部が形成されて
いる回路基板の前記開口部の周囲に絶縁性樹脂からなる
フィルムを配置し、前記回路基板に、前記光素子半導体
チップをフリップチップ実装するとともに、前記フィル
ムを硬化させ、封止樹脂を注入して硬化させるものであ
り、硬化したフィルムによって、封止樹脂が、光素子半
導体チップの受光領域へ流れ込んだり、回路基板の開口
部から流れ出すのを防止することができる。According to a seventeenth aspect of the present invention, a film made of an insulating resin is disposed around the opening of the circuit board having an opening formed in a region facing the light receiving region of the optical element semiconductor chip, The optical element semiconductor chip is flip-chip mounted on the circuit board, and the film is cured, and a sealing resin is injected and cured. To the light receiving area of the circuit board or out of the opening of the circuit board.
【００２６】請求項１８に記載の発明は、請求項１７記
載の発明において、前記封止樹脂を、前記回路基板の接
続端子の外方から内方へ注入するとともに、前記外方と
前記内方との圧力差を利用して供給するものであり、圧
力差を利用することによって内方の隅々まで封止樹脂を
充填できる。According to an eighteenth aspect of the present invention, in accordance with the seventeenth aspect of the present invention, the sealing resin is injected from the outside to the inside of the connection terminal of the circuit board, and the outside and the inside of the connection terminal are connected to each other. The sealing resin can be supplied to every inner corner by using the pressure difference.
【００２７】請求項１９に記載の発明は、光素子半導体
チップの受光領域と相対する領域に開口部が形成されて
いる回路基板に、前記開口部に対応して開口された樹脂
フィルムを配置し、前記光素子半導体チップを前記回路
基板に圧接させて前記樹脂フィルムを硬化させてフリッ
プチップ実装するものであり、樹脂フィルムで封止する
ので、封止時の樹脂の広がりを抑制することが可能とな
り、光素子半導体チップの受光領域へ流れ込んだり、回
路基板の開口部から流れ出すのを防止することができ
る。According to a nineteenth aspect of the present invention, a resin film having an opening corresponding to the opening is disposed on a circuit board having an opening formed in a region facing the light receiving region of the optical element semiconductor chip. The optical element semiconductor chip is pressed against the circuit board, the resin film is cured, and flip-chip mounting is performed. Since the resin film is sealed, the spread of the resin at the time of sealing can be suppressed. Thus, it is possible to prevent the light from flowing into the light receiving region of the optical element semiconductor chip or flowing out from the opening of the circuit board.
【００２８】請求項２０に記載の発明は、光素子半導体
チップの受光領域と相対する領域に開口部が形成されて
いる回路基板に、前記光素子半導体チップをフリップチ
ップ実装し、前記開口部から前記光素子半導体チップの
受光領域に至る空間を閉塞する閉塞体を挿入した状態
で、封止樹脂を注入して硬化させ、前記閉塞体を取り外
すものであり、回路基板の開口部から光素子半導体チッ
プの受光領域に至る空間が閉塞された状態で封止樹脂を
注入するので、封止樹脂が、光素子半導体チップの受光
領域へ流れ込んだり、回路基板の開口部から流れ出すと
いったことがない。According to a twentieth aspect of the present invention, the optical element semiconductor chip is flip-chip mounted on a circuit board having an opening in a region opposed to a light receiving region of the optical element semiconductor chip. A sealing resin is injected and cured in a state in which a closing member for closing a space reaching a light receiving region of the optical element semiconductor chip is inserted, and the closing member is removed, and the optical element semiconductor is removed from an opening of the circuit board. Since the sealing resin is injected while the space to the light receiving area of the chip is closed, the sealing resin does not flow into the light receiving area of the optical element semiconductor chip or flow out of the opening of the circuit board.
【００２９】以下、図面によって本発明の実施の形態に
ついて詳細に説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
【００３０】（実施形態１）図１は、本発明の一実施形
態である光素子の実装構造体１の概略断面図である。(Embodiment 1) FIG. 1 is a schematic sectional view of an optical element mounting structure 1 according to an embodiment of the present invention.
【００３１】この実施の形態の光素子の実装構造体１
は、受光素子部の領域である受光領域２および接続端子
としての二段の突起電極３が同一面側に形成されている
光素子半導体チップ４を、前記受光領域２に相対する領
域に開口部５が形成された回路基板６にフリップチップ
実装してなるものである。An optical element mounting structure 1 according to this embodiment
The optical element semiconductor chip 4 in which the light receiving region 2 which is the region of the light receiving element portion and the two-stage projecting electrode 3 as the connection terminal are formed on the same surface side is provided with an opening in the region opposed to the light receiving region 2. The circuit board 6 is formed by flip-chip mounting on a circuit board 6 on which the circuit board 5 is formed.
【００３２】この光素子半導体チップ４の突起電極３
は、公知の方法で形成され、例えば、ワイヤーボンディ
ング装置を改良したバンプボンダー装置を用いてＡｕの
ワイヤーを溶かして球状にした後に電極パッド７へ超音
波、熱と圧力とを用いて接合して形成する。なお、Ａｕ
の突起電極３に限らず、はんだ等でもよいし、形成方法
もワイヤボンティング法に限らず、メッキ法でもよい。The protruding electrode 3 of this optical element semiconductor chip 4
Is formed by a known method, for example, by melting a Au wire into a spherical shape using a bump bonder device which is an improved wire bonding device, and bonding the wire to the electrode pad 7 using ultrasonic waves, heat and pressure. Form. In addition, Au
Not only the bump electrode 3 but also solder or the like, and the forming method is not limited to the wire bonding method but may be a plating method.
【００３３】この光素子の実装構造体１では、光素子半
導体チップ４の突起電極３と回路基板６の電極端子８と
の電気的接続を導電性接着剤９を用いて行っており、こ
の導電性接着剤９の硬化を行った後に、半導体素子チッ
プ４と回路基板６との間に、封止樹脂１０を供給、硬化
して実装構造体とするものである。In the optical element mounting structure 1, electrical connection between the protruding electrodes 3 of the optical element semiconductor chip 4 and the electrode terminals 8 of the circuit board 6 is made by using a conductive adhesive 9. After the hardening of the adhesive 9, the sealing resin 10 is supplied between the semiconductor element chip 4 and the circuit board 6 and hardened to form a mounting structure.
【００３４】この実施の形態では、封止樹脂１０が、光
素子半導体チップ４の矩形の受光領域２に流れ込んだ
り、あるいは、前記受光領域２に光を導入するための回
路基板６の矩形の開口部５から流れ出るのを防止するた
めに、次のように構成している。In this embodiment, the sealing resin 10 flows into the rectangular light receiving region 2 of the optical element semiconductor chip 4 or a rectangular opening of the circuit board 6 for introducing light into the light receiving region 2. In order to prevent the liquid from flowing out of the section 5, the following configuration is provided.
【００３５】すなわち、この実施の形態では、光素子半
導体チップ４の受光領域２と相対する箇所に形成されて
いる回路基板６の開口部５の周囲には、供給される封止
樹脂１０を堰き止めるためのダム部１１が、前記開口部
５を囲むように矩形に連続して設けられている。That is, in this embodiment, the supplied sealing resin 10 is damped around the opening 5 of the circuit board 6 formed at a position facing the light receiving region 2 of the optical element semiconductor chip 4. A dam portion 11 for stopping is provided continuously in a rectangular shape so as to surround the opening 5.
【００３６】この実施の形態では、ダム部１１は、例え
ば、ソルダレジストなどを用いてスクリーン印刷や露
光、現像などの公知の方法によって形成される。In this embodiment, the dam portion 11 is formed by a known method such as screen printing, exposure, and development using, for example, a solder resist.
【００３７】このように、回路基板６の開口部５の周囲
に、ダム部を突設することにより、光素子半導体チップ
４と回路基板６との間に、封止樹脂１０を外方から注入
する際に、封止樹脂１０が、ダム部１１で堰き止められ
ることになり、回路基板６の開口部５から漏れ出した
り、光素子半導体チップ４の受光領域２に広がるのを抑
制できることになり、これによって、良好な特性の光素
子の実装構造体１を得ることができる。As described above, by projecting the dam portion around the opening 5 of the circuit board 6, the sealing resin 10 is injected from the outside between the optical element semiconductor chip 4 and the circuit board 6. In this case, the sealing resin 10 is blocked by the dam portion 11, so that it is possible to prevent the sealing resin 10 from leaking out from the opening 5 of the circuit board 6 and spreading to the light receiving region 2 of the optical element semiconductor chip 4. Thereby, the mounting structure 1 of the optical element having good characteristics can be obtained.
【００３８】図２は、この実施の形態の製造工程を示す
図であり、先ず、同図（ａ）に示されるように、光素子
半導体チップ４の電極パッド７上にワイヤボンディング
法などによって突起電極３を形成し、さらに導電性接着
剤９を該突起電極３上に形成する。FIG. 2 is a view showing a manufacturing process of this embodiment. First, as shown in FIG. 2A, a projection is formed on the electrode pad 7 of the optical element semiconductor chip 4 by a wire bonding method or the like. The electrode 3 is formed, and a conductive adhesive 9 is formed on the protruding electrode 3.
【００３９】一方、光素子半導体チップ４の受光領域９
に対応する開口部５を有する回路基板６には、電極端子
８を形成する一方、上述のようにスクリーン印刷などの
手法を用いて前記開口部５の周囲にダム部１１を形成す
る。On the other hand, the light receiving region 9 of the optical element semiconductor chip 4
The electrode terminals 8 are formed on the circuit board 6 having the openings 5 corresponding to the above, and the dam portions 11 are formed around the openings 5 by using a technique such as screen printing as described above.
【００４０】次に、同図（ｂ）に示されるように、光素
子半導体チップ４を、フェイスダウン状態で、突起電極
３が端子電極７上に対応するように位置合わせを行って
回路基板６上に載置し、高温に加熱することにより、導
電性接着剤９の硬化を行って電気的に接続し、さらに、
同図（ｃ）に示されるように、接続を補強するために封
止樹脂１０を、矢符Ａで示されるように外方から注入し
て封止硬化させて図１の光素子の実装構造体１を得るも
のである。Next, as shown in FIG. 2B, the optical element semiconductor chip 4 is positioned in a face-down state so that the protruding electrodes 3 correspond to the terminal electrodes 7, and the circuit board 6 is formed. Placed on top and heated to a high temperature, the conductive adhesive 9 is cured and electrically connected.
As shown in FIG. 1C, a sealing resin 10 is injected from the outside as shown by an arrow A in order to reinforce the connection, and the resin is cured by sealing. The body 1 is obtained.
【００４１】この封止樹脂１０の注入時に、ダム部１１
によって封止樹脂１０が、回路基板６の開口部５から漏
れ出したり、光素子半導体チップ４の受光領域９に広が
るのを抑制できることになる。When the sealing resin 10 is injected, the dam 11
Accordingly, it is possible to prevent the sealing resin 10 from leaking out of the opening 5 of the circuit board 6 and spreading to the light receiving region 9 of the optical element semiconductor chip 4.
【００４２】また、ダム部１１をレジストで形成してい
るので、回路基板の製造と同時にダム部を形成すること
ができ、安価に実現できる。Further, since the dam portion 11 is formed of a resist, the dam portion can be formed simultaneously with the manufacture of the circuit board, and can be realized at low cost.
【００４３】この実施の形態では、ダム部１１をソルダ
レジストで構成したけれども、本発明の他の実施の形態
として、回路基板６の配線形成に用いられる銅箔を用い
てもよい。すなわち、公知の回路基板製造方法で配線形
成と同時に銅箔のパターニングを行うことによって、回
路基板６の開口部５の周囲に、回路構成に関与しないダ
ム部１１を設けてもよい。このように配線形成と同時に
ダム部１１を形成することにより、安価に実現できる。
さらに、この銅箔を用いたダム部１１のみニッケルや金
などのメッキを施すことなく、酸化層を形成するように
してもよく、この酸化層の形成によって、封止樹脂１０
のぬれ性を阻害して封止樹脂１０がダム部１１を乗り越
えるのを防止するようにしてもよい。In this embodiment, the dam portion 11 is formed of a solder resist. However, as another embodiment of the present invention, a copper foil used for forming wiring of the circuit board 6 may be used. That is, the dam portion 11 not involved in the circuit configuration may be provided around the opening 5 of the circuit board 6 by patterning the copper foil at the same time as forming the wiring by a known circuit board manufacturing method. By forming the dam portion 11 at the same time as the formation of the wiring in this way, it can be realized at low cost.
Further, an oxide layer may be formed only on the dam portion 11 using the copper foil without plating with nickel, gold, or the like.
The sealing resin 10 may be prevented from climbing over the dam 11 by inhibiting the wettability of the sealing resin 10.
【００４４】また、ダム部１１は、レジストや銅箔に限
らず、封止樹脂１０の注入時に流動特性を有さない材料
からなるものであればよく、例えば、硬化済みの絶縁性
樹脂などであってもよい。The dam portion 11 is not limited to a resist or a copper foil, and may be made of a material having no flow characteristics when the sealing resin 10 is injected. For example, the dam portion 11 may be made of a cured insulating resin or the like. There may be.
【００４５】上述の実施の形態では、ダム部１１は、回
路基板６の開口部５の周囲に設けたけれども、本発明の
他の実施の形態として、光素子半導体チップ４の受光領
域２の周囲に設けてもよく、あるいは、回路基板６およ
び光素子半導体チップ４の両者に設けるようにしてもよ
い。In the above embodiment, the dam 11 is provided around the opening 5 of the circuit board 6. However, as another embodiment of the present invention, the dam 11 is provided around the light receiving region 2 of the optical element semiconductor chip 4. May be provided on both the circuit board 6 and the optical element semiconductor chip 4.
【００４６】（実施形態２）図３は、本発明の他の実施
の形態の光素子の実装構造体の概略断面図であり、上述
の実施の形態に対応する部分には、同一の参照符号を付
す。(Embodiment 2) FIG. 3 is a schematic sectional view of a mounting structure of an optical element according to another embodiment of the present invention, and portions corresponding to the above-described embodiment are denoted by the same reference numerals. Is attached.
【００４７】この実施の形態の光素子の実装構造体１１
も、光素子半導体チップ４を、開口部５が形成された回
路基板６に、導電性接着剤９を用いてフリップチップ実
装して封止樹脂１０で封止するものである。The optical element mounting structure 11 of this embodiment
Also, the optical element semiconductor chip 4 is flip-chip mounted on the circuit board 6 in which the opening 5 is formed by using a conductive adhesive 9 and sealed with a sealing resin 10.
【００４８】この実施の形態では、封止樹脂１０が、光
素子半導体チップ４の受光領域２に流れ込むのを防止す
るために、次のように構成している。In this embodiment, in order to prevent the sealing resin 10 from flowing into the light receiving region 2 of the optical element semiconductor chip 4, the following configuration is adopted.
【００４９】すなわち、この実施の形態では、光素子半
導体チップ４の受光領域２の周囲には、封止樹脂１０の
ぬれ性を阻害するぬれ不良領域１２を設けている。That is, in this embodiment, the wetting failure region 12 which hinders the wetting property of the sealing resin 10 is provided around the light receiving region 2 of the optical element semiconductor chip 4.
【００５０】このぬれ不良領域１２は、例えば、電解エ
ッチングによって凹凸を形成して構成され、この凹凸に
空気をかみ込んで封止樹脂のぬれ性を阻害するものであ
る。The poor wetting region 12 is formed by forming irregularities by, for example, electrolytic etching, and the air is trapped in the irregularities to impair the wettability of the sealing resin.
【００５１】このように、光素子半導体チップ４の受光
領域２の周囲に、封止樹脂１０のぬれ性を阻害するぬれ
不良領域１２を設けたので、封止樹脂１０の注入時に、
封止樹脂１０が、光素子半導体チップ４の受光領域２に
広がるのを防止できることになり、これによって、良好
な特性を有する光素子の実装構造体２１を得ることがで
きる。As described above, since the non-wetting region 12 that hinders the wettability of the sealing resin 10 is provided around the light receiving region 2 of the optical element semiconductor chip 4, when the sealing resin 10 is injected,
The sealing resin 10 can be prevented from spreading to the light receiving region 2 of the optical element semiconductor chip 4, whereby an optical element mounting structure 21 having good characteristics can be obtained.
【００５２】この実施の形態の光素子の実装構造体２１
は、上述の実施の形態と基本的に同様にして製造される
ものであり、ぬれ不良領域１２が形成された光素子半導
体チップ４を、フェイスダウン状態で、その突起電極３
が端子電極７上に対応するように位置合わせを行って回
路基板６上に載置し、高温に加熱することにより、導電
性接着剤９の硬化を行って電気的接続し、さらに、封止
樹脂１０を注入して封止硬化させるものである。The optical element mounting structure 21 of this embodiment
Is manufactured basically in the same manner as in the above-described embodiment. The optical element semiconductor chip 4 in which the wetting failure region 12 is formed is placed face-down in a state in which
Are positioned so as to correspond to the terminal electrodes 7, placed on the circuit board 6, and heated to a high temperature to cure the conductive adhesive 9 to make electrical connection, and further to seal. The resin 10 is injected to be sealed and cured.
【００５３】なお、ぬれ不良領域１２は、電解エッチン
グに限らず、例えば、フッ素処理やフッ素以外の親水基
を有してない有機物を、受光領域２の周囲に塗布して形
成し、処理された固体表面の表面張力の低下によって封
止樹脂１０のぬれ性を阻害してもよく、あるいは、この
処理と上述の電解エッチングなどによる凹凸の形成を組
み合わせてもよい。また、受光領域２の周囲に油を塗布
して封止樹脂１０のぬれ性を阻害してもよい。The poor wetting region 12 is not limited to the electrolytic etching, but is formed by applying an organic material having no hydrophilic group other than fluorine or the like around the light receiving region 2, for example. The wettability of the sealing resin 10 may be impaired by lowering the surface tension of the solid surface, or this treatment may be combined with the above-described formation of unevenness by electrolytic etching or the like. In addition, oil may be applied around the light receiving region 2 to inhibit the wettability of the sealing resin 10.
【００５４】上述の実施の形態では、光素子半導体チッ
プ４の受光領域２の周囲に、ぬれ不良領域１２を形成し
たけれども、本発明の他の実施の形態として、回路基板
６の開口部５の周囲に、封止樹脂１０のぬれ性を阻害す
るぬれ不良領域を設けてもよく、あるいは、光素子半導
体チップ４および回路基板６の両者に設けてもよい。In the above-described embodiment, the wetting failure region 12 is formed around the light receiving region 2 of the optical element semiconductor chip 4. However, as another embodiment of the present invention, the opening 5 of the circuit board 6 is formed. Around the periphery, a poor wetting region that inhibits the wettability of the sealing resin 10 may be provided, or may be provided on both the optical element semiconductor chip 4 and the circuit board 6.
【００５５】また、上述の実施の形態１と組み合わせて
もよい。すなわち、光素子半導体チップ４または回路基
板６の一方にぬれ不良領域を設け、他方にダム部を設け
てもよい。Further, it may be combined with the first embodiment. That is, a wetting failure region may be provided on one of the optical element semiconductor chip 4 and the circuit board 6, and a dam portion may be provided on the other.
【００５６】（実施形態３）図４は、本発明のさらに他
の実施の形態の光素子の実装構造体の概略断面図であ
り、上述の実施の形態に対応する部分には、同一の参照
符号を付す。(Embodiment 3) FIG. 4 is a schematic sectional view of a mounting structure for an optical element according to still another embodiment of the present invention. Assign a sign.
【００５７】この実施の形態の光素子の実装構造体３１
も、光素子半導体チップ４を、開口部５が形成された回
路基板６に、導電性接着剤９を用いてフリップチップ実
装して封止樹脂１０で封止するものである。The optical element mounting structure 31 of this embodiment
Also, the optical element semiconductor chip 4 is flip-chip mounted on the circuit board 6 in which the opening 5 is formed by using a conductive adhesive 9 and sealed with a sealing resin 10.
【００５８】この実施の形態では、封止樹脂１０が、光
素子半導体チップ４の矩形の受光領域２に流れ込んだ
り、あるいは、前記受光領域２に光を導入するための回
路基板６の矩形の開口部５から流れ出るのを防止するた
めに、次のように構成している。In this embodiment, the sealing resin 10 flows into the rectangular light receiving region 2 of the optical element semiconductor chip 4 or a rectangular opening of the circuit board 6 for introducing light into the light receiving region 2. In order to prevent the liquid from flowing out of the section 5, the following configuration is provided.
【００５９】すなわち、この実施の形態では、光素子半
導体チップ４の受光領域２の周囲には、光素子半導体チ
ップ４と前記回路基板６とを繋ぐ絶縁性樹脂からなる隔
離壁１３が設けられている。That is, in this embodiment, an isolation wall 13 made of insulating resin is provided around the light receiving region 2 of the optical element semiconductor chip 4 and connects the optical element semiconductor chip 4 and the circuit board 6. I have.
【００６０】この隔離壁１３は、回路基板６の開口部５
の周囲に、前記開口部５に対応する開口を有する矩形の
フィルム状に加工されたエポキシ系樹脂などの絶縁性樹
脂を配置し、上述の実施の形態と同様に、フリップチッ
プ実装を行って導電性接着剤９を硬化させると同時に前
記絶縁性樹脂の硬化を行うことによって形成している。The separating wall 13 is formed by the opening 5 of the circuit board 6.
Around the periphery of the substrate, an insulating resin such as an epoxy-based resin processed into a rectangular film having an opening corresponding to the opening 5 is disposed, and, similarly to the above-described embodiment, is mounted by flip-chip mounting. It is formed by curing the insulating resin at the same time as the adhesive 9 is cured.
【００６１】このように光素子半導体チップ４と回路基
板６との間に亘る隔離壁１３によって、封止樹脂１０
が、光素子半導体チップ４の矩形の受光領域２に流れ込
んだり、あるいは、前記受光領域２に光を導入するため
の回路基板６の矩形の開口部５から流れ出るのを確実に
防止できる。As described above, the separation wall 13 extending between the optical element semiconductor chip 4 and the circuit board 6 allows the sealing resin 10
Can be reliably prevented from flowing into the rectangular light receiving region 2 of the optical element semiconductor chip 4 or flowing out from the rectangular opening 5 of the circuit board 6 for introducing light into the light receiving region 2.
【００６２】また、隔離壁１３を構成する絶縁樹脂によ
って、光素子半導体チップ４と回路基板６との接着面積
が広くなって接着強度が向上する。Also, the insulating resin forming the isolation wall 13 increases the bonding area between the optical element semiconductor chip 4 and the circuit board 6 and improves the bonding strength.
【００６３】この実施の形態の光素子の実装構造体３１
は、回路基板６の開口部５の周囲に、絶縁性樹脂からな
る前記開口部５に対応した開口を有する矩形のフィルム
を配置し、この回路基板６に、光素子半導体チップ４
を、フェイスダウン状態で、その突起電極３が端子電極
７上に対応するように位置合わせを行って回路基板６上
に載置し、高温に加熱するとともに、加圧することによ
り、導電性接着剤９の硬化を行って電気的接続するとと
もに、前記フィルムを硬化させて隔離壁１３を形成し、
さらに、封止樹脂１０を注入して封止硬化させるもので
ある。The optical element mounting structure 31 of this embodiment
A rectangular film having an opening corresponding to the opening 5 made of an insulating resin is arranged around the opening 5 of the circuit board 6, and the optical element semiconductor chip 4
Is placed on the circuit board 6 in a face-down state so that the protruding electrodes 3 correspond to the terminal electrodes 7, and is heated to a high temperature and pressurized. 9 to make electrical connection and cure the film to form an isolation wall 13;
Furthermore, the sealing resin 10 is injected and the sealing is cured.
【００６４】この実施の形態では、隔離壁１３によっ
て、回路基板６の中央側と封止樹脂１０が注入される外
方側とが遮断されており、このため、封止樹脂１０を回
路基板６の内方へ円滑に供給できるように、圧力差を利
用している。In this embodiment, the central side of the circuit board 6 and the outer side into which the sealing resin 10 is injected are blocked by the separating wall 13, so that the sealing resin 10 is separated from the circuit board 6. The pressure difference is used so that it can be supplied smoothly to the inside.
【００６５】すなわち、例えば、真空チャンバ内の真空
雰囲気において、封止樹脂１０を回路基板６の外方から
供給し、その後、大気中に開放することにより、大気の
圧力によって封止樹脂を、低圧の回路基板６の内方へ供
給するものであり、これによって、隅づみまで封止樹脂
１０を充填することが可能である。That is, for example, in a vacuum atmosphere in a vacuum chamber, the sealing resin 10 is supplied from the outside of the circuit board 6 and then opened to the atmosphere, whereby the sealing resin is reduced to a low pressure by the pressure of the atmosphere. Is supplied to the inside of the circuit board 6, whereby the sealing resin 10 can be filled up to the corners.
【００６６】この実施の形態では、隔離壁１３を、フィ
ルム状に加工した絶縁性樹脂を用いて構成したけれど
も、本発明の他の実施の形態として、粘度が高く流動性
を有していない樹脂材料を用いることもできる。In this embodiment, the isolation wall 13 is formed by using an insulating resin processed into a film shape. However, as another embodiment of the present invention, a resin having a high viscosity and having no fluidity is used. Materials can also be used.
【００６７】（実施形態４）図５は、本発明のさらに他
の実施の形態の光素子の実装構造体４１の概略断面図で
あり、上述の実施の形態に対応する部分には、同一の参
照符号を付す。(Embodiment 4) FIG. 5 is a schematic sectional view of an optical element mounting structure 41 according to still another embodiment of the present invention. Reference numerals are assigned.
【００６８】この実施の形態の光素子の実装構造体４１
も、光素子半導体チップ４を、開口部５が形成された回
路基板６に、異方性導電膜のフィルム１４を用いてフリ
ップチップ実装するものである。The optical element mounting structure 41 of this embodiment
Also, the optical element semiconductor chip 4 is flip-chip mounted on the circuit board 6 in which the opening 5 is formed by using the anisotropic conductive film 14.
【００６９】すなわち、封止樹脂としてフィルム１４を
用いることにより、光素子半導体チップ４の受光領域２
および回路基板６の開口部５への封止樹脂の広がりを抑
制することができる。That is, by using the film 14 as the sealing resin, the light receiving region 2 of the optical element semiconductor chip 4 can be formed.
In addition, the spread of the sealing resin to the opening 5 of the circuit board 6 can be suppressed.
【００７０】この実施の形態の光素子の実装構造体４１
は、上述の実施の形態と基本的に同様にして製造される
ものであり、回路基板６に、該回路基板６の開口部５に
対応する開口を有する異方性導電膜のフィルム１４を配
置し、この回路基板６に、光素子半導体チップ４を、フ
ェイスダウン状態で、その突起電極３が端子電極７上に
対応するように位置合わせを行って回路基板６上に載置
し、高温に加熱、加圧することにより、異方性導電膜の
フィルム１４を硬化させて電気的接続を得るとともに、
樹脂封止を行うものである。The mounting structure 41 of the optical device of this embodiment
Is manufactured basically in the same manner as in the above embodiment, and a film 14 of an anisotropic conductive film having an opening corresponding to the opening 5 of the circuit board 6 is arranged on the circuit board 6. Then, the optical element semiconductor chip 4 is positioned on the circuit board 6 in a face-down state so that the protruding electrodes 3 correspond to the terminal electrodes 7 and placed on the circuit board 6, and the temperature is raised to a high temperature. By heating and pressing, the film 14 of the anisotropic conductive film is cured to obtain an electrical connection,
This is to perform resin sealing.
【００７１】なお、封止樹脂は、異方性導電膜に限ら
ず、他の樹脂フィルムであってもよい。The sealing resin is not limited to the anisotropic conductive film, but may be another resin film.
【００７２】（実施の形態５）図６は、本発明の他の実
施の形態の光素子の実装構造体５１の概略断面図であ
り、上述の実施の形態に対応する部分には、同一の参照
符号を付す。(Embodiment 5) FIG. 6 is a schematic sectional view of an optical element mounting structure 51 according to another embodiment of the present invention. Reference numerals are assigned.
【００７３】この実施の形態の光素子の実装構造体５１
も、光素子半導体チップ４を、開口部５が形成された回
路基板６に、導電性接着剤９を用いてフリップチップ実
装して封止樹脂１０で封止するものである。The optical element mounting structure 51 of this embodiment
Also, the optical element semiconductor chip 4 is flip-chip mounted on the circuit board 6 in which the opening 5 is formed by using a conductive adhesive 9 and sealed with a sealing resin 10.
【００７４】この実施の形態では、封止樹脂１０が、光
素子半導体チップ４の矩形の受光領域２に流れ込んだ
り、あるいは、前記受光領域２に光を導入するための回
路基板６の矩形の開口部５から流れ出るのを防止するた
めに、次のように構成している。In this embodiment, the sealing resin 10 flows into the rectangular light receiving area 2 of the optical element semiconductor chip 4 or a rectangular opening of the circuit board 6 for introducing light into the light receiving area 2. In order to prevent the liquid from flowing out of the section 5, the following configuration is provided.
【００７５】すなわち、この光素子の実装構造体５１の
製造工程を示す図７に示されるように、光素子半導体チ
ップ４を、回路基板６に実装した後、同図（ｂ）に示さ
れるように、回路基板６の開口部５から光素子半導体チ
ップ４の受光領域２に至る空間を閉塞する閉塞体１５を
挿入した状態で、同図（ｃ）に示されるように封止樹脂
１０を注入して硬化させ、その後、閉塞体１０を取り外
すことによって、図６の光素子の実装構造体５１を得る
ものである。That is, as shown in FIG. 7 showing a manufacturing process of the optical element mounting structure 51, after the optical element semiconductor chip 4 is mounted on the circuit board 6, as shown in FIG. Then, a sealing resin 10 is injected as shown in FIG. 3C in a state where a closing body 15 for closing a space from the opening 5 of the circuit board 6 to the light receiving region 2 of the optical element semiconductor chip 4 is inserted. Then, the closing body 10 is removed to obtain the optical element mounting structure 51 shown in FIG.
【００７６】閉塞体１５は、光素子半導体チップ４の受
光領域２への異物の混入を防止して保護する保護膜１６
と、受光領域２に対する密着性を確保しながら高さを調
整するための高さ調整層１７とを備えており、金属や樹
脂などで構成された受け台１８に支持されている。保護
膜１６としては、耐熱性および離型性に優れるテトラフ
ロロエチレン等の材料を用いることができ、高さ調整層
１７としては、封止樹脂硬化後に容易に取り外すことが
でき、再利用が可能な粘土等を用いることができる。The closing body 15 is formed of a protective film 16 for preventing and protecting foreign matter from entering the light receiving region 2 of the optical element semiconductor chip 4.
And a height adjustment layer 17 for adjusting the height while ensuring adhesion to the light receiving region 2, and is supported by a pedestal 18 made of metal, resin, or the like. As the protective film 16, a material such as tetrafluoroethylene having excellent heat resistance and releasability can be used, and as the height adjusting layer 17, it can be easily removed after the sealing resin is cured, and can be reused. Natural clay or the like can be used.
【００７７】このように、封止樹脂１０の注入時には、
光素子半導体チップ４の受光領域２および回路基板６の
開口部５を閉塞するので、封止樹脂１０が、光素子半導
体チップ４の受光領域２に流れ込んだり、あるいは、回
路基板６の矩形の開口部５から流れ出るのを確実に防止
できる。As described above, when the sealing resin 10 is injected,
Since the light receiving area 2 of the optical element semiconductor chip 4 and the opening 5 of the circuit board 6 are closed, the sealing resin 10 flows into the light receiving area 2 of the optical element semiconductor chip 4 or a rectangular opening of the circuit board 6. Flowing out of the part 5 can be reliably prevented.
【００７８】（その他の実施の形態）上述の各実施の形
態では、ダム部１１、ぬれ不良領域１２および隔離壁１
３は、受光領域２などの周囲の全周に亘って設けられた
けれども、必ずしも全周に亘って設ける必要はない。(Other Embodiments) In each of the above embodiments, the dam 11, the poor wetting area 12, and the isolation wall 1
Although the reference numeral 3 is provided over the entire periphery of the light receiving area 2 and the like, it is not always necessary to provide the reference numeral 3 over the whole periphery.
【００７９】また、上述の各実施の形態では、受光領域
２および開口部５は、矩形であったけれども、矩形に限
らず、円形、その他の形状であってもよい。Further, in each of the above-described embodiments, the light receiving region 2 and the opening 5 are rectangular, but are not limited to a rectangle, and may be a circle or another shape.
【００８０】上述の実施の形態では、光素子としてＣＣ
Ｄに適用して説明したけれども、ＣＣＤに限らず、フォ
トダイオードやその他の光素子に適用してもよい。In the above embodiment, the optical element is CC
Although described with reference to D, the invention is not limited to CCD, but may be applied to photodiodes and other optical elements.
【００８１】また、上述の各実施の形態を適宜組み合わ
せてもよく、例えば、実施の形態５と実施の形態２とを
組み合わせてもよい。Further, the above embodiments may be appropriately combined, for example, the fifth embodiment and the second embodiment may be combined.
【００８２】[0082]
【発明の効果】以上のように本発明によれば、光素子半
導体チップの受光領域あるいは回路基板の開口部の周囲
にダム部を設けたので、封止樹脂の受光領域や開口部へ
の広がりを防止することができ、良好な特性の光素子の
実装構造体を得ることができる。しかも、ダム部の形成
材料にレジストや銅箔を用いることにより、効率よくダ
ム部を形成することが可能となり、安価に実現できる。As described above, according to the present invention, since the dam portion is provided around the light receiving region of the optical element semiconductor chip or the opening of the circuit board, the sealing resin spreads to the light receiving region and the opening. Can be prevented, and a mounting structure of an optical element having good characteristics can be obtained. In addition, by using a resist or a copper foil as a material for forming the dam portion, the dam portion can be efficiently formed and can be realized at low cost.
【００８３】また、光素子半導体チップの受光領域ある
いは回路基板の開口部の周囲に、封止樹脂のぬれ性を阻
害するぬれ不良領域を設けたので、封止樹脂の受光領域
や開口部への広がりを抑制することができる。Further, since a wetting failure region which hinders the wettability of the sealing resin is provided around the light receiving region of the optical element semiconductor chip or the opening of the circuit board, the sealing resin has a poor ability to cover the light receiving region and the opening. Spread can be suppressed.
【００８４】また、光素子半導体チップの受光領域の周
囲には、該光素子半導体チップと回路基板との間に亘っ
て隔離壁が設けられるので、封止樹脂が、光素子半導体
チップの受光領域へ流れ込んだり、回路基板の開口部か
ら流れ出すのを一層確実に防止することができる。Further, since an isolation wall is provided around the light receiving area of the optical element semiconductor chip and between the optical element semiconductor chip and the circuit board, the sealing resin is applied to the light receiving area of the optical element semiconductor chip. And flowing out from the opening of the circuit board can be prevented more reliably.
【００８５】さらに、フィルム状の封止樹脂を硬化させ
て光素子半導体チップと回路基板との間の封止を行うの
で、封止樹脂の硬化時の広がりを抑制することが可能と
なり、光素子半導体チップの受光領域へ流れ込んだり、
回路基板の開口部から流れ出すのを防止することができ
る。Furthermore, since the sealing between the optical element semiconductor chip and the circuit board is performed by curing the film-shaped sealing resin, it is possible to suppress the spread of the sealing resin during curing, and to reduce the optical element. Flowing into the light receiving area of the semiconductor chip,
It can be prevented from flowing out of the opening of the circuit board.
【００８６】また、回路基板の開口部から光素子半導体
チップの受光領域に至る空間を閉塞した状態で、封止樹
脂を注入して硬化させので、封止樹脂が、光素子半導体
チップの受光領域へ流れ込んだり、回路基板の開口部か
ら流れ出すといったことがない。Further, the sealing resin is injected and cured in a state where the space from the opening of the circuit board to the light receiving area of the optical element semiconductor chip is closed, so that the sealing resin is applied to the light receiving area of the optical element semiconductor chip. Into the circuit board or out of the opening in the circuit board.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一つの実施の形態の光素子の実装構造
体の概略断面図である。FIG. 1 is a schematic sectional view of a mounting structure for an optical element according to an embodiment of the present invention.
【図２】図１の製造工程を示す概略断面図である。FIG. 2 is a schematic sectional view showing a manufacturing process of FIG.
【図３】本発明の他の実施の形態の光素子の実装構造体
の概略断面図である。FIG. 3 is a schematic sectional view of a mounting structure of an optical element according to another embodiment of the present invention.
【図４】本発明のさらに他の実施の形態の光素子の実装
構造体の概略断面図である。FIG. 4 is a schematic sectional view of a mounting structure of an optical element according to still another embodiment of the present invention.
【図５】本発明の他の実施の形態の光素子の実装構造体
の概略断面図である。FIG. 5 is a schematic sectional view of a mounting structure for an optical element according to another embodiment of the present invention.
【図６】本発明のさらに他の実施の形態の光素子の実装
構造体の概略断面図である。FIG. 6 is a schematic sectional view of a mounting structure for an optical element according to still another embodiment of the present invention.
【図７】図６の製造工程を示す概略断面図である。FIG. 7 is a schematic sectional view showing the manufacturing process of FIG. 6;
１，２１，３１，４１，５１ 光素子の実装構
造体 ２ 受光領域 ３ 突起電極 ４ 光素子半導体チ
ップ ５ 開口部 ６ 回路基板 １０ 封止樹脂 １１ ダム部 １２ ぬれ不良領域 １３ 隔離壁 １５ 閉塞体1, 21, 31, 41, 51 Optical element mounting structure 2 Light receiving area 3 Protruding electrode 4 Optical element semiconductor chip 5 Opening 6 Circuit board 10 Sealing resin 11 Dam section 12 Wetting failure area 13 Isolation wall 15 Closure
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 27/14 Ｈ０４Ｎ 5/335 Ｖ ５Ｆ０８８ 31/02 Ｈ０１Ｌ 27/14 Ｄ // Ｈ０４Ｎ 5/335 31/02 Ｂ (72)発明者 林 祥剛 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 4M109 AA01 BA04 BA05 CA06 DA06 DB07 DB08 DB12 EA02 GA01 4M118 AA08 AA10 BA10 CA02 GA02 HA11 HA20 HA24 HA31 5C024 CY47 CY48 5F044 KK01 LL07 5F061 AA01 BA04 CA06 CA26 FA01 5F088 BA10 BA13 JA01 JA06 JA20──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 27/14 H04N 5/335 V 5F088 31/02 H01L 27/14 D // H04N 5/335 31/02 B (72) Inventor Shogo Hayashi 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture F-term (reference) 4M109 AA01 BA04 BA05 CA06 DA06 DB07 DB08 DB12 EA02 GA01 4M118 AA08 AA10 BA10 CA02 GA02 HA11 HA20 HA24 HA31 5C024 CY47 CY48 5F044 KK01 LL07 5F061 AA01 BA04 CA06 CA26 FA01 5F088 BA10 BA13 JA01 JA06 JA20
Claims (20)
成されている光素子半導体チップを、前記受光領域に相
対する領域に開口部が形成された回路基板にフリップチ
ップ実装してなる光素子の実装構造体であって、 前記光素子半導体チップの前記受光領域の周囲および前
記回路基板の前記開口部の周囲の少なくとも一方には、
前記光素子半導体チップと前記回路基板との間に注入さ
れる封止樹脂を堰き止めるダム部を設けたことを特徴と
する光素子の実装構造体。1. An optical element comprising: an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface side; and a flip chip mounted on a circuit board having an opening formed in a region facing the light receiving region. Wherein at least one of the periphery of the light receiving region of the optical element semiconductor chip and the periphery of the opening of the circuit board,
A mounting structure for an optical element, comprising a dam portion for damping a sealing resin injected between the optical element semiconductor chip and the circuit board.
流動特性を有さない材料からなる請求項１記載の光素子
の実装構造体。2. The optical element mounting structure according to claim 1, wherein the dam portion is made of a material having no flow characteristics when the sealing resin is injected.
載の光素子の実装構造体。3. The mounting structure for an optical element according to claim 2, wherein the material is a resist.
の銅箔を用いて電気回路構成を担うことなく前記ダム部
とする請求項２記載の光素子の実装構造体。4. The mounting structure for an optical element according to claim 2, wherein the dam portion is formed by using a copper foil for forming wiring of a circuit board as the material without forming an electric circuit.
を施さずに酸化層が形成されている請求項４記載の光素
子の実装構造体。5. The optical element mounting structure according to claim 4, wherein an oxide layer is formed without plating on a surface of the dam portion made of the copper foil.
成されている光素子半導体チップを、前記受光領域に相
対する領域に開口部が形成された回路基板にフリップチ
ップ実装してなる光素子の実装構造体であって、 前記光素子半導体チップの前記受光領域の周囲および前
記回路基板の前記開口部の周囲の少なくとも一方には、
前記光素子半導体チップと前記回路基板との間に注入さ
れる封止樹脂のぬれ性を阻害するぬれ不良領域を設けた
ことを特徴とする光素子の実装構造体。6. An optical element in which an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface side is flip-chip mounted on a circuit board having an opening formed in a region facing the light receiving region. Wherein at least one of the periphery of the light receiving region of the optical element semiconductor chip and the periphery of the opening of the circuit board,
A mounting structure for an optical element, wherein a wetting failure region that inhibits the wettability of a sealing resin injected between the optical element semiconductor chip and the circuit board is provided.
の周囲または前記回路基板の前記開口部の周囲の一方に
は、前記ぬれ不良領域を設け、他方には、前記封止樹脂
をせき止めるダム部を設けた請求項６記載の光素子の実
装構造体。7. A dam portion for providing the wetting failure region at one of the periphery of the light receiving region of the optical element semiconductor chip or the periphery of the opening of the circuit board, and the other dam portion for damping the sealing resin. The mounting structure for an optical element according to claim 6, further comprising:
成されている光素子半導体チップを、前記受光領域に相
対する領域に開口部が形成された回路基板にフリップチ
ップ実装してなる光素子の実装構造体であって、 前記光素子半導体チップの前記受光領域の周囲には、該
光素子半導体チップと前記回路基板とを繋ぐ隔離壁が設
けられることを特徴とする光素子の実装構造体。8. An optical element in which an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface side is flip-chip mounted on a circuit board having an opening formed in a region facing the light receiving region. The mounting structure of the optical element, wherein an isolation wall connecting the optical element semiconductor chip and the circuit board is provided around the light receiving region of the optical element semiconductor chip. .
項８記載の光素子の実装構造体。9. The mounting structure for an optical element according to claim 8, wherein the isolation wall is made of an insulating resin.
チップと前記回路基板との間に注入される封止樹脂の硬
化前に、該封止樹脂よりも粘度の高い樹脂またはフィル
ム状に形成された樹脂である請求項９記載の光素子の実
装構造体。10. The insulating resin is formed into a resin or film having a higher viscosity than the sealing resin before the sealing resin injected between the optical element semiconductor chip and the circuit board is cured. The mounting structure for an optical element according to claim 9, wherein the mounting structure is made of a resin.
形成されている光素子半導体チップを、前記受光領域に
相対する領域に開口部が形成された回路基板にフリップ
チップ実装してなる光素子の実装構造体であって、 前記受光領域に対応する領域が開口されたフィルム状の
封止樹脂を硬化させて前記光素子半導体チップと前記回
路基板との間の封止を行うことを特徴とする光素子の実
装構造体。11. An optical element in which an optical element semiconductor chip having a light receiving region and a connection terminal formed on the same surface side is flip-chip mounted on a circuit board having an opening formed in a region facing the light receiving region. The mounting structure of the above, wherein sealing between the optical element semiconductor chip and the circuit board is performed by curing a film-shaped sealing resin having an area corresponding to the light receiving area opened. Optical element mounting structure.
求項１１記載の光素子の実装構造体。12. The mounting structure according to claim 11, wherein the sealing resin is an anisotropic conductive film.
き止めるダム部が形成された光素子半導体チップを、前
記受光領域と相対する領域に開口部が形成されている回
路基板にフリップチップ実装し、フリップチップ実装後
に前記封止樹脂を注入して硬化させることを特徴とする
光素子の実装構造体の製造方法。13. An optical element semiconductor chip in which a dam portion for damping a sealing resin is formed around the light receiving region, and a flip chip is mounted on a circuit board having an opening formed in a region opposed to the light receiving region. A method of manufacturing a mounting structure for an optical element, comprising mounting, flip-chip mounting, and injecting and sealing the sealing resin.
する領域に開口部が形成されるとともに、前記開口部の
周囲に、封止樹脂を堰き止めるダム部が形成されている
回路基板に、前記光素子半導体チップをフリップチップ
実装し、フリップチップ実装後に封止樹脂を注入して硬
化させることを特徴とする光素子の実装構造体の製造方
法。14. A circuit board, wherein an opening is formed in a region facing a light receiving region of an optical element semiconductor chip, and a dam portion for damping a sealing resin is formed around the opening. A method for manufacturing a mounting structure for an optical element, comprising: mounting an optical element semiconductor chip by flip chip mounting; and injecting and sealing a sealing resin after the flip chip mounting.
性を阻害するぬれ不良領域が形成された光素子半導体チ
ップを、前記受光領域と相対する領域に開口部が形成さ
れている回路基板に、フリップチップ実装し、フリップ
チップ実装後に前記封止樹脂を注入して硬化させること
を特徴とする光素子の実装構造体の製造方法。15. A circuit in which an optical element semiconductor chip having a non-wetting region that inhibits wettability with a sealing resin is formed around a light receiving region, and an opening is formed in a region facing the light receiving region. A method for manufacturing an optical element mounting structure, comprising: mounting a flip-chip on a substrate; and injecting and curing the sealing resin after the flip-chip mounting.
する領域に開口部が形成されるとともに、前記開口部の
周囲に、封止樹脂のぬれ性を阻害するぬれ不良領域が形
成された回路基板に、前記光素子半導体チップをフリッ
プチップ実装し、フリップチップ実装後に前記封止樹脂
を注入して硬化させることを特徴とする光素子の実装構
造体の製造方法。16. A circuit board in which an opening is formed in a region facing a light receiving region of an optical element semiconductor chip, and a wetting failure region is formed around the opening to impair the wettability of a sealing resin. A method of manufacturing the optical element mounting structure, wherein the optical element semiconductor chip is flip-chip mounted, and the sealing resin is injected and cured after the flip-chip mounting.
する領域に開口部が形成されている回路基板の前記開口
部の周囲に絶縁性樹脂からなるフィルムを配置し、前記
回路基板に、前記光素子半導体チップをフリップチップ
実装するとともに、前記フィルムを硬化させ、封止樹脂
を注入して硬化させることを特徴とする光素子の実装構
造体の製造方法。17. A film made of an insulating resin is disposed around an opening of a circuit board having an opening formed in a region opposed to a light receiving region of an optical element semiconductor chip, and the light is applied to the circuit board. A method for manufacturing a mounting structure for an optical element, comprising: mounting an element semiconductor chip by flip-chip; curing the film; and injecting and curing a sealing resin.
端子の外方から内方へ注入するとともに、前記外方と前
記内方との圧力差を利用して供給する請求項１７記載の
光素子の実装構造体の製造方法。18. The method according to claim 17, wherein the sealing resin is injected from outside to inside of the connection terminal of the circuit board, and is supplied by utilizing a pressure difference between the outside and the inside. A method for manufacturing an optical element mounting structure.
する領域に開口部が形成されている回路基板に、前記開
口部に対応して開口された樹脂フィルムを配置し、前記
光素子半導体チップを前記回路基板に圧接させて前記樹
脂フィルムを硬化させてフリップチップ実装することを
特徴とする光素子の実装構造体の製造方法。19. A resin film having an opening corresponding to the opening is disposed on a circuit board having an opening formed in a region opposed to a light receiving region of the optical device semiconductor chip, and the optical device semiconductor chip is mounted on the circuit board. A method for manufacturing a mounting structure for an optical element, wherein the resin film is cured by being brought into pressure contact with the circuit board and flip-chip mounted.
する領域に開口部が形成されている回路基板に、前記光
素子半導体チップをフリップチップ実装し、前記開口部
から前記光素子半導体チップの受光領域に至る空間を閉
塞する閉塞体を挿入した状態で、封止樹脂を注入して硬
化させ、前記閉塞体を取り外すことを特徴とする光素子
の実装構造体の製造方法。20. The optical element semiconductor chip is flip-chip mounted on a circuit board having an opening formed in a region opposed to a light receiving region of the optical device semiconductor chip, and light is received from the optical element semiconductor chip through the opening. A method for manufacturing a mounting structure for an optical element, characterized in that a sealing resin is injected and cured in a state in which a closing member for closing a space leading to a region is inserted, and the closing member is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000059921A JP2001250889A (en) | 2000-03-06 | 2000-03-06 | Mounting structure of optical element and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000059921A JP2001250889A (en) | 2000-03-06 | 2000-03-06 | Mounting structure of optical element and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001250889A true JP2001250889A (en) | 2001-09-14 |
Family
ID=18580313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000059921A Pending JP2001250889A (en) | 2000-03-06 | 2000-03-06 | Mounting structure of optical element and its manufacturing method |
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| Country | Link |
|---|---|
| JP (1) | JP2001250889A (en) |
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