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JPS6381895A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPS6381895A
JPS6381895A JP22644086A JP22644086A JPS6381895A JP S6381895 A JPS6381895 A JP S6381895A JP 22644086 A JP22644086 A JP 22644086A JP 22644086 A JP22644086 A JP 22644086A JP S6381895 A JPS6381895 A JP S6381895A
Authority
JP
Japan
Prior art keywords
circuit wiring
copper
wiring board
printed wiring
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22644086A
Other languages
Japanese (ja)
Inventor
藤木 勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elna Co Ltd
Original Assignee
Elna Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elna Co Ltd filed Critical Elna Co Ltd
Priority to JP22644086A priority Critical patent/JPS6381895A/en
Publication of JPS6381895A publication Critical patent/JPS6381895A/en
Pending legal-status Critical Current

Links

Landscapes

  • Paper (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、プリント配線板の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a printed wiring board.

〔発明の技術的な背七I] 電−FR器の小型化あるいは軽量化に伴うプリンKPi
?、′La板の回路配線の高密度化と相俟って、同一配
線板にマイクロプロセッサなどを小電流で動作させるた
めの小電流回路配線と、大電流により外部機器を作動さ
せるための大電流回路配線あるいは電源回路配線とが間
接して設けられることが多い。A常、この小電流回路配
線と大電流回路配線とは同一厚さの導体層(銅層)から
なフているので、小電流回路配線に対して大電流回路配
線に流れる電流の許容電流を増大させるにはその配線幅
を拡大している。1ノかし、このように配線幅を拡大す
ると、プリント配線板の回路配線の高密度化を図ること
が[41fiなものとなっている。
[Technical background 7I of the invention] Purin KPi due to the miniaturization or weight reduction of electric FR equipment
? , 'In conjunction with the increased density of circuit wiring on La boards, the same wiring board now has low-current circuit wiring to operate microprocessors and other devices with small currents, and large-current circuit wiring to operate external devices with large currents. It is often provided indirectly with circuit wiring or power supply circuit wiring. A: Usually, the small current circuit wiring and the high current circuit wiring are made of a conductor layer (copper layer) of the same thickness, so the allowable current that flows through the large current circuit wiring is different from that of the small current circuit wiring. To increase this, the wiring width is expanded. However, expanding the wiring width in this way makes it possible to increase the density of circuit wiring on a printed wiring board.

[発明のL]的] しかるに、本発明は大電流回路配線に流れる電流の許容
電流を配線幅を拡大することによフて増大させるのでは
なく、配線部を17くすることによって増大させ、許容
電流の異なる回路配線の高密度化を図るものである。具
体的には部分アディテイブ法を改良することによってこ
打を実現したものてあ/:)6 [実施例] 以ト、本発明の一実施例をN面と共に説明する。説明四
二先−・γって、この実施例では両面のプリント配線板
について説明するか、片面のブリット配線板についても
同様であるのでその説明は省略する。
[L of the invention] However, the present invention does not increase the allowable current flowing through the large current circuit wiring by expanding the wiring width, but by increasing the number of wiring parts by 17, This is intended to increase the density of circuit wiring with different allowable currents. Specifically, this was achieved by improving the partial additive method./:)6 [Example] Hereinafter, an example of the present invention will be described together with the N-side. Explanation 42--.gamma. In this embodiment, a double-sided printed wiring board will be explained, and since the same applies to a single-sided printed wiring board, the explanation thereof will be omitted.

先ず、第1図(A)に示すように両面鋼張積層板(1)
を用意する。(2)は銅箔であり、その厚さとしては例
えば18μmあるいは35μm(7)ものかある。そし
て、スルーホールを形成するため1二、同図(B)に示
すように透孔(3)を穿設し、活性化処理し、透孔(3
)の内壁および積層板(1)の表面に同図(C)に示す
ように銅メッキの核(4)、通常はパラジウム核を析出
させる。引続き、同1fi(D)に示すように積層板(
1)の全面に化学鋼メッキあるいは電解錫メケキ、つま
りパネルメッキを施し、第1の銅メ・戸キ層(5)を形
成する。
First, as shown in Figure 1 (A), a double-sided steel clad laminate (1)
Prepare. (2) is a copper foil whose thickness is, for example, 18 μm or 35 μm (7). Then, in order to form a through hole, a through hole (3) is drilled as shown in FIG.
) and on the surface of the laminate (1), copper plating nuclei (4), usually palladium nuclei, are deposited as shown in Figure (C). Subsequently, as shown in 1fi (D), a laminate (
Chemical steel plating or electrolytic tin plating, that is, panel plating, is applied to the entire surface of 1) to form a first copper plating layer (5).

このシメ・tキ処理浅、第2図(E)に示すように透孔
(3)の両端間[1部を例えば感光性フィル!、 (6
)により密↓干してその孔壁を保護−6−ると共に、−
張積層k(1)の表裏の所要箇所に回路配線を形成する
ための同感光性フィルム(6)によるエツチングレジス
トを形成する。この感光性フィルム(6)に代えてイン
ク化埋め印刷法などにより透孔(3)の孔壁を保護する
こともできる。
After this seam/cutting process is performed, as shown in FIG. , (6
) to protect the hole wall and dry it tightly.
Etching resists are formed using the same photosensitive film (6) for forming circuit wiring at required locations on the front and back sides of the tension laminate k (1). Instead of using this photosensitive film (6), the walls of the through holes (3) can also be protected by an ink filling printing method or the like.

第1の銅メッキ層(5)および潟箔(2)のエツチング
処理後、第2し1(F)に2部才ようにニーyチングレ
シスト(6)を711離し、回路配線を保護するための
半[Hレジストである永久レジスト(7)を同図(G)
に示すよ・)形成する。
After etching the first copper plating layer (5) and the lagoon foil (2), the kneeling resist (6) is separated by 711 points in the second layer (F) to protect the circuit wiring. The permanent resist (7), which is a semi-H resist, is shown in the same figure (G).
As shown in )).

この永久レジスl−(’lを形成するとき、大電流容t
を必要とする大電流回路配線(8)部分にはこの木矢レ
ジスト(7)を形成しないようにする。そして、再びf
ヒ学銅メッキあるいは電解銅メ・Iキを施すと、7pJ
z図(H)に示すように永久レジスト(7)の形成さ打
ていない大電流回路配線(8)部分およびスルーホール
く9)には第2の銅メッキ層(10)か形成される。第
2の銅メッキ層(10) rンは25〜35μm程度で
ある。
When forming this permanent resistor l-('l, large current capacity t
This wooden arrow resist (7) should not be formed on the portion of the high current circuit wiring (8) that requires a high voltage. And again f
When applied with Higaku copper plating or electrolytic copper plating, 7 pJ
As shown in Figure z (H), a second copper plating layer (10) is formed on the large current circuit wiring (8) and through holes 9) where the permanent resist (7) is not formed. The thickness of the second copper plating layer (10) is approximately 25 to 35 μm.

最後に、プリント配線板上に数値、文字、マークなどを
表示するだめの文字印刷工程を利用して1;第1時に露
出している大電流回路配線部分をヱ21ズ(1)に示す
ように文字印刷用インク層(11)によって被覆する。
Finally, by using the character printing process to display numbers, characters, marks, etc. on the printed wiring board, the high current circuit wiring part exposed at the first step was printed as shown in E21 (1). is coated with a character printing ink layer (11).

このような一連の工程によって未発明に係るプリント配
線板(12)を得る。
Through such a series of steps, a printed wiring board (12) according to the invention is obtained.

[効果] 以−1−にて述べた本発明によると、大電流8星を要す
る回路配線のみその配線部を第7〈シたものであるため
、非常に経済的てあり、また小′:+4L流回路配線と
大電流回路配線とを高密度で同一のプリント配線板に形
成することかできるものである。
[Effects] According to the present invention described in -1- below, only the circuit wiring that requires a large current of 8 stars has its wiring part reduced to 7th, so it is very economical and small. +4L flow circuit wiring and large current circuit wiring can be formed at high density on the same printed wiring board.

4、[)1而の簡litな説明 第1図および第2図は本発明に係る欠へ法を示す工程図
である。
4. Brief explanation of [1] Figures 1 and 2 are process diagrams showing the cutting method according to the present invention.

図中、(1)・・・鋼張積層板、  (2)・・・銅τ
^、  (3)・・・透孔、  (4)・・・メ・ツキ
の核、(5)、(10)・・・t4メッキ層、(6)・
・・エツチングレジスト、(7)・・・永久レジスト、
  (8)・・・大電流回路配線、(9)・・・スルー
ホール、  (11)・−・文字印刷用インク層、  
(12)・・・プリント配線板。
In the figure, (1)...Steel clad laminate, (2)...Copper τ
^, (3)...Through hole, (4)...Medical core, (5), (10)...T4 plating layer, (6)...
...Etching resist, (7)...Permanent resist,
(8)...High current circuit wiring, (9)...Through hole, (11)...Ink layer for character printing,
(12)...Printed wiring board.

り、ν訂出願人 エルナー株式会社 第1図 第2図 くri, ν revision applicant: ELNA Co., Ltd. Figure 1 Figure 2 Ku

Claims (1)

【特許請求の範囲】 [1]銅張積層板に透孔を穿設し、活性化処理した後に
銅張積層板の全面に銅メッキする工程と、透孔の孔壁を
保護すると共に銅張積層板の少なくともいずれか一面の
所要箇所に回路配線を形成するためのエッチングレジス
トを形成しでエッチングする工程と、 エッチングレジストの剥離後、永久レジストを形成し、
永久レジストの形成されていない回路配線部分をさらに
銅メッキする工程と、 銅メッキされた回路配線部分を文字印刷用インク層にて
被覆する工程と、 からなるプリント配線板の製造方法。
[Scope of Claims] [1] A step of drilling a through hole in a copper clad laminate, plating the entire surface of the copper clad laminate with copper after activation treatment, and protecting the hole wall of the through hole and plating the copper clad laminate with copper. forming and etching an etching resist for forming circuit wiring at a required location on at least one side of the laminate; after peeling off the etching resist, forming a permanent resist;
A method for manufacturing a printed wiring board, comprising the steps of: further plating the circuit wiring portions on which no permanent resist is formed with copper; and covering the copper-plated circuit wiring portions with a layer of character printing ink.
JP22644086A 1986-09-25 1986-09-25 Manufacture of printed wiring board Pending JPS6381895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22644086A JPS6381895A (en) 1986-09-25 1986-09-25 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22644086A JPS6381895A (en) 1986-09-25 1986-09-25 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPS6381895A true JPS6381895A (en) 1988-04-12

Family

ID=16845141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22644086A Pending JPS6381895A (en) 1986-09-25 1986-09-25 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPS6381895A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5067457A (en) * 1973-10-20 1975-06-06
JPS5766696A (en) * 1980-10-13 1982-04-22 Kanto Kasei Kogyo Method of producing printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5067457A (en) * 1973-10-20 1975-06-06
JPS5766696A (en) * 1980-10-13 1982-04-22 Kanto Kasei Kogyo Method of producing printed circuit board

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