JPS636916A - High voltage current interrupting circuit - Google Patents
High voltage current interrupting circuitInfo
- Publication number
- JPS636916A JPS636916A JP14936686A JP14936686A JPS636916A JP S636916 A JPS636916 A JP S636916A JP 14936686 A JP14936686 A JP 14936686A JP 14936686 A JP14936686 A JP 14936686A JP S636916 A JPS636916 A JP S636916A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- parallel
- snubber
- clamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000008033 biological extinction Effects 0.000 abstract description 3
- 230000006378 damage Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
Landscapes
- Thyristor Switches And Gates (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、自己消弧型半導体素子全直列接続して構成
される高圧’[流しゃ断回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a high-voltage current cutoff circuit constructed by connecting all self-extinguishing semiconductor elements in series.
この種のt流しゃ断回路として、従来は1iHJえば第
4図に示すチョッパ回路が知られている。これは同図に
一点鎖線で示す様に、自己消弧型半導体素子の1つであ
るGTOサイリスタ3.4を直列接続してダイオード9
.lOとコンデンサ12゜13と抵抗t’y、isから
なるスナバ回路と直流分圧抵抗22.23t−それぞれ
のGTOサイリスタ3.4と並列に接続して構成される
。このチョッパ回路において、GTOサイリスタ3.4
がオンしていて負荷電流imt通流している状態がらG
TOサイリスタ3,4をオフさせ次時のGTOサイリス
タ3,4のアノード電流II l i2 、 スナバ
コンデンサ12.13の電流1g1 r ’82 、ス
ナバコンデンサ12,13の電圧V1.V2 お工び一
点鎖線で示した電流しゃ断回路の電流jの各波形を第5
図に示す。同図において、GTOサイリスタ3および4
け同時には消弧せず、Δtだけ消弧時刻に差があるもの
とする。すなわち、GTOサイリスタ4は時Ntaで高
抵抗となってその7ノード電流をスナバ回路へ転流し、
そのΔ仁後でめる時刻tbでGTOサイリスタ3が同様
の動作をする。時刻tc でスナバコンデ/す12お工
び13の電圧の和、すなわちこのtt流しゃ断回路の電
圧vl + v、が第4図のスナバコンデンサ14の電
圧Edに等しくなってスナバダイオード11がオンし、
これ以降この電流しゃ断回路の電流は第4図のスナバコ
ンデンサ14へ転流し、さらに負荷抵抗7および負荷イ
ンダクタンス8の電流はフリーホイーリングダイオード
5.6へ転流して時刻tdでこの電流しゃ断回路の電流
lは零となる。時刻tdにおけるスナバコンデ/す12
および13の電圧、すなわちGTOサイリスタ3および
4のアノード電圧V、およびV、は等しくなく、vl<
v2となる。これは。As this type of t-flow cutoff circuit, a chopper circuit shown in FIG. 4 has been known for 1iHJ. As shown by the dashed line in the figure, GTO thyristor 3.4, which is one of the self-extinguishing semiconductor elements, is connected in series to form diode 9.
.. A snubber circuit consisting of lO, capacitors 12 and 13, resistors t'y and is, and DC voltage dividing resistors 22 and 23t are connected in parallel with respective GTO thyristors 3 and 4. In this chopper circuit, GTO thyristor 3.4
While G is on and load current imt is flowing
When the TO thyristors 3 and 4 are turned off, the next time the anode current II l i2 of the GTO thyristors 3 and 4, the current 1g1 r '82 of the snubber capacitor 12.13, and the voltage V1 of the snubber capacitor 12 and 13 are set. V2 Each waveform of the current j of the current cutoff circuit shown by the dashed line is
As shown in the figure. In the same figure, GTO thyristors 3 and 4
It is assumed that the arc does not extinguish at the same time, and there is a difference in arc extinguishing time by Δt. That is, the GTO thyristor 4 has a high resistance at time Nta and commutates the 7 node current to the snubber circuit,
The GTO thyristor 3 operates in a similar manner at time tb determined after the Δin. At time tc, the sum of the voltages of the snubber capacitor 12 and 13, that is, the voltage vl + v of this tt current cutoff circuit, becomes equal to the voltage Ed of the snubber capacitor 14 in FIG. 4, and the snubber diode 11 is turned on.
From then on, the current in this current cutoff circuit is commutated to the snubber capacitor 14 in FIG. The current l becomes zero. Snubber conditioner/su12 at time td
and 13, that is, the anode voltages V and V of GTO thyristors 3 and 4 are not equal, and vl<
It becomes v2. this is.
GTOサイリスタ3および4の消弧時刻の差Δtに起因
するもので、 VlとV、の差電圧らはスナバコンデ
ンサ12.13の容t’tc、 として次式に1って
与えられる。This is due to the difference Δt between the extinguishing times of the GTO thyristors 3 and 4, and the difference voltage between Vl and V is given by the following equation with the capacity t'tc of the snubber capacitor 12.13 as follows.
すなわち、GTOサイリスタ3お工び4の消弧時刻の差
Δtに比例して時刻tdにおけるスナバコンデンサ12
および13の電圧差E6が増大し、先に消弧したGTO
サイリスタ4の時刻tdでの電圧7重が増大することに
なる。この電圧V!がGTOサイリスタ4の耐圧以下で
あれば、GTOサイリスタ4は過電圧破壊することはな
いが、GTOサイリスタ3および4の消弧側の差Δtが
ろる値以上でるると、この電流しゃ断回路の電流iが零
になる時刻td以前にGTOサイリスタ4の7ノード電
圧V、がその耐圧を越え、GTOサイリスタ4は過電圧
破壊してしまう。例えば、耐圧2.5にV、可制御電流
lに人のGTOサイリスタでは、直列数1の時の消弧時
アノード電圧上昇率抑制に必要なスナバコンデンサ容t
は2μFで6D、 このGTOサイリスタをこの電流し
ゃ断回路へ適用してlKNしゃ断し九時の、先に消弧す
るGTOサイリスタ4の時刻t、からtetでのアノー
ド電圧上昇率は。In other words, the snubber capacitor 12 at time td is proportional to the difference Δt between the extinguishing times of the GTO thyristors 3 and 4.
and 13 voltage difference E6 increases, and the GTO which extinguished first
The voltage of the thyristor 4 at time td increases by 7 times. This voltage V! If is less than the withstand voltage of GTO thyristor 4, GTO thyristor 4 will not be destroyed by overvoltage. However, if the difference Δt between the extinguishing side of GTO thyristors 3 and 4 exceeds the failure value, the current in this current cutoff circuit will decrease. Before the time td when i becomes zero, the 7-node voltage V of the GTO thyristor 4 exceeds its withstand voltage, and the GTO thyristor 4 is destroyed by overvoltage. For example, in a GTO thyristor with a withstand voltage of 2.5 V and a controllable current of 1, the snubber capacitor capacity t required to suppress the rate of increase in anode voltage during extinguishing when the number of series connections is 1 is
is 2μF and 6D.The rate of increase in anode voltage from time t to tet of GTO thyristor 4, which is first extinguished at 9 o'clock when this GTO thyristor is applied to this current cutoff circuit to cut off lKN, is:
dvl 、、’a t = l (に人”l/2 Cp
’F 1−500 (v/μs)でるることから1例え
ばΔt=1(μB〕としてもE、 =500 (V)と
なり、耐圧2.5にYのGTOサイリスタにとって非常
に厳しい1直でろる。また、GTOサイリスタの消弧時
刻の差Δt、すなわちター7オフ時間のバラツキを使用
されるすべての接合温度においでlps以下にそろえる
ことは非常に困難でろるので、従来はスナバコンデンサ
12.13の容tea1に直列数1の場合に必要であっ
た容Lcり増加式せて時刻t、から1c1でのdvt/
dt2減少させ、時刻tdに2ける先に消弧したGTO
サイリスタ4のアノード電圧v、ヲその耐圧以下となる
ようにしている。dvl ,,'a t = l (ni person"l/2 Cp
'F 1-500 (v/μs), so even if Δt = 1 (μB), E = 500 (V), which is a very difficult 1 shift for a GTO thyristor with a breakdown voltage of 2.5 Y. In addition, it is very difficult to make the difference Δt in the extinction time of the GTO thyristor, that is, the variation in the off time of the GTO thyristor, to less than lps at all junction temperatures used, so conventionally a snubber capacitor 12.13 dvt/ from time t to 1c1
GTO whose arc was decreased by dt2 and extinguished first by 2 at time td
The anode voltage v of the thyristor 4 is set to be less than its withstand voltage.
ところがこの様なI!流しゃ断回路では、スナバ1;
l !
(2C6v 1 ”およびg C8v2 ” )は、G
TOサイリスタ3および4の次の点弧までの期間とその
直後にスナバ抵抗17および18によってすべて消費葛
れてスナバコンデンサ12お工び13の電圧は零となる
ので、スナバコンデ/す12おLびI3の容量C,’(
r増加することは、この電流しゃ断回路の損失をこれに
比例して増大させてしまうことになる、という問題がめ
る。However, I like this! In a flow cutoff circuit, snubber 1; l! (2C6v 1 ” and g C8v2 ”) is G
During the period until the next firing of TO thyristors 3 and 4 and immediately thereafter, the snubber capacitor 12 and 13 are completely consumed by the snubber resistors 17 and 18 and the voltage of the snubber capacitor 12 and 13 becomes zero. Capacity C,'(
A problem arises in that an increase in r causes a proportional increase in the loss of this current cutoff circuit.
したがって、この発明は直列接続された自己消弧型半導
体素子のターンオフ時間のバラツキに起因する電圧分担
不平衡による素子の過電圧破壊を。Therefore, the present invention prevents overvoltage breakdown of devices due to unbalanced voltage distribution caused by variations in turn-off time of self-extinguishing semiconductor devices connected in series.
低損失で防止する電流しゃ断回路を提供することを目的
とする。The purpose is to provide a current cutoff circuit that prevents current loss with low loss.
直列接続され次自己消弧型半導体素子にダイオードとコ
ンデンサと抵抗からなり、消弧時の面圧上昇率を抑制す
るスナバ回路をそれぞれ並列接続してなる電流しゃ断回
路に、素子の耐圧よジも低い電圧クランプ回路を素子そ
れぞれに並列接続する口
〔作 用〕
こうすることにより、素子のターンオフ時間のバラツキ
に起因する電圧分担不平衡による素子の過電圧破壊を、
素子消弧時の電圧上昇率抑制用スナバ回路のスナバコン
デ/すgi−全増加きせることなく、低損失で防止しょ
うとするものでおる。The current cutoff circuit consists of a self-extinguishing semiconductor element connected in series, a diode, a capacitor, and a resistor, each connected in parallel with a snubber circuit that suppresses the rate of increase in surface pressure during arc extinguishing. A low voltage clamp circuit is connected in parallel to each element. By doing this, overvoltage breakdown of the element due to unbalanced voltage distribution caused by variations in element turn-off time can be prevented.
The snubber circuit for suppressing the rate of voltage rise when an element is turned off is intended to be prevented with low loss without causing a total increase.
〔発明の実施しIJ ]
第1図はこの発明の芙施しIJt−示すもので、第4図
に示した従来例に加えて一点鎖線で示すダイオード28
.29とクランプ電源26.27からなる電圧クランプ
回路1GTQサイリスタ3および4それぞれに並列接続
して構成される。第2図は第1図においてGTOサイリ
スタ3.4がオンしていて負荷電流Ik通流している状
態から、GTOサイリスタ3.4をオフさせ友時の各部
動作波形を示す波形図で、各記号は第5図と同様である
。この図が第5図と異なる点け、先に消弧しfcGTO
サイリスタ4のアノード電圧V、が時刻t、以降は、ダ
イオード29がオンして電圧クランプ回路のクランプ電
源電圧E0となっている点で、この電圧E0はGTOサ
イリスタ3.4の耐圧より低くされており、これによっ
てこの電圧クランプ回路がない場合にGTOサイリスタ
4のアノード電圧V、が七のGTOサイリスタ4を過電
圧破壊から防止することができる。ま比、第1図の実施
例において、スナバコンデンサ12.13の容量はGT
Oサイリスタ3.4が直列数1の時必要であつ友素子消
弧時の電圧上昇率抑制用スナバ回路のスナバコンデンサ
容量と同一でるる。[Practice of the Invention] FIG. 1 shows an implementation of the present invention, in which, in addition to the conventional example shown in FIG.
.. A voltage clamp circuit 1 consisting of a clamp power supply 29 and a clamp power supply 26 and 27 is connected in parallel to GTQ thyristors 3 and 4, respectively. FIG. 2 is a waveform diagram showing the operating waveforms of each part when the GTO thyristor 3.4 is turned off and the load current Ik is flowing from the state shown in FIG. is the same as in FIG. This diagram differs from Figure 5 in that the arc is turned on and the arc is extinguished first.
Since the anode voltage V of the thyristor 4 is at time t, the diode 29 is turned on and becomes the clamp power supply voltage E0 of the voltage clamp circuit, and this voltage E0 is lower than the withstand voltage of the GTO thyristor 3.4. Therefore, in the absence of this voltage clamp circuit, the GTO thyristor 4 whose anode voltage V is 7 can be prevented from being destroyed by overvoltage. In the embodiment shown in Fig. 1, the capacitance of the snubber capacitor 12.13 is GT.
This is the same as the snubber capacitor capacity of the snubber circuit for suppressing the voltage rise rate when the companion element is turned off, which is required when the number of O thyristors 3.4 is 1 in series.
第3図は第1図の一点鎖線で示す電圧クランプ回路の別
のFJ’に示すもので、コンデンサ30゜31と抵抗3
2.33の並列回路によってクランプ電源を構成してい
る。こ\で、コンデンサ30゜31の容量は第1図のス
ナバコンデ/す12゜13の容量の数倍〜lO倍程度と
し、抵抗32゜33は第1図のチョッパ回路の出力特性
(スイッチング周波数、GTOサイリスタのオン幅)か
ら適当に選定することによって、この並列回路全低損失
のクランプ電源にすることができる。Figure 3 shows another FJ' of the voltage clamp circuit shown by the dashed line in Figure 1, with a capacitor 30°31 and a resistor 3.
A clamp power supply is constructed by 2.33 parallel circuits. Here, the capacitance of the capacitor 30°31 is several times to 10 times the capacitance of the snubber capacitor 12°13 shown in Fig. 1, and the resistor 32°33 is set to the output characteristics (switching frequency, switching frequency, etc.) of the chopper circuit shown in Fig. 1. By appropriately selecting the on-width of the GTO thyristor, it is possible to create a clamp power supply with low overall loss in this parallel circuit.
この発明によれば、直列接続された自己消弧型半導体素
子にダイオードとコンデ/すと抵抗からなる消弧時電圧
上昇率抑制用スナバ回路をそれぞれ並列接続してなる電
流しゃ断回路に対し、素子の耐圧エリも低い電圧クラン
プ回路を素子それぞれに並列接続する構成としたので、
直列後fejtされた自己消弧型半導体素子のターノオ
フ時間のバラノキに起因する電圧分担不平衡による素子
の過電圧破壊を低損失で防止することができる利点がも
たらされる。According to the present invention, for a current cutoff circuit formed by connecting in parallel a snubber circuit for suppressing the voltage rise rate at the time of arc-extinguishing consisting of a diode and a capacitor/resistance to self-extinguishing semiconductor elements connected in series, Since the configuration is such that a voltage clamp circuit with a low withstand voltage is connected in parallel to each element,
This provides the advantage that overvoltage destruction of the device due to unbalanced voltage distribution caused by fluctuations in the turn-off time of the self-extinguishing semiconductor device that has been serially connected and turned off can be prevented with low loss.
第1図はこの発明の実施例を示す回路図、第2図はその
動作を説明するための各部波形図、第3図はこの発明に
用いられる電圧クランプ回路の別の例を示す回路図、第
4図はii!流しゃ断回路の従来例を示す回路図、第5
図はその動作を説明する九めの各部波形図である。
符号説明
L・・直流電源、2・・・直流母線配線インダクタ7ス
、3〜4・・GTOサイリスタ、5〜6 ・・フリーホ
イーリングダイオード、7・・・負荷抵抗、8・・・負
荷インダクタンス% 9〜11・・スナバダイオード、
12〜16・・・スナバコンデンサ、17〜21・・ス
ナバ抵抗、22〜25・・・直流分圧抵抗、26〜27
・・・クランプ電源、28〜29・・・ダイオード。
30〜31・コンデンサ、32〜33・・抵抗。
代理人 弁理士 並 木 昭 夫
代理人 弁理士 松 崎 清
第2図FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of each part for explaining its operation, and FIG. 3 is a circuit diagram showing another example of the voltage clamp circuit used in the present invention. Figure 4 is ii! Circuit diagram showing a conventional example of a current cutoff circuit, No. 5
The figure is the ninth waveform diagram of each part explaining the operation. Symbol explanation L...DC power supply, 2...DC bus wiring inductor 7s, 3-4...GTO thyristor, 5-6...freewheeling diode, 7...load resistance, 8...load inductance %9~11...Snubber diode,
12-16... Snubber capacitor, 17-21... Snubber resistor, 22-25... DC voltage dividing resistor, 26-27
...Clamp power supply, 28-29...diode. 30~31・Capacitor, 32~33・Resistor. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 2
Claims (1)
形半導体素子の各々にダイオード、コンデンサおよび抵
抗からなり該素子消弧時の電圧上昇率を抑制するスナバ
回路を並列接続してなる高圧電流しや断回路において、 前記素子の各々に該素子の耐圧よりも低いクランプ電源
をもつ電圧クランプ回路を並列に接続してなることを特
徴とする高圧電流しや断回路。[Claims] A snubber circuit comprising a diode, a capacitor, and a resistor for each of a plurality of self-extinguishing semiconductor elements connected in series between a DC power source and a load, and suppressing the rate of voltage increase when the element is extinguished. A high voltage current source or disconnection circuit formed by connecting in parallel a high voltage current source or disconnection circuit, characterized in that each of the elements is connected in parallel with a voltage clamp circuit having a clamp power source lower than the withstand voltage of the element. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14936686A JPS636916A (en) | 1986-06-27 | 1986-06-27 | High voltage current interrupting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14936686A JPS636916A (en) | 1986-06-27 | 1986-06-27 | High voltage current interrupting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS636916A true JPS636916A (en) | 1988-01-12 |
Family
ID=15473567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14936686A Pending JPS636916A (en) | 1986-06-27 | 1986-06-27 | High voltage current interrupting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS636916A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110417285A (en) * | 2019-06-30 | 2019-11-05 | 武汉东城新能源有限公司 | A kind of novel high-frequency high voltage silicon rectifier stack circuit |
-
1986
- 1986-06-27 JP JP14936686A patent/JPS636916A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110417285A (en) * | 2019-06-30 | 2019-11-05 | 武汉东城新能源有限公司 | A kind of novel high-frequency high voltage silicon rectifier stack circuit |
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