JP6439835B1 - Multi-level power converter and control method thereof - Google Patents

Abstract

In a multilevel power conversion device, an overvoltage is applied to a switching device to prevent overvoltage breakdown, and the reliability of the device is improved. In a multi-level power conversion device that includes a DC module 1 common to each phase and a phase module 2 for each phase (two or more phases), and generates an AC output converted from a DC voltage into a plurality of voltage levels. The eleventh and thirteenth switching devices S11a, S11b, and S13a between the common connection point of the third and fourth switching devices S3 and S4a of the phase module 2 and the common connection point of the sixth and eighth switching devices S6b and S8. , S13b are connected in series. [Selection] Figure 1

Description

  The present invention relates to a voltage type high voltage multilevel power conversion device having a neutral point.

  FIG. 9 shows a three-phase multilevel power conversion device described in [Embodiment 15] of Patent Document 1. For the sake of explanation, FIG. 10 shows a multi-level power converter for one phase module of FIG. The multilevel power conversion device of FIG. 10 includes a DC module 1 and a phase module 2.

  The DC module 1 includes two first and second DC capacitors DCP and DCN, two first and second flying capacitors FCP and FCN, and eight first to eighth semiconductor devices Sa, Sb, Sc, Sd, and Se. , Sf, Sg, Sh.

  The phase module 2 includes ten first to tenth switching devices S1, S2, S3, S4a, S4b, S6a, S6b, S8, S9, S10, four first and third diodes D1a, D1b, D3a, D3b. Here, the first to eighth semiconductor devices Sa to Sh and the first to tenth switching devices S1 to S10 are exemplified as those composed of diodes connected in reverse parallel to the IGBT.

  The DC module 1 maintains the voltages of the first and second DC capacitors DCP and DCN at 2E [V] and the voltages of the first and second flying capacitors FCP and FCN at E [V]. By selecting the potential, five potentials (+ 2E, + E, 0, −E, −2E) are output. Also, let I be the current flowing through the output terminal O.

  Here, the voltage output command values of the phase module 2 are [+ 2E], [+ E], [NP], [−E], and [−2E].

  The voltage output command value [+ 2E] means that the voltage of the output terminal O with respect to the neutral point terminal N is + 2E. The same applies to [+ E], [−E], and [−2E]. The voltage output command value [NP] means that the voltage of the output terminal O with respect to the neutral point terminal N is zero.

  FIG. 11 shows an example of the switching pattern. A circle in FIG. 11 indicates a switching device in which the phase module 2 is turned on. In FIG. 11, the first to eighth semiconductor devices Sa to Sh in which the DC module 1 is turned on are not marked with a circle. The same applies to FIG.

JP 2015-47056 A Japanese Patent Laying-Open No. 2015-92790

  In general, a power converter inserts a short-circuit prevention time (dead time) Td in order to prevent overcurrent breakdown of a semiconductor device and a switching device due to a short circuit when a voltage command value transitions. A switching pattern during the dead time Td is shown in FIG.

  In the case of transition from [+ 2E] to [+ E] in FIG. 11, since the first switching device S1 and the second switching device S2 are short-circuited simultaneously, the second switching device S1 must be turned off after the first switching device S1 is turned off. It is necessary to turn on the switching device S2. Therefore, the switching pattern of the dead time is in a state where the first switching device S1 and the second switching device S2 are simultaneously turned off.

  FIG. 11 shows only the switching pattern at the steady time, but the switching pattern at the dead time is uniquely determined in this way in order to achieve short circuit prevention.

  As shown in FIG. 12, the switching pattern during the dead time Td is [DT + 2], [DT + 1], [DT-1], and [DT-2]. [DT + 2] is between [+ 2E] and [+ E], [DT + 1] is between [+ E] and [NP], [DT-1] is between [NP] and [−E], and [DT-2] is [−E] and [−E]. -E] dead time switching pattern.

  FIG. 13 shows the switching pattern [DT + 1] again. As shown in FIG. 13, a parasitic inductance exists in the current path (wiring). The parasitic inductances in FIG. 13 are L1 to L9, respectively. When the current I flowing from the output terminal O changes from [NP] to [+ E] and is negative, it is ideal that the potential of the output terminal changes from NP to + E. However, due to the parasitic inductance difference of the wiring, the diode of the first switching device S1 may be momentarily clamped, and the potential of the output terminal O may be + 2E. As a result, since the output terminal O is NP → 2E → E and the emitter terminal side of the eighth switching device S8 is −E → −E → −E, the series circuit of the sixth and eighth switching devices S6a, S6b, and S8. In some cases, the voltage applied to the both ends of E → changes from E → 3E → 2E.

  The reason why the diode of the first switching device S1 is clamped for a moment will be described below. Since the current paths are different at the time of [± 2E], [± E], and [NP] output, the wiring is also different. Therefore, the parasitic inductance differs depending on the switching pattern. Due to this difference in parasitic inductance (when L1 <L2), the diode of the first switching device S1 is clamped for a moment.

  In the multilevel power converter, the path through which the current passes varies depending on the switching pattern and the current polarity. Therefore, it is necessary to consider the parasitic inductance in each state.

  Table 1 shows the total parasitic inductance in each state. From the symmetry of the power conversion circuit, L1≈L5, L2≈L4, L6≈L9, and L7≈L8.

  Since the parasitic inductances L1 to L9 exist in the current path, and the parasitic inductance value varies depending on the current path as shown in Table 1, commutation occurs when the potential of the output terminal O changes. At that time, a surge voltage is generated, and the sixth and eighth switching devices S6a, S6b, and S8 may receive a higher voltage. As a result, the sixth and eighth switching devices S6a, S6b, and S8 may be destroyed by overvoltage, and the power conversion circuit may not operate normally.

  At this time, a voltage of instantaneous 3E is applied to both ends of the series circuit of the sixth and eighth switching devices S6a, S6b, and S8. There is no problem if the voltage is evenly shared because it is 3E for the switching device 3 series, but if the voltage is not evenly shared or if it takes time to share equally, the voltage becomes unbalanced in a transient state. As a result, an excessive voltage is applied to a specific switching device, and the switching device may be overvoltage destroyed.

  Patent Document 2 discloses a circuit that balances the voltages of two series switching devices. However, when a voltage is applied to three series switching devices, the voltages of the sixth switching devices S6a and S6b can be balanced by applying the technique of Patent Document 2, but an excessive voltage is applied to the eighth switching device S8. Cannot be avoided.

  Here, the case of [DT + 1] is given as an example, but the same phenomenon occurs in the case of [DT + 2]. The same phenomenon occurs in the case of [DT-1] and [DT-2], and the voltage balance of the third and fourth switching devices S3, S4a and S4b becomes a problem.

  This problem is an event that can occur because there is a switching device whose potential is not fixed during the dead time. In order to reduce this phenomenon, one of the solutions is to determine the potential of the terminal of the switching device as much as possible and supply a stable voltage during the dead time.

As described above, in the multilevel power conversion device, it is an issue to suppress the overvoltage breakdown due to the overvoltage being applied to the switching device and to improve the reliability of the device.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof includes a DC module common to each phase and a phase module of each phase (two or more phases), and a plurality of DC voltages are obtained from the DC voltage. A multi-level power conversion device for generating an AC output converted to a voltage level of the first DC module, wherein the DC module includes two first and second DC capacitors connected in series, and one end at a positive end of the first DC capacitor. Is connected between the first semiconductor device, the fourth semiconductor device having one end connected to the negative electrode end of the first DC capacitor, and the other end of the first semiconductor device and the other end of the fourth semiconductor device. A first flying capacitor connected to the first flying capacitor; a common connection point of the first semiconductor device and the first flying capacitor; and a common connection point of the fourth semiconductor device and the first flying capacitor. Between the second and third semiconductor devices connected in series, a fifth semiconductor device having one end connected to the positive electrode end of the second DC capacitor, and one end connected to the negative electrode end of the second DC capacitor. An eighth semiconductor device; a second flying capacitor connected between the other end of the fifth semiconductor device and the other end of the eighth semiconductor device; and a common connection of the fifth semiconductor device and the second flying capacitor And sixth and seventh semiconductor devices connected in series between a point, the eighth semiconductor device, and a common connection point of the second flying capacitor, and the phase module includes one end of the first semiconductor device. And first and second switching devices connected in series between a common connection point of the second and third semiconductor devices and a common connection of the sixth and seventh semiconductor devices And the ninth and tenth switching devices connected in series between the first semiconductor device and one end of the eighth semiconductor device, the common connection point of the first and second switching devices, and the common connection of the ninth and tenth switching devices 3rd, 4th, 6th, 8th switching device connected in series between the point, a common connection point of the 3rd, 4th switching device, and a common connection point of the 6th, 8th switching device, Eleventh and thirteenth switching devices connected in series, and connecting a common connection point of the fourth and fifth semiconductor devices and a common connection point of the eleventh and thirteenth switching devices, The common connection point of the fourth and sixth switching devices is an output terminal.

  Further, as one aspect thereof, a part or all of the fourth, sixth, eleventh and thirteenth switching devices are connected in series.

  Further, as one mode, the switching patterns of Tables 2 and 3 are provided, and the transition condition of each switching pattern is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP ] → [DT-1] ← → [−E] ← → [DT-2] ← → [-2E].

S1 to S13b: 1st to 13th switching devices Sa to Sh: 1st to 8th semiconductor devices [+ 2E], [+ E], [NP], [−E], [−2E]: Voltage output command value [DT + 2 ]: Dead time between [+ 2E] and [+ E] [DT + 1]: Dead time between [+ E] and [NP] [DT-1]: Dead time between [NP] and [−E] [DT-2] ]: [-E] and [-2E] dead time [DD]: first DC capacitor discharge, second DC capacitor discharge [CD]: first DC capacitor charge, second DC capacitor discharge [DC]: first 1 DC capacitor discharge, 2nd DC capacitor charge [CC]: 1st DC capacitor charge, 2nd DC capacitor charge
1: Semiconductor device, switching device ON
0: Semiconductor device, switching device OFF
Further, as one aspect thereof, a part or all of the first to eighth semiconductor devices and the first to thirteenth switching devices are connected in parallel to two or more.

  As another aspect, a multi-level power conversion device that includes a DC module common to each phase and a phase module of each phase (two or more phases), and generates an AC output converted from a DC voltage into a plurality of voltage levels. The DC module includes two first and second DC capacitors connected in series, a first semiconductor device having one end connected to the positive terminal of the first DC capacitor, and the first DC capacitor. A fourth semiconductor device having one end connected to a negative electrode end; a first flying capacitor connected between the other end of the first semiconductor device and the other end of the fourth semiconductor device; and the first semiconductor device; Second and third semiconductor devices connected in series between a common connection point of the first flying capacitor and a common connection point of the fourth semiconductor device and the first flying capacitor. A fifth semiconductor device having one end connected to the positive electrode end of the second DC capacitor, an eighth semiconductor device having one end connected to the negative electrode end of the second DC capacitor, and the other of the fifth semiconductor device A second flying capacitor connected between one end and the other end of the eighth semiconductor device; a common connection point of the fifth semiconductor device and the second flying capacitor; the eighth semiconductor device; and the second flying capacitor. Sixth and seventh semiconductor devices connected in series with each other, and the phase module includes a common connection point between one end of the first semiconductor device and the second and third semiconductor devices. Between the first and second switching devices connected in series with each other, the common connection point of the second and third semiconductor devices, and one end of the fourth semiconductor device. The third and fourth switching devices connected, the ninth and tenth switching devices connected in series between one end of the fifth semiconductor device and the common connection point of the sixth and seventh semiconductor devices, and the first 6, eleventh and twelfth switching devices connected in series between a common connection point of the seventh semiconductor device and one end of the eighth semiconductor device; a common connection point of the first and second switching devices; The fifth and sixth switching devices connected in series between the common connection point of the third and fourth switching devices, and the common connection point of the ninth and tenth switching devices and the common of the eleventh and twelfth switching devices The 13th and 14th switching devices connected in series between the connection points, the common connection point of the fifth and sixth switching devices, and the first 7 and 15 switching devices connected in series between the common connection point of the third and fourteenth switching devices, and the fourth and ninth common connection points of the fourth and fifth semiconductor devices. A common connection point of the switching devices is connected, and the common connection point of the seventh and fifteenth switching devices is used as an output terminal.

  Further, as one aspect thereof, a part or all of the seventh and fifteenth switching devices are connected in series.

  Further, as one mode, the switching patterns of Tables 4 and 5 are provided, and the transition condition of each switching pattern is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP ] → [DT-1] ← → [−E] ← → [DT-2] ← → [-2E].

S1 to S15b: 1st to 15th switching devices Sa to Sh: 1st to 8th semiconductor devices [+ 2E], [+ E], [NP], [−E], [−2E]: Voltage output command value [DT + 2 ]: Dead time between [+ 2E] and [+ E] [DT + 1]: Dead time between [+ E] and [NP] [DT-1]: Dead time between [NP] and [−E] [DT-2] ]: [-E] and [-2E] dead time [DD]: first DC capacitor discharge, second DC capacitor discharge [CD]: first DC capacitor charge, second DC capacitor discharge [DC]: first 1 DC capacitor discharge, 2nd DC capacitor charge [CC]: 1st DC capacitor charge, 2nd DC capacitor charge
1: Semiconductor device, switching device ON
0: Semiconductor device, switching device OFF
Moreover, as one aspect thereof, a part or all of the first to eighth semiconductor devices and the first to fifteenth switching devices are connected in parallel to two or more.

  Moreover, as one aspect thereof, the phase module is provided for three phases.

Further, as one aspect thereof, the multi-level power conversion device is connected in 2 ^x stages (an integer equal to or greater than 1) in series.

  ADVANTAGE OF THE INVENTION According to this invention, in a multilevel power converter device, it becomes possible to suppress that an overvoltage is applied to a switching device and to destroy an overvoltage, and to improve the reliability of an apparatus.

1 is a circuit diagram illustrating a multilevel power conversion device according to Embodiment 1. FIG. FIG. 3 shows a switching pattern in the first embodiment. The circuit diagram which shows the multilevel power converter device in Embodiment 2. FIG. FIG. 6 is a circuit diagram illustrating a multilevel power conversion device according to a third embodiment. FIG. 6 is a diagram illustrating a switching pattern in a third embodiment. FIG. 9 is a diagram illustrating parasitic inductances in a third embodiment. The circuit diagram which shows the multilevel power converter device in Embodiment 4. FIG. The figure which shows the multilevel power converter device connected in series multistage. The figure which shows an example of the conventional multilevel power converter device. FIG. 9 is a diagram showing one phase module of FIG. 8. The figure which shows the switching pattern of the conventional multilevel power converter device. The figure which shows the switching pattern in the dead time of the conventional multilevel power converter device. The figure which shows the diode clamp phenomenon in the dead time in the conventional multilevel power converter device.

  Hereinafter, Embodiments 1 to 4 of the multilevel power converter according to the present invention will be described in detail with reference to FIGS.

[Embodiment 1]
FIG. 1 is a circuit diagram showing a multilevel power conversion device according to the first embodiment. As shown in FIG. 1, the multilevel power conversion device according to the first embodiment includes a DC module 1 and a phase module 2. In FIG. 1, only one phase module 2 is shown, but the phase module 2 has two or more phases.

  The DC module 1 includes two first and second DC capacitors DCP and DCN, two first and second flying capacitors FCP and FCN, and eight first to eighth semiconductor devices Sa, Sb, Sc, Sd, and Se. , Sf, Sg, Sh.

  The phase module 2 includes 14 first to thirteenth switching devices S1, S2, S3, S4a, S4b, S6a, S6b, S8, S9, S10, S11a, S11b, S13a, and S13b.

  In the DC module 1, first and second DC capacitors DCP and DCN are connected in series. One end of the first semiconductor device Sa is connected to the positive end of the first DC capacitor DCP. One end of the fourth semiconductor device Sd is connected to the negative end of the first DC capacitor DCP. A first flying capacitor FCP is connected between the other end of the first semiconductor device Sa and the other end of the fourth semiconductor device Sd. Second and third semiconductor devices Sb and Sc are connected in series between a common connection point of the first semiconductor device Sa and the first flying capacitor FCP and a common connection point of the fourth semiconductor device Sd and the first flying capacitor FCP. .

  One end of the fifth semiconductor device Se is connected to the positive end of the second DC capacitor DCN. One end of the eighth semiconductor device Sh is connected to the negative end of the second DC capacitor DCN. The second flying capacitor FCN is connected between the other end of the fifth semiconductor device Se and the other end of the eighth semiconductor device Sh. Sixth and seventh semiconductor devices Sf and Sg are connected in series between the common connection point of the fifth semiconductor device Se and the second flying capacitor FCN and the common connection point of the eighth semiconductor device Sh and the second flying capacitor FCN. .

  In the phase module 2, the first and second switching devices S1, S2 are connected in series between one end of the first semiconductor device Sa and the common connection point of the second and third semiconductor devices Sb, Sc. Ninth and tenth switching devices S9 and S10 are connected in series between the common connection point of the sixth and seventh semiconductor devices Sf and Sg and one end of the eighth semiconductor device Sh.

  The third, fourth, sixth and eighth switching devices S3, S4a between the common connection point of the first and second switching devices S1, S2 and the common connection point of the ninth, tenth switching devices S9, S10 , S4b, S6a, S6b, S8 are connected in series.

  The eleventh and thirteenth switching devices S11a, S11b, S13a, and S13b are connected in series between the common connection point of the third and fourth switching devices S3 and S4a and the common connection point of the sixth and eighth switching devices S6b and S8. Is done.

  The common connection point of the fourth and fifth semiconductor devices Sd and Se and the common connection point of the eleventh and thirteenth switching devices S11b and S13a are connected. A common connection point of the fourth and sixth switching devices S4b and S6a is defined as an output terminal O.

  Here, the first to eighth semiconductor devices Sa to Sh and the first to thirteenth switching devices S1 to S13b are described as examples including diodes connected in reverse parallel to the IGBT. The DC module 1 maintains the voltages of the first and second DC capacitors DCP and DCN at 2E [V], the voltages of the first and second flying capacitors FCP and FCN at E [V], and the phase module 2 is the potential of the DC module. Is selected, five potentials (+ 2E, + E, 0, −E, −2E) are output. Also, let I be the current flowing through the output terminal O.

  The first and second diodes D1a, D1b, D3a, D3b of the conventional multilevel power converter shown in FIG. 10 are replaced with the first to thirteenth switching devices S11a, S11b, S13a, S13b. It is a difference.

  The switching patterns of the first to eighth semiconductor devices Sa to Sh and the first to thirteenth switching devices S1 to S13b that output five levels in the first embodiment are shown in Table 2 and FIG.

  As shown in Table 2, five potentials can be output from the output terminal O by a combination of these gate signals (ON / OFF signals of the switching device). Here, the voltage output command value of the phase module 2 is [+ 2E], [+ E], [NP], [−E], [−2E], and the voltage output command of the DC module 1 is [DD], [CD], Let [DC] and [CC].

  The voltage output command value [D] of the DC module 1 is the discharge command of the first flying capacitor FCP or the second flying capacitor FCN when the current I is positive, and [C] is the first flying capacitor FCP or the second flying capacitor FCN. Means a charge command.

  In Table 2, the first voltage output command value is a command for the first flying capacitor FCP, and the second is a command for the second flying capacitor FCN. For example, when the voltage output command value is [CD], the first flying capacitor FCP means a charge command, and the second flying capacitor FCN means a discharge command. In Table 2, 1 means gate on, and 0 means gate off. The first to eighth semiconductor devices Sa to Sh and the first to thirteenth switching devices S1 to S13b are turned on when the gate is turned on and turned off when the gate is turned off.

  The output voltage of the phase module 2 is approximated to a sine wave. Therefore, the condition for the transition of the voltage output command value is [+ 2E] ← → [+ E] ← → [NP] ← → [−E] ← → [−2E]. The switching patterns of the first to thirteenth switching devices S1 to S13b during the dead time are shown in Table 3 and FIG.

In Table 3, [DT + 2] is a dead time switching pattern between [+ 2E] and [+ E]. [DT + 1] is a dead time switching pattern between [+ E] and [NP]. [DT-1] is a dead time switching pattern between [NP] and [-E]. [DT-2] is a dead time switching pattern between [-E] and [-2E].

  Therefore, if the switching pattern during the dead time is included, the switching pattern transition condition is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP] ← → [DT-1] ← → [−E] ← → [DT-2] ← → [-2E].

  The feature of the first embodiment is that the eleventh and thirteenth switching devices S11a, S11b, S13a, and S13b are positively turned on to reduce the number of connection points of the switching devices whose potentials are undefined during operation. .

  As shown in Tables 2 and 3, when [+ 2E], [+ E], and [NP] are being output, the thirteenth switching devices S13a and S13b are turned on. [DT + 2] and [DT + 1] during the dead time are similarly turned on.

  Thereby, the collector terminal side of the eighth switching device S8 becomes the NP potential. In [+ 2E], [+ E], [NP], [DT + 2], and [DT + 1], since the ninth switching device S9 is on, the emitter terminal side of the eighth switching device S8 has a potential of −E. Therefore, the voltage applied between the collector and emitter terminals of the eighth switching device S8 is E.

  Consider the example given in the problem. When the current changes from [NP] to [+ E] and the current I of the output terminal O flows negatively, the potential of the output terminal O ideally changes from NP to + E. However, due to the impedance difference of the wiring, the diode of the first switching device S1 may be momentarily clamped and + 2E may be output to the output terminal O. As a result, the voltage applied between the sixth and eighth switching devices S6a, S6b, and S8 may change sequentially from E → 3E → 2E.

  However, since the voltage applied to the eighth switching device S8 is always E in [+ 2E], [+ E], [NP], [DT + 2], and [DT + 1], the voltage applied to the sixth switching devices S6a and S6b can be considered. That's fine. Since the voltage applied to the sixth switching devices S6a and S6b is 0 → 2E → E, the voltage is balanced without any problems if the control method of Patent Document 2 is used.

  The surge voltage has a correlation with the potential fluctuation amount, and since the potential fluctuation amount is reduced by one level (E) as compared with the prior art, the surge voltage is also reduced accordingly.

  When [-2E], [-E], and [NP] are output, the eleventh switching devices S11a and S11b are turned on. Similarly, [DT-2] and [DT-1] during the dead time turn on the eleventh switching devices S11a and S11b. As a result, the emitter terminal side of the third switching device S3 has an NP potential, and the collector terminal side of the third switching device S3 has a potential of + E. Therefore, the voltage applied between the collector and emitter terminals of the third switching device S3 is E.

  For the same reason as described above, there is no problem and the voltages of the third and fourth switching devices S3, S4a and S4b are balanced and the surge voltage is also reduced.

  In FIG. 1 of the first embodiment, the fourth switching devices S4a and S4b are connected in series due to the withstand voltage of the switching devices. The same applies to the sixth switching devices S6a and S6b, the eleventh switching devices S11a and S11b, and the thirteenth switching devices S13a and S13b. If a switching device having a high withstand voltage is used, two switching devices connected in series may be combined into one.

  As described above, according to the first embodiment, since the voltage applied to the third and eighth switching devices S3 and S8 is stabilized, the third and eighth switching devices S3 and S8 are transient during the dead time. Unaffected by potential fluctuations.

  In addition, since the third and eighth switching devices S3 and S8 are not affected by the transient potential fluctuation, the destruction of the third and eighth switching devices S3 and S8 due to the overvoltage is suppressed. Therefore, the reliability of the power conversion device is improved.

  Further, even if the diode of the first switching device S1 or the tenth switching device S10 is clamped and an unintended voltage is applied to the fourth switching devices S4a, S4b or the sixth switching devices S6a, S6b, it is more than the conventional power converter. Since the voltage is small, the amount of surge voltage due to potential fluctuation can be suppressed.

  Furthermore, since the surge voltage is small, the switching loss of the fourth switching device S4a, S4b or the sixth switching device S6a, S6b is small and the temperature rise of the switching device is suppressed, so that the reliability and life of the switching device are improved. . Therefore, it is possible to improve the reliability of the power conversion device.

[Embodiment 2]
FIG. 3 is a circuit diagram illustrating the multilevel power conversion device according to the second embodiment. As shown in FIG. 3, the multilevel power conversion device according to the second embodiment is obtained by extending the phase module 2 according to the first embodiment to three phases. The power conversion device according to the second embodiment shown in FIG. 3 includes one DC module 1 and three phase modules 2a, 2b, and 2c.

  The five potentials supplied from the DC module 1 are configured to be connected in parallel with the phase modules 2a, 2b, and 2c.

  As described above, according to the second embodiment, the same operational effects as those of the first embodiment can be obtained.

[Embodiment 3]
FIG. 4 is a circuit diagram showing a multilevel power conversion device according to the third embodiment. As shown in FIG. 4, the multilevel power conversion device according to the third embodiment includes a DC module 1 and a phase module 2. In FIG. 4, only one phase module 2 is shown, but the phase module 2 has two or more phases.

  The DC module 1 includes two first and second DC capacitors DCP and DCN, two first and second flying capacitors FCP and FCN, and eight first to eighth semiconductor devices Sa, Sb, Sc, Sd, and Se. , Sf, Sg, Sh.

  The phase module 2 has 16 first to fifteenth switching devices S1, S2, S3, S4, S5, S6, S7a, S7b, S9, S10, S11, S12, S13, S14, S15a, and S15b.

  Since the configuration of the DC module 1 is the same as that of the first embodiment, description thereof is omitted here.

  In the phase module 2, the first and second switching devices S1, S2 are connected in series between one end of the first semiconductor device Sa and the common connection point of the second and third semiconductor devices Sb, Sc. The third and fourth switching devices S3 and S4 are connected in series between the common connection point of the second and third semiconductor devices Sb and Sc and one end of the fourth semiconductor device Sd.

  Ninth and tenth switching devices S9 and S10 are connected in series between one end of the fifth semiconductor device Se and the common connection point of the sixth and seventh semiconductor devices Sf and Sg. The eleventh and twelfth switching devices S11 and S12 are connected in series between the common connection point of the sixth and seventh semiconductor devices Sf and Sg and one end of the eighth semiconductor device Sh.

  The fifth and sixth switching devices S5 and S6 are connected in series between the common connection point of the first and second switching devices S1 and S2 and the common connection point of the third and fourth switching devices S3 and S4. The thirteenth and fourteenth switching devices S13 and S14 are connected in series between the common connection point of the ninth and tenth switching devices S9 and S10 and the common connection point of the eleventh and twelfth switching devices S11 and S12.

  Seventh and fifteenth switching devices S7a, S7b, S15a and S15b are connected in series between the common connection point of the fifth and sixth switching devices S5 and S6 and the common connection point of the thirteenth and fourteenth switching devices S13 and S14. Is done.

  The common connection point of the fourth and fifth semiconductor devices Sd and Se and the common connection point of the fourth and ninth switching devices S4 and S9 are connected. A common connection point of the seventh and fifteenth switching devices S7b and S15a is defined as an output terminal O.

  Here, the first to eighth semiconductor devices Sa to Sh and the first to fifteenth switching devices S1 to S15b are exemplified as those composed of diodes connected in reverse parallel to the IGBT. The DC module 1 maintains the voltages of the first and second DC capacitors DCP and DCN at 2E [V] and the voltages of the first and second flying capacitors FCP and FCN at E [V]. By selecting the potential, five potentials (+ 2E, + E, 0, −E, −2E) are output. Also, let I be the current flowing through the output terminal O.

  This configuration includes a first DC capacitor DCP, a first flying capacitor FCP, first to fourth semiconductor devices Sa to Sd, first to sixth switching devices S1 to S6, and a second DC capacitor DCN. , The second flying capacitor FCN, the fifth to eighth semiconductor devices Se to Sh, and the ninth to fourteenth switching devices S9 to S14 are geometrically symmetrical about the terminal N and the output terminal O, respectively. Circuit.

  In the multilevel power conversion device according to the third embodiment, the first, second diodes D1a, D1b, D3a, D3b of the multilevel power conversion device shown in FIG. 10 are replaced with the sixth, fourth, ninth, and thirteenth switching devices S6. , S4, S9, and S13, and third and tenth switching devices S3 and S10 are added.

  The switching patterns of the first to eighth switching devices Sa to Sh and the first to fifteenth switching devices S1 to S15b that output five levels of the multilevel power conversion device according to the third embodiment are shown in Table 4 and FIG.

  As shown in Table 4, a combination of these gate signals (switching device ON / OFF signals) allows five potentials to be output. Here, the voltage output command value of the phase module 2 is [+ 2E], [+ E], [NP], [−E], [−2E], and the voltage output command value of the DC module 1 is [DD], [CD]. , [DC], [CC].

  Furthermore, the output voltage of the phase module is approximated to a sine wave. Therefore, the transition condition of the voltage output command is [+ 2E] ← → [+ E] ← → [NP] ← → [−E] ← → [−2E]. Switching patterns during the dead time Td are shown in Table 5 and FIG.

  In Table 5, [DT + 2] is a dead time switching pattern between [+ 2E] and [+ E]. [DT + 1] is a dead time switching pattern between [+ E] and [NP]. [DT-1] is a dead time switching pattern between [NP] and [-E]. [DT-2] is a dead time switching pattern between [-E] and [-2E].

  Therefore, if the switching pattern during the dead time is included, the switching pattern transition condition is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP] ← → [DT-1] ← → [−E] ← → [DT-2] ← → [-2E].

  The features of the third embodiment are roughly divided into three. The first is that, as in the first embodiment, the number of connection points of switching devices whose potentials are undefined during operation is reduced by the combination of the switching devices. In addition, since there are locations where switching devices that are conductive at the time of [+ E] and [−E] output are in parallel, the conduction loss of this portion can be reduced.

  The second is that the voltage applied to each switching device is always limited to E during the gate-off period, as in the first embodiment. However, there are places where a voltage of 2E is applied by two switching devices connected in series during the gate-off period. The location is between the seventh switching devices S7a and S7b or between the fifteenth switching devices S15a and S15b.

  As an example, the voltages of the fourteenth and fifteenth switching devices S14, S15a, and S15b will be described. In the state of [+ 2E], the voltage applied to the fourteenth switching device S14 is always E and the voltage applied to the fifteenth switching devices S15a and S15b is 2E by the operation of the switching pattern in Table 4. In these places, if the technique of patent document 2 is used, the voltage of the two switching devices connected in series can be balanced without any problem. In addition, you may use the method of balancing the voltage of two switching devices connected in series other than patent document 2. FIG.

  Third, since the circuit of the third embodiment has symmetry in geometry, there are many common paths in the current path between [+ 2E] and [+ E]. Therefore, the difference in parasitic inductance due to each wiring is small. Furthermore, there are many common lines in the current path between [+ E] and [NP], and the difference in parasitic inductance due to each wiring is small.

  FIG. 6 shows the parasitic inductance of the multilevel power conversion device according to the third embodiment. Table 6 shows the total parasitic inductance in the third embodiment.

  Due to the symmetry of the power conversion circuit, the parasitic inductances are L1≈L5, L2≈L4, L6≈L7≈L8≈L9, and L10≈L11. L6 // L7 in Table 6 indicates an inductance value when the parasitic inductance L6 and the parasitic inductance L7 are connected in parallel. The same applies to the other //.

  The switching pattern transitions to [+ 2E], [+ E], [NP], [−E], and [−2E]. However, since there are many common paths in the current path in the switching pattern between the transitions, There is a common parasitic inductance. Thereby, the change of the total parasitic inductance at the time of switching pattern transition becomes small. For example, when the current changes from [NP] to [+ E] and the current flows in a negative polarity, since the parasitic inductances L7 and L10 are common parasitic inductances, the change in the total parasitic inductance is small.

  In the prior art (FIGS. 10 to 13) and FIG. 1 of the first embodiment, there is a case where there is no common current path in the switching pattern between the transitions, so the total parasitic inductance value changes suddenly at the switching pattern transition. There is a case. For example, in the circuit of FIG. 13, when [NP] changes to [+ E] and the current flows in a negative polarity, the total parasitic inductance changes from L3 + L8 to L2 + L6 as shown in Table 1.

  Further, the same conducting member is often used for adjacent current paths such as L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, and L11 in FIG. When the conducting member is the same, the parasitic inductance of each member is theoretically equal. Therefore, as in the third embodiment, when the circuit configuration has geometric symmetry and the switching pattern changes little by little, the difference in the total parasitic inductance in the switching pattern between the transitions also becomes small. In particular, when a 2 in 1 module is used for the switching device (IGBT), the effect becomes remarkable.

  In the third embodiment, the amount of surge voltage generated due to the difference in parasitic inductance during commutation that has occurred in the prior art can be suppressed in principle.

  Consider the example given in the prior art. In the third embodiment, when the current changes from [NP] to [+ E] and the current flows in the negative polarity, the potential of the output terminal O changes from NP to + E. This is because the difference in parasitic inductance is small compared to the prior art, and as can be seen from Table 6, the total parasitic inductance values of [+ E] and [DT + 1] are small compared to the total parasitic inductance value of [+ 2E]. Therefore, the potential of the output terminal O does not become + 2E.

  This is because the current paths of [+ E] and [DT + 1] are partially parallel (L6 // L7), and the total parasitic inductance value of [+ E] and [DT + 1] is smaller than the total parasitic inductance value of [+ 2E]. This is because the phenomenon in which the diode of the first switching device S1 is momentarily clamped does not occur.

  Further, in [+ 2E], [+ E], [NP], [DT + 2], and [DT + 1], since the eleventh switching device S11 is on, the potential of the emitter terminal of the fourteenth switching device S14 is −E.

  Therefore, the voltage applied between the series circuits of the fifteenth and fourteenth switching devices S15a, S15b and S14 in FIG. 4 (the voltage applied between the emitter terminal of the fourteenth switching device S14 and the collector terminal of the fifteenth switching device S15a) is The maximum is 2E, and the surge voltage is also reduced. The surge voltage generated during gate on / off switching has a correlation with the amount of potential fluctuation, and since the amount of potential fluctuation is reduced, the surge voltage is also reduced accordingly.

  In FIG. 4 of the third embodiment, the seventh switching devices S7a and S7b are connected in series because of the withstand voltage of the switching devices. The same applies to the fifteenth switching devices S15a and S15b. If a switching device having a high withstand voltage is used, these two switching devices connected in series may be combined into one.

  As described above, according to the third embodiment, since the voltage applied to each switching device is stabilized, it is not affected by the transient potential fluctuation during the dead time Td.

  In addition, since it is not affected by transient potential fluctuations, the probability of occurrence of breakdown or failure due to overvoltage is reduced. Therefore, the reliability of the power conversion device is improved.

  Even if the diode is clamped and an unintended voltage is applied to the seventh switching devices S7a and S7b or the fifteenth switching devices S15a and S15b, the voltage is smaller than that of the prior art, so the amount of surge voltage due to potential fluctuation is small. . Thereby, since a switching device becomes difficult to destroy overvoltage, the reliability of a power converter device improves.

  Furthermore, since the amount of surge voltage is small, the switching loss of the seventh switching device S7a, S7b or the fifteenth switching device S15a, S15b is small, and the temperature rise of each switching device is suppressed. improves. Therefore, the reliability of the power conversion device is improved.

  In addition, the following effects can be obtained as compared with the first embodiment. Since the circuit of Embodiment 3 has geometric symmetry, the difference in parasitic inductance between the switching patterns is small. Furthermore, since the difference in parasitic inductance is small in each switching pattern, surge voltage due to commutation can be further suppressed. Thereby, since it becomes difficult for a switching device to destroy overvoltage more, the reliability of a power converter device improves.

  Further, since the switching devices on the conduction path are arranged in parallel at the time of [+ E] and [−E] output, conduction loss can be reduced. Therefore, the second, third, fifth, sixth, tenth, eleventh, thirteenth, and fourteenth switching devices S2, S3, S5, S6, S10, S11, S13, and S14 are configured in parallel. Therefore, the reliability of the power conversion device is improved.

[Embodiment 4]
FIG. 7 is a circuit diagram showing a multilevel power conversion device according to the fourth embodiment. As shown in FIG. 7, the multilevel power conversion device according to the fourth embodiment is obtained by extending the phase module 2 according to the third embodiment to three phases.

  The multilevel power conversion device according to the fourth embodiment includes one DC module 1 and three phase modules 2a, 2b, and 2c. The five potentials supplied from the DC module 1 are configured to be connected in parallel with the phase modules 2a, 2b, and 2c.

  As described above, according to the fourth embodiment, the same operational effects as those of the third embodiment are obtained.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  For example, some or all of the semiconductor devices and switching devices in the first to fourth embodiments may be connected in parallel to two or more.

It is also possible to connect the multi-level power conversion apparatus of Embodiment 1-4 in 2 ^x stage series multistage (x = 1 or more integer). FIG. 8A shows a configuration in which two stages of multi-level power converters are connected in series, and FIG. 8B shows a configuration in which four stages are connected in series.

The configuration of a 2 ^× stage serial multistage will be described. As an example, when the configuration of FIG. 1 is applied to the multilevel power conversion devices 3a and 3b of FIG. 8A, the negative electrode of the DC capacitor DCN on the multilevel power conversion device 3a side and the DC of the multilevel power conversion device 3b side are shown. Connect the positive electrode of the capacitor DCP. The same connection is made in FIG.
Further, as shown in FIG. 8A, in the case of two-stage series connection, one end of the switching device S is connected to the output terminals of the adjacent multilevel power converters 3a and 3b. The other ends of the switching device S are connected to each other, and the common connection point is used as an output terminal.

  As shown in FIG. 8B, in the case of four-stage series connection, the output terminals of the adjacent multilevel power converters 3a, 3b and 3c, 3d are connected via the switching device S. Further, the common connection points are connected to each other through the switching device S, and the connection point is set as an output terminal.

  As a result, it is possible to output a voltage of 9 levels when connected in 2-stage multi-stage, 17 levels when connected in 4-stage multi-stage, and 33 levels when connected in 8-stage multi-stage.

DESCRIPTION OF SYMBOLS 1 ... DC module 2 ... Phase module Sa-Sh ... Semiconductor device S1-S15 ... Switching device L1-L11 ... Parasitic inductance 3a-3d ... Multi-level power converter

Claims (10)

A multi-level power converter that includes a DC module common to each phase and a phase module of each phase (two or more phases), and generates an AC output converted from a DC voltage into a plurality of voltage levels,
The DC module is
Two first and second DC capacitors connected in series;
A first semiconductor device having one end connected to the positive electrode end of the first DC capacitor;
A fourth semiconductor device having one end connected to the negative electrode end of the first DC capacitor;
A first flying capacitor connected between the other end of the first semiconductor device and the other end of the fourth semiconductor device;
Second and third semiconductor devices connected in series between a common connection point of the first semiconductor device and the first flying capacitor and a common connection point of the fourth semiconductor device and the first flying capacitor;
A fifth semiconductor device having one end connected to the positive electrode end of the second DC capacitor;
An eighth semiconductor device having one end connected to the negative electrode end of the second DC capacitor;
A second flying capacitor connected between the other end of the fifth semiconductor device and the other end of the eighth semiconductor device;
And sixth and seventh semiconductor devices connected in series between the common connection point of the fifth semiconductor device and the second flying capacitor and the common connection point of the eighth semiconductor device and the second flying capacitor. And
The phase module is
First and second switching devices connected in series between one end of the first semiconductor device and a common connection point of the second and third semiconductor devices;
Ninth and tenth switching devices connected in series between a common connection point of the sixth and seventh semiconductor devices and one end of the eighth semiconductor device;
Third, fourth, sixth and eighth switching devices connected in series between the common connection point of the first and second switching devices and the common connection point of the ninth and tenth switching devices;
Eleventh and thirteenth switching devices connected in series between the common connection point of the third and fourth switching devices and the common connection point of the sixth and eighth switching devices,
Connecting the common connection point of the fourth and fifth semiconductor devices and the common connection point of the eleventh and thirteenth switching devices, and using the common connection point of the fourth and sixth switching devices as an output terminal;
It has the switching pattern of Table 2 and Table 3,
The transition condition of each switching pattern is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP] ← → [DT-1] ← → [−E] ← → [DT− 2] ← → [−2E] Multi-level power conversion device

S1 to S13b: 1st to 13th switching devices Sa to Sh: 1st to 8th semiconductor devices [+ 2E], [+ E], [NP], [−E], [−2E]: Voltage output command value [DT + 2 ]: Dead time between [+ 2E] and [+ E] [DT + 1]: Dead time between [+ E] and [NP] [DT-1]: Dead time between [NP] and [−E] [DT-2] ]: [-E] and [-2E] dead time [DD]: first DC capacitor discharge, second DC capacitor discharge [CD]: first DC capacitor charge, second DC capacitor discharge [DC]: first 1 DC capacitor discharge, 2nd DC capacitor charge [CC]: 1st DC capacitor charge, 2nd DC capacitor charge
1: Semiconductor device, switching device ON
0: Semiconductor device, switching device OFF The multilevel power conversion apparatus according to claim 1, wherein a part or all of the first to eighth semiconductor devices and the first to thirteenth switching devices are connected in parallel to two or more. A multi-level power converter that includes a DC module common to each phase and a phase module of each phase (two or more phases), and generates an AC output converted from a DC voltage into a plurality of voltage levels,
The DC module is
Two first and second DC capacitors connected in series;
A first semiconductor device having one end connected to the positive electrode end of the first DC capacitor;
A fourth semiconductor device having one end connected to the negative electrode end of the first DC capacitor;
A first flying capacitor connected between the other end of the first semiconductor device and the other end of the fourth semiconductor device;
Second and third semiconductor devices connected in series between a common connection point of the first semiconductor device and the first flying capacitor and a common connection point of the fourth semiconductor device and the first flying capacitor;
A fifth semiconductor device having one end connected to the positive electrode end of the second DC capacitor;
An eighth semiconductor device having one end connected to the negative electrode end of the second DC capacitor;
A second flying capacitor connected between the other end of the fifth semiconductor device and the other end of the eighth semiconductor device;
And sixth and seventh semiconductor devices connected in series between the common connection point of the fifth semiconductor device and the second flying capacitor and the common connection point of the eighth semiconductor device and the second flying capacitor. And
The phase module is
First and second switching devices connected in series between one end of the first semiconductor device and a common connection point of the second and third semiconductor devices;
Third and fourth switching devices connected in series between a common connection point of the second and third semiconductor devices and one end of the fourth semiconductor device;
Ninth and tenth switching devices connected in series between one end of the fifth semiconductor device and a common connection point of the sixth and seventh semiconductor devices; a common connection point of the sixth and seventh semiconductor devices; Eleventh and twelfth switching devices connected in series with one end of the eighth semiconductor device;
Fifth and sixth switching devices connected in series between a common connection point of the first and second switching devices and a common connection point of the third and fourth switching devices;
Thirteenth and fourteenth switching devices connected in series between a common connection point of the ninth and tenth switching devices and a common connection point of the eleventh and twelfth switching devices;
Seventh and fifteenth switching devices connected in series between the common connection point of the fifth and sixth switching devices and the common connection point of the thirteenth and fourteenth switching devices;
The common connection point of the fourth and fifth semiconductor devices is connected to the common connection point of the fourth and ninth switching devices, and the common connection point of the seventh and fifteenth switching devices is used as an output terminal. Multi-level power converter. 4. The multilevel power converter according to claim 3 , wherein two or more of the seventh and fifteenth switching devices are connected in series. It has the switching pattern of Table 4 and Table 5,
The transition condition of each switching pattern is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP] ← → [DT-1] ← → [−E] ← → [DT− 2] ← → [-2E], The multi-level power converter according to claim 3 or 4,

S1 to S15b: 1st to 15th switching devices Sa to Sh: 1st to 8th semiconductor devices [+ 2E], [+ E], [NP], [−E], [−2E]: Voltage output command value [DT + 2 ]: Dead time between [+ 2E] and [+ E] [DT + 1]: Dead time between [+ E] and [NP] [DT-1]: Dead time between [NP] and [−E] [DT-2] ]: [-E] and [-2E] dead time [DD]: first DC capacitor discharge, second DC capacitor discharge [CD]: first DC capacitor charge, second DC capacitor discharge [DC]: first 1 DC capacitor discharge, 2nd DC capacitor charge [CC]: 1st DC capacitor charge, 2nd DC capacitor charge
1: Semiconductor device, switching device ON
0: Semiconductor device, switching device OFF 6. The multilevel power conversion according to claim 3, wherein a part or all of the first to eighth semiconductor devices and the first to fifteenth switching devices are connected in parallel to two or more. apparatus. The multi-level power converter according to claim 1, wherein the phase modules are provided for three phases. The multilevel power conversion device according to any one of claims 1 to 7, wherein the multilevel power conversion device is connected in 2 ^x stages (x = an integer of 1 or more) in series. A DC module common to each phase, and a phase module for each phase (two or more phases),
The DC module is
Two first and second DC capacitors connected in series;
A first semiconductor device having one end connected to the positive electrode end of the first DC capacitor;
A fourth semiconductor device having one end connected to the negative electrode end of the first DC capacitor;
A first flying capacitor connected between the other end of the first semiconductor device and the other end of the fourth semiconductor device;
Second and third semiconductor devices connected in series between a common connection point of the first semiconductor device and the first flying capacitor and a common connection point of the fourth semiconductor device and the first flying capacitor;
A fifth semiconductor device having one end connected to the positive electrode end of the second DC capacitor;
An eighth semiconductor device having one end connected to the negative electrode end of the second DC capacitor;
A second flying capacitor connected between the other end of the fifth semiconductor device and the other end of the eighth semiconductor device;
And sixth and seventh semiconductor devices connected in series between the common connection point of the fifth semiconductor device and the second flying capacitor and the common connection point of the eighth semiconductor device and the second flying capacitor. And
The phase module is
First and second switching devices connected in series between one end of the first semiconductor device and a common connection point of the second and third semiconductor devices;
Ninth and tenth switching devices connected in series between a common connection point of the sixth and seventh semiconductor devices and one end of the eighth semiconductor device;
Third, fourth, sixth and eighth switching devices connected in series between the common connection point of the first and second switching devices and the common connection point of the ninth and tenth switching devices;
Eleventh and thirteenth switching devices connected in series between the common connection point of the third and fourth switching devices and the common connection point of the sixth and eighth switching devices,
The common connection point of the fourth and fifth semiconductor devices and the common connection point of the eleventh and thirteenth switching devices are connected, and the common connection point of the fourth and sixth switching devices is used as an output terminal. A control method for a multi-level power converter that generates an AC output converted into a plurality of voltage levels,
It has the switching pattern of Table 2 and Table 3,
The transition condition of each switching pattern is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP] ← → [DT-1] ← → [−E] ← → [DT− 2] ← → [−2E]. A control method for a multilevel power conversion device.

S1 to S13b: 1st to 13th switching devices Sa to Sh: 1st to 8th semiconductor devices [+ 2E], [+ E], [NP], [−E], [−2E]: Voltage output command value [DT + 2 ]: Dead time between [+ 2E] and [+ E] [DT + 1]: Dead time between [+ E] and [NP] [DT-1]: Dead time between [NP] and [−E] [DT-2] ]: [-E] and [-2E] dead time [DD]: first DC capacitor discharge, second DC capacitor discharge [CD]: first DC capacitor charge, second DC capacitor discharge [DC]: first 1 DC capacitor discharge, 2nd DC capacitor charge [CC]: 1st DC capacitor charge, 2nd DC capacitor charge
1: Semiconductor device, switching device ON
0: Semiconductor device, switching device OFF A control method for controlling the multilevel power conversion device according to claim 3 ,
It has the switching pattern of Table 4 and Table 5,
The transition condition of each switching pattern is [+ 2E] ← → [DT + 2] ← → [+ E] ← → [DT + 1] ← → [NP] ← → [DT-1] ← → [−E] ← → [DT− 2] ← → [−2E]. A control method for a multilevel power conversion device.

S1 to S15b: 1st to 15th switching devices Sa to Sh: 1st to 8th semiconductor devices [+ 2E], [+ E], [NP], [−E], [−2E]: Voltage output command value [DT + 2 ]: Dead time between [+ 2E] and [+ E] [DT + 1]: Dead time between [+ E] and [NP] [DT-1]: Dead time between [NP] and [−E] [DT-2] ]: [-E] and [-2E] dead time [DD]: first DC capacitor discharge, second DC capacitor discharge [CD]: first DC capacitor charge, second DC capacitor discharge [DC]: first 1 DC capacitor discharge, 2nd DC capacitor charge [CC]: 1st DC capacitor charge, 2nd DC capacitor charge
1: Semiconductor device, switching device ON
0: Semiconductor device, switching device OFF

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