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JPS6361776B2 - - Google Patents

Info

Publication number
JPS6361776B2
JPS6361776B2 JP57140962A JP14096282A JPS6361776B2 JP S6361776 B2 JPS6361776 B2 JP S6361776B2 JP 57140962 A JP57140962 A JP 57140962A JP 14096282 A JP14096282 A JP 14096282A JP S6361776 B2 JPS6361776 B2 JP S6361776B2
Authority
JP
Japan
Prior art keywords
circuit
bonding
signal
wire
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57140962A
Other languages
Japanese (ja)
Other versions
JPS5931036A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP57140962A priority Critical patent/JPS5931036A/en
Publication of JPS5931036A publication Critical patent/JPS5931036A/en
Publication of JPS6361776B2 publication Critical patent/JPS6361776B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/78268Discharge electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8503Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明はワイヤボンデイング停止回路、特にス
パーク放電を利用した自動ワイヤボンデイング装
置に関するワイヤボンデイング停止回路に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wire bonding stop circuit, and more particularly to a wire bonding stop circuit for an automatic wire bonding apparatus using spark discharge.

半導体集積回路(IC)部品の製造において、
ICチツプのボンデイングパツド部とリードフレ
ームのピン端子間を金属リード線で結線するボン
デイング作業の高速化はIC部品の大量生産の為
極めて重要な課題である。
In the manufacturing of semiconductor integrated circuit (IC) parts,
Speeding up the bonding process, in which metal lead wires are used to connect the bonding pads of IC chips and pin terminals of lead frames, is an extremely important issue for the mass production of IC components.

この問題を解決する為、近年自動ワイヤボンデ
イング装置がIC製造ラインに大量に採用されて
いる。このボンデイング工程において金属リード
線、例えば金線の先端を熔融させて直径80〜
110μmの金ボールを形成することが不可欠であ
り、この為金線とスパーク電極間の電気的なスパ
ーク放電をした金ボール形成方法が広く実施され
ている。この金ボールはICチツプのボンデイン
グパツド部との熱圧着の為の表面積を大きくする
事及びワイヤボンデイング時にパツド部への機械
的な衝撃によりパツド部にクラツクが発生するこ
とを防止する緩衝物として働く。
To solve this problem, automatic wire bonding equipment has recently been widely adopted in IC manufacturing lines. In this bonding process, the tip of a metal lead wire, such as a gold wire, is melted and
It is essential to form a 110 μm gold ball, and for this reason, a method of forming a gold ball using an electrical spark discharge between a gold wire and a spark electrode is widely practiced. This gold ball is used to increase the surface area for thermocompression bonding with the bonding pad of the IC chip, and as a buffer to prevent cracks from occurring in the pad due to mechanical impact during wire bonding. work.

自動ワイヤボンデイング装置の1ボンデイング
サイクルは下記の第1〜第3の主要工程からな
る。
One bonding cycle of the automatic wire bonding apparatus consists of the following first to third main steps.

(1) キヤピラリの先端から金線を所定の長さだけ
送出する。(金線送出工程) (2) スパーク電極を金線の先端に配置した後、ス
パーク放電により金線の先端を溶かし所定径の
金ボールを形成する。(金ボール形成工程) (3) キヤピラリをICチツプのパツド部上に配置
した後、パツド部と金ボール部を熱圧着する。
(熱圧着工程) 従来のスパーク放電を利用した自動ワイヤボン
デイング装置は0.2〜0.4秒/ボンデイングサイク
ル程度のボンデイング速度でボンデイング作業を
行つているが、キヤピラリからの金線の送出量が
設定値以上に長くなりすぎスパーク電極と金線が
短絡し金線の先端に金ボールが形成されない事が
しばしば生じた。
(1) Send out a specified length of gold wire from the tip of the capillary. (Gold wire delivery process) (2) After placing the spark electrode at the tip of the gold wire, the tip of the gold wire is melted by spark discharge to form a gold ball of a predetermined diameter. (Gold ball forming process) (3) After placing the capillary on the pad part of the IC chip, the pad part and the gold ball part are bonded by thermocompression.
(Thermocompression bonding process) Conventional automatic wire bonding equipment using spark discharge performs bonding work at a bonding speed of about 0.2 to 0.4 seconds/bonding cycle, but the amount of gold wire delivered from the capillary exceeds the set value. When the length was too long, the spark electrode and the gold wire were short-circuited, and a gold ball was often not formed at the tip of the gold wire.

従来のボンデイング装置では金線とスパーク電
極の短絡状態を検出する機能を有しない為、金線
の先端に所定径の金ボールが形成されない状態で
熱圧着工程を開始しキヤピラリの先端が直接パツ
ド部を“空打ち”するので、パツド部にクラツク
を生じさせながら連続してボンデイング不良の
IC部品を製造する問題があつた。
Conventional bonding equipment does not have a function to detect short-circuit conditions between the gold wire and the spark electrode, so the thermocompression bonding process is started before a gold ball of a specified diameter is formed at the tip of the gold wire, and the tip of the capillary is directly attached to the pad. Since the pad is "dry-struck", bonding defects are continuously detected while causing cracks in the pad.
There was a problem in manufacturing IC parts.

本発明はこれらの欠点を解決する為、金線がス
パーク電極に接触すると熱圧着工程を停止させる
ワイヤボンデイング停止回路に提供するものであ
る。
The present invention solves these drawbacks by providing a wire bonding stop circuit that stops the thermocompression bonding process when the gold wire comes into contact with the spark electrode.

以下第1〜第3図に示す本発明の実施例に従つ
て詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention shown in FIGS. 1 to 3 will be described in detail below.

本発明の実施例によるワイヤボンデイング停止
回路は放電電流検出回路1と、遅延回路2と、信
号比較回路3と、禁止信号発生回路4から構成さ
れる。放電電流検出回路1はスパーク放電回路5
に流れる電流の有無を検出しパルス信号に変換す
る回路である。放電電流回路5は高圧直流電源
(例えば550V)6、スイツチ7、抵抗8、ワイヤ
クランプ手段9、金線10、スパーク電極11か
ら形成される。
The wire bonding stop circuit according to the embodiment of the present invention includes a discharge current detection circuit 1, a delay circuit 2, a signal comparison circuit 3, and an inhibition signal generation circuit 4. The discharge current detection circuit 1 is a spark discharge circuit 5
This circuit detects the presence or absence of current flowing through the circuit and converts it into a pulse signal. The discharge current circuit 5 is formed of a high voltage DC power source (for example, 550V) 6, a switch 7, a resistor 8, a wire clamping means 9, a gold wire 10, and a spark electrode 11.

金線10はワイヤリール12から垂直(Z軸方
向)に送出されキヤピラリ13の針穴に案内され
る。キヤピラリ13はボンデイングアーム14と
一体となり駆動回路15の出力信号(K)によりZ軸
方向に可動される。ワイヤクランプ手段9は駆動
回路16により時間的に金線10をクランプし、
又放電回路5のスイツチとして作用する。
The gold wire 10 is fed out vertically (in the Z-axis direction) from the wire reel 12 and guided into the needle hole of the capillary 13. The capillary 13 is integrated with the bonding arm 14 and is moved in the Z-axis direction by the output signal (K) of the drive circuit 15. The wire clamping means 9 temporally clamps the gold wire 10 by a drive circuit 16,
It also acts as a switch for the discharge circuit 5.

スパーク電極11は駆動回路17によりZ軸を
中心として回転しキヤピラリ13の直下に配置さ
れる。このキヤピラリ13の先端とスパーク電極
11間のキヨリl1は正確に設定値(この実施例で
は1.2mm)に決められる。
The spark electrode 11 is rotated around the Z axis by a drive circuit 17 and is placed directly below the capillary 13 . The offset l 1 between the tip of the capillary 13 and the spark electrode 11 is accurately determined to a set value (1.2 mm in this embodiment).

放電電流検出回路1は例えばホトカプラ回路1
8と波形整形回路19から構成される。ホトカプ
ラ回路18は発光素子20と受光素子21を含
み、抵抗8間に降下した電圧により発光素子20
が発光し受光素子21に入射される。波形整形回
路19は例えばトランジスタ22及びインバータ
23を含み受光素子21から入力された信号を増
巾及び波形整形する。
The discharge current detection circuit 1 is, for example, a photocoupler circuit 1.
8 and a waveform shaping circuit 19. The photocoupler circuit 18 includes a light emitting element 20 and a light receiving element 21, and the voltage dropped across the resistor 8 causes the light emitting element 20 to
emits light and enters the light receiving element 21. The waveform shaping circuit 19 includes, for example, a transistor 22 and an inverter 23, and amplifies and shapes the waveform of the signal input from the light receiving element 21.

遅延回路2は各々時定数回路26,27を有す
る単安定マルチバイブレータ回路24,25から
形成され、インバータ23から出力された信号に
よりこの出力信号のパルス巾に相当する時間T1
を経過後、パルス信号を出力する。時定数回路2
6はインバータ23から出力される出力信号のパ
ルス巾以上の時定数T2を有する。
The delay circuit 2 is formed from monostable multivibrator circuits 24 and 25 having time constant circuits 26 and 27, respectively, and the signal output from the inverter 23 causes a time T 1 corresponding to the pulse width of this output signal.
After , a pulse signal is output. Time constant circuit 2
6 has a time constant T 2 that is greater than the pulse width of the output signal output from the inverter 23 .

信号比較回路3はインバータ28とAND論理
回路29から構成され、インバータ23から所定
のパルス巾を有するパルス信号が出力されるとパ
ルス信号を出力する。
The signal comparison circuit 3 is composed of an inverter 28 and an AND logic circuit 29, and outputs a pulse signal when the inverter 23 outputs a pulse signal having a predetermined pulse width.

禁止信号発生回路4はJKフリツプフロツプ3
0と、ゲート回路31と遅延回路32から構成さ
れ、比較回路3の出力信号に応答してキヤピラリ
13のボンデイング動作を停止させる禁止信号を
出力する。JKフリツプフロツプ30は遅延回路
32を通してタイミング信号発生回路33からタ
イミング信号を入力され定期的に出力端子を
“H”レベルにリセツトする。
Inhibition signal generation circuit 4 is JK flip-flop 3
0, a gate circuit 31, and a delay circuit 32, and outputs an inhibition signal for stopping the bonding operation of the capillary 13 in response to the output signal of the comparison circuit 3. The JK flip-flop 30 receives a timing signal from the timing signal generation circuit 33 through the delay circuit 32, and periodically resets its output terminal to the "H" level.

次に本発明の実施例による動作を第2図のタイ
ミング図を参照して説明する。
Next, the operation according to the embodiment of the present invention will be explained with reference to the timing diagram of FIG.

まずタイミング信号発生回路33からタイミン
グ信号Aが出力されると駆動回路16によりワイ
ヤクランプ手段9が金線10をクランプする。
(第2図A)次にタイミング信号発生回路33か
らタイミング信号Bが出力されると駆動回路17
によりスパーク電極11をキヤピラリ13の直下
に配置する。(第2図B)通常ボンデイングワイ
ヤは直径20〜30μmの金線10が使用され、又キ
ヤピラリ13の先端とスパーク電極11間l1は例
えば1〜2mm程度に設定される。又放電回路5の
直流電源6が550V程度であると金線10の先端
とスパーク電極11間のスパーク間隙l3は例えば
0.15〜0.2mm程度に設定される。
First, when the timing signal A is output from the timing signal generation circuit 33, the wire clamp means 9 clamps the gold wire 10 by the drive circuit 16.
(FIG. 2A) Next, when the timing signal B is output from the timing signal generation circuit 33, the drive circuit 17
The spark electrode 11 is placed directly below the capillary 13. (FIG. 2B) Usually, a gold wire 10 with a diameter of 20 to 30 μm is used as the bonding wire, and the distance l 1 between the tip of the capillary 13 and the spark electrode 11 is set to, for example, about 1 to 2 mm. Further, when the DC power source 6 of the discharge circuit 5 is about 550V, the spark gap l3 between the tip of the gold wire 10 and the spark electrode 11 is, for example,
It is set at about 0.15 to 0.2 mm.

LKフリツプフロツプ30は、前ボンデイング
サイクル時にタイミング信号発生回路33のタイ
ミング信号Cにより、リセツトされるため出力
端子は“H”レベル状態保持されている。又、
AND論理回路34の一方の入力端子は次のタイ
ミング信号が発生されるまで“L”レベル状態に
保持されている。
Since the LK flip-flop 30 is reset by the timing signal C of the timing signal generating circuit 33 during the previous bonding cycle, the output terminal is held at the "H" level state. or,
One input terminal of the AND logic circuit 34 is held at the "L" level state until the next timing signal is generated.

次にタイミング信号発生回路33よりタイミン
グ信号Eが出力されるとスイツチ7が例えば20〜
30ミリ秒間閉じ放電回路5が完成する。これによ
り間隙l3にスパーク放電が発生し金線10の先端
を熔融させる。熔融した金線はボール10aとな
り表面張力によりスパーク放電が持続しない高さ
l2(例えば約0.5mm)まで上昇して停止する。この
様に正常なスパーク状態であれば、波形整形回路
19は所定期間T1(例えば2.5〜3.0ミリ秒)“H”
レベルの信号を出力する。(第2図F) インバータ23から出力された出力信号は遅延
回路2に入力され、期間T1より長く、且つスイ
ツチ7の制御信号Eより短い期間である時間T2
後にパルス信号Gを出力する。(第2図G)この
パルス信号GとFの状態が比較され、波形整形回
路19の出力信号Fのパルス巾が正常のスパーク
期間T1以内であれば“H”レベル信号を出力す
る。(第2図H)JKフリツプフロツプ30に
“H”レベル信号が入力されると出力端子の出
力信号Iは“L”レベル状態に変化しAND論理
回路34に入力される。(第2図I)従つてゲー
ト回路34の出力信号Jは“L”レベルとなり駆
動回路15は正常動作でボンデイングアーム14
を駆動させる。(第2図J,K) 従つてパツド部への熱圧着工程が実行される。
Next, when the timing signal E is output from the timing signal generation circuit 33, the switch 7 changes from 20 to 20, for example.
The discharge circuit 5 is completed by closing for 30 milliseconds. This generates a spark discharge in the gap l3 , melting the tip of the gold wire 10. The molten gold wire becomes a ball 10a at a height where spark discharge does not continue due to surface tension.
It will rise to l 2 (e.g. about 0.5mm) and stop. In this normal spark state, the waveform shaping circuit 19 remains “H” for a predetermined period T 1 (for example, 2.5 to 3.0 milliseconds).
Outputs a level signal. (FIG. 2F) The output signal output from the inverter 23 is input to the delay circuit 2, and the time T 2 is longer than the period T 1 and shorter than the control signal E of the switch 7.
Afterwards, a pulse signal G is output. (FIG. 2G) The states of the pulse signals G and F are compared, and if the pulse width of the output signal F of the waveform shaping circuit 19 is within the normal spark period T1 , an "H" level signal is output. (FIG. 2H) When the "H" level signal is input to the JK flip-flop 30, the output signal I at the output terminal changes to the "L" level state and is input to the AND logic circuit 34. (FIG. 2 I) Therefore, the output signal J of the gate circuit 34 becomes "L" level, and the drive circuit 15 operates normally and the bonding arm 14
drive. (FIG. 2 J, K) Therefore, the thermocompression bonding process to the pad portion is performed.

一方スイツチ信号Eの“H”レベル中にタイミ
ング信号発生回路33よりタイミング信号Cが遅
延回路32に入力され所定の時間経過後JKフリ
ツプフロツプ30の出力端子は“H”レベルに
リセツトされる。(第2図C,D) 次に金線10がスパーク電極11に接触した場
合を考慮すると、スイツチ7のオン期間中放電回
路5に短絡電流が流れる。従つて波形整形回路1
9の出力信号FはT1期間以上に“H”レベル信
号を出力する。(第2図F点線波形)遅延回路2
は信号が入力されると常にT2期間後パルス信号
を出力する。この為比較回路3はスイツチ信号E
が“H”レベル期間中“L”レベル状態に保持さ
れ従つてJKフリツプフロツプ回路30の出力
端子の状態も“H”レベルに保持される。
On the other hand, while the switch signal E is at the "H" level, the timing signal C is input from the timing signal generating circuit 33 to the delay circuit 32, and after a predetermined time has elapsed, the output terminal of the JK flip-flop 30 is reset to the "H" level. (FIGS. 2C and D) Next, considering the case where the gold wire 10 comes into contact with the spark electrode 11, a short circuit current flows through the discharge circuit 5 while the switch 7 is on. Therefore, waveform shaping circuit 1
The output signal F of 9 outputs an "H" level signal for the T1 period or more. (Figure 2 F dotted line waveform) Delay circuit 2
always outputs a pulse signal after a period of T2 when a signal is input. For this reason, the comparison circuit 3 uses the switch signal E.
is held at the "L" level during the "H" level period, and accordingly, the state of the output terminal of the JK flip-flop circuit 30 is also held at the "H" level.

次にタイミング信号発生回路33よりAND論
理回路34の一方の入力端子に“H”レベル信号
が入力されるので、AND論理回路34より駆動
回路15に“H”レベルの禁止信号が出力され
る。従つてボンデイングアーム14は動作を停止
し、IC部品のパツド部への熱圧着工程が完全に
防止される。駆動回路15は解除信号Oが入力さ
れるまで状態を保持する。AND論理回路34が
禁止信号を出力した後一方の入力端子は“L”レ
ベル状態になり、再びAND論理回路34の出力
端子は“L”レベル状態に復帰する。
Next, an "H" level signal is input from the timing signal generation circuit 33 to one input terminal of the AND logic circuit 34, so that the AND logic circuit 34 outputs an "H" level inhibition signal to the drive circuit 15. Therefore, the bonding arm 14 stops operating, and the process of thermocompression bonding of the IC component to the pad portion is completely prevented. The drive circuit 15 maintains its state until the release signal O is input. After the AND logic circuit 34 outputs the prohibition signal, one input terminal becomes the "L" level state, and the output terminal of the AND logic circuit 34 returns to the "L" level state again.

次に金線10の先端とスパーク電極11間がI2
以上である場合を考慮すると、スイツチ7のオン
期間中スパーク放電が発生せず放電回路5に放電
電流が流れない。波形整形回路19の出力信号F
は“L”レベル状態に保持され、遅延回路2の出
力信号Gも“L”レベル状態に保持される。従つ
て比較回路3の出力信号Hも“L”レベル状態と
なり、JKフリツプフロツプ30の信号の“H”
レベル状態を変化させない。その後タイミング信
号発生回路33からAND論理回路34の一方の
入力端子にタイミング信号Cが入力されると
AND論理回路34は駆動回路15に“H”レベ
ルの禁止信号を出力し、ボンデイングアーム14
の動作を停止させる。その後遅延回路32からリ
セツト信号Dが出力され更にJKフリツプフロツ
プ30の出力端子を“H”レベルのまま保持し
次のボンデイングサイクルにクロツク端子CKに
信号が入力されるのを待機する。
Next, there is an I 2 between the tip of the gold wire 10 and the spark electrode 11.
Considering the above case, no spark discharge occurs during the ON period of the switch 7, and no discharge current flows through the discharge circuit 5. Output signal F of waveform shaping circuit 19
is held at the "L" level, and the output signal G of the delay circuit 2 is also held at the "L" level. Therefore, the output signal H of the comparator circuit 3 also becomes "L" level, and the signal of the JK flip-flop 30 goes "H".
Do not change level status. After that, when the timing signal C is input from the timing signal generation circuit 33 to one input terminal of the AND logic circuit 34,
The AND logic circuit 34 outputs an "H" level inhibition signal to the drive circuit 15, and the bonding arm 14
stop the operation. Thereafter, a reset signal D is output from the delay circuit 32, and the output terminal of the JK flip-flop 30 is held at the "H" level, waiting for a signal to be input to the clock terminal CK in the next bonding cycle.

尚本発明の実施例において各タイミング信号を
デイジタル回路によるタイミング信号発生回路3
3を考慮したが、回転シヤフトに取付けられたス
リツト付の制御円盤と検出器を有する機械的な手
段で発生する事も可能である。
In the embodiment of the present invention, each timing signal is generated by a timing signal generation circuit 3 using a digital circuit.
3 has been considered, but it is also possible to generate it by mechanical means having a control disk with a slit and a detector mounted on the rotating shaft.

以上説明した様に本発明によるワイヤボンデイ
ング停止回路はキヤピラリの先端とスパーク電極
間での金線短絡状態及びキヤピラリの先端からの
金線の送出量が少い状態を同様に検出してボンデ
イングアーム動作を停止させるので、キヤピラリ
の先端で半導体電子部品のボンデイングパツド部
を直接“空打ち”する事が完全に防止される。
As explained above, the wire bonding stop circuit according to the present invention similarly detects a gold wire short-circuit condition between the capillary tip and the spark electrode and a condition in which the amount of gold wire delivered from the capillary tip is small, and operates the bonding arm. This completely prevents the tip of the capillary from directly hitting the bonding pad of the semiconductor electronic component.

従つて金線の先端に金ボールが形成されない状
態で自動ボンデイング動作が実行され、連続して
不良品IC部品が製造される事故が解消される。
本発明によるワイヤボンデイング停止回路は高速
度で動作する完全自動ボンデイング装置に使用し
て、非常に高い製造歩留でワイヤボンデイング作
業を可能にするものである。
Therefore, the automatic bonding operation is performed without a gold ball being formed at the tip of the gold wire, and the accident of continuously manufacturing defective IC parts is eliminated.
The wire bonding stop circuit according to the present invention can be used in fully automatic bonding equipment operating at high speeds to enable wire bonding operations with very high manufacturing yields.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるワイヤボンデイング停止
回路の実施例である。第2図は本発明の実施例の
為の動作タイミング図である。 1……放電電流検出回路、2……遅延回路、3
……比較回路、4……禁止信号発生回路。
FIG. 1 is an embodiment of a wire bonding stop circuit according to the present invention. FIG. 2 is an operational timing diagram for an embodiment of the present invention. 1...Discharge current detection circuit, 2...Delay circuit, 3
...Comparison circuit, 4...Prohibition signal generation circuit.

Claims (1)

【特許請求の範囲】 1 スパーク電極とボンデイング用金属線間に放
電電流が流れると放電期間に相当する第1のパル
ス信号を出力する放電電流検出回路と、前記第1
パルス信号の発生時から所定の時間経過後第2の
パルス信号を出力する遅延回路と、前記第1パル
ス信号のパルス巾と前記遅延時間を比較する比較
回路と、前記比較回路の出力信号に応答して半導
体素子のパツド部と前記ボンデイング用金属線と
の熱圧着工程を停止させる信号を出力する禁止信
号発生回路を含むワイヤボンデイング停止回路。 2 前記遅延回路が複数の単安定マルチバイブレ
ータからなる事を特徴とする特許請求の範囲第1
項記載のワイヤボンデイング停止回路。 3 前記遅延時間が3ミリ秒以上である事を特徴
とする特許請求の範囲第1項記載のワイヤボンデ
イング停止回路。
[Scope of Claims] 1. A discharge current detection circuit that outputs a first pulse signal corresponding to a discharge period when a discharge current flows between the spark electrode and the bonding metal wire;
a delay circuit that outputs a second pulse signal after a predetermined time has elapsed from generation of the pulse signal; a comparison circuit that compares the pulse width of the first pulse signal with the delay time; and a response to the output signal of the comparison circuit. A wire bonding stop circuit including a prohibition signal generating circuit that outputs a signal to stop a thermocompression bonding process between a pad portion of a semiconductor element and the metal wire for bonding. 2. Claim 1, wherein the delay circuit comprises a plurality of monostable multivibrators.
Wire bonding stop circuit described in section. 3. The wire bonding stop circuit according to claim 1, wherein the delay time is 3 milliseconds or more.
JP57140962A 1982-08-16 1982-08-16 Wire bonding stopping circuit Granted JPS5931036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57140962A JPS5931036A (en) 1982-08-16 1982-08-16 Wire bonding stopping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57140962A JPS5931036A (en) 1982-08-16 1982-08-16 Wire bonding stopping circuit

Publications (2)

Publication Number Publication Date
JPS5931036A JPS5931036A (en) 1984-02-18
JPS6361776B2 true JPS6361776B2 (en) 1988-11-30

Family

ID=15280860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57140962A Granted JPS5931036A (en) 1982-08-16 1982-08-16 Wire bonding stopping circuit

Country Status (1)

Country Link
JP (1) JPS5931036A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548377Y2 (en) * 1989-09-26 1993-12-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548377Y2 (en) * 1989-09-26 1993-12-24

Also Published As

Publication number Publication date
JPS5931036A (en) 1984-02-18

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