JPS6350719A - Electronic absolute encoder - Google Patents

Abstract

PURPOSE:To obtain a highly accurate small-sized encoder, by adding an A-phase encoder signal and a B-phase encoder signal shifted by 90 deg. in phase from said A-phase signal in a set ratio and forming n-pieces (n is an integer of 1 or larger) of n-phase encoder signals. CONSTITUTION:The A-phase signal obtained from an encoder is taken on a Y-axis and the B-phase signal obtained therefrom is taken on an X-axis. Two phases are added to the fundamental vibration A-phase signal and fundamental vibration B-phase signal (A=sintheta, B=costheta, a peak value = a) of the encoder in a certain ratio to amplify said signals so as to obtain the peak (a) to obtain a vector (e). That is, a C-phase signal is obtained in addition to the A-phase and B-phase signals of the encoder. As mentioned above, when two encoder signals are added in a certain ratio and the signals are amplified so as to obtain the peak value (a), from said signals, n-phase encoder signals shifted in phase infinitely like C, D, E... phases in addition to the A-phase and the B-phase can be formed. Therefore, by further linearly forming n-phase encoder signals by the same method, highly accurate multiphase n-phase encoder signals can be formed inexpensively and easily.

Description

[Detailed Description of the Invention] (Industrial Field of Application) The present invention is applicable to processing: mechanical machines, robots, mo! The present invention relates to an electronic absolute encoder that is useful for use in devices and other devices that perform positioning using encoders.

(Problems with the Prior Art) In a device that uses an encoder for positioning, etc., the higher the accuracy of the positioning, the more it is necessary to use an encoder that can obtain a large number of pulses.

Encoders that can produce a large number of pulses (high pulses) are large and expensive. For this reason, there are many cases where it cannot be used in the device to which it is intended.

Furthermore, if a small encoder capable of producing high pulses is selected, this encoder has the disadvantage that it is manufactured with great precision and precision and is therefore very expensive.

In many cases, a given objective can be achieved using a small, high nTK encoder, which can be very expensive.

However, with conventional small-sized, high-precision incremental encoders, it is difficult to obtain all the encoder signals from a limited-sized encoder.

If you want to obtain a high pulse encoder signal,
It is necessary to increase the machining accuracy (in the case of optical encoders) and the m accuracy (in the case of magnetic encoders), but this means that when trying to obtain higher pulse encoder signals, There is a limit.

Using the original oscillating A-phase encoder signal and the original oscillating A-phase encoder signal, directly using a 2x circuit or 4x circuit,
Although methods are known for obtaining the entire double or quadruple encoder signal, at most only a double or quadruple signal can be obtained, and it has been impossible to obtain an encoder signal larger than that.

(Object of the present invention) The present invention provides an original in A-phase encoder signal having at least a predetermined peak value, and an original in A-phase encoder signal having a predetermined peak value that is shifted by about 90 degrees in electrical angle from the original A-phase encoder signal. Using an encoder that can obtain a B-phase encoder signal, it is easy to easily generate n-phase encoder signals (n is an integer of 1 or more) for the original A-phase encoder signal and the original B-phase encoder signal using an electric circuit; The objective is to obtain a high-pulse, high-precision, single-degree electronic absolute encoder in a compact and inexpensive manner by forming one word of a multi-phase encoder.

(Means for Achieving the Topic of the Present Invention) The problem of the present invention is to add the 1(n) phase encoder signal and the B phase encoder signal of the encoder at a set ratio.
is an integer greater than or equal to 1), and using two selected encoder signals among the formed n-phase encoder signals, the above-mentioned signal is generated between the selected two encoder signals. This is achieved by sequentially forming new n-phase encoder signals in a similar manner.

(Example) Electronic absolute encoder of the present invention: According to ζ, A
The outline of how a multiphase encoder signal is obtained using an encoder sound from which two signals, phase and B phase, are obtained will be explained with reference to FIG.

Referring to FIG. 1, the A-phase signal obtained from the encoder is plotted on the Y-axis, and the B-phase signal is plotted on the Y-axis. Encoder original S
A phase signal, original oscillation B phase signal (A = sinθB-cas
When the two phases are added at a certain ratio to θ, peak value -a) and the signal is fully amplified so that the peak value is aK, a vector C is obtained. That is, as shown in FIG. 2, a C-phase signal is obtained in addition to the KA-phase and B-phase encoder signals.

In this way, by adding the two encoder signals at a certain ratio,
When the signal is amplified so that the wave height becomes flt &, the signal will be C, D, and E in addition to phase A and B;■.

..., it is possible to create an encoder signal of 90 phases with an infinite phase shift.

The Toki that waveform-shaped the encoder signals of each phase,
By reading the up edge and down edge, two pulses can be obtained per pulse. Now, with respect to the number of pulses k of the uniform per revolution, in the case of phase 3n, the number of pulses per revolution is K = 2 n k (1)
However, n is an integer greater than or equal to 1, and resolution can be improved.

The case where all encoder signals of the next KA-H phase are generated will be explained.

FIG. 3 is a vector diagram, FIG. 4 is a waveform diagram of the A-H phase encoder signal, and FIG. 5 is a fixed timing chart of the entire waveform of the A-H phase encoder signal.

Referring to Figure 3, A;! 1: A case will be explained in which a C-phase encoder signal and a D-phase encoder signal are created using an encoder signal and a B-phase encoder signal. The human phase and B phase encoder signals appear as shown in FIG. In addition, λ is A
An encoder signal for the inverse of the phase encoder signal, other B and C
, D, . . . phases, but the diagrams for these are omitted.

Generally, the encoder outputs A-phase and B-phase encoder waveforms 1 that are shifted by 90 degrees in electrical angle, as shown in Figure 4.
．． 2 is obtained. This A-phase and B-phase encoder is the third
As is clear from the figure, when the A-phase encoder signal is expressed as a full voltage signal VA, when the peak value is k, it becomes: (2) A-kasmθ , , (2), and when the B-phase encoder signal is expressed as a voltage signal VB , Va = k-house θ (3).

Therefore, when the C-phase encoder signal vc shown in FIG. 4 is formed between the A-phase encoder signal VA and the B-phase encoder signal v8, as is clear from FIG. 3, the C-phase encoder signal Va becomes Vo=sln45°.・A+cas45°@B=0.7
0711A + 0.707・B...(4)
Therefore, between the fc A-phase encoder signal V and the B-phase encoder signal Va, the D-phase encoder waveform 4? have D
When the phase encoder signal VD k is formed, VD-sin (
45') ・A+cm(45°)-B= -0,707
A+0.707B...(5).

From this, the C-phase encoder waveform is obtained by equation (4), f
As shown in Fig. 4, only the c waveform is formed at the 9th position of the input phase encoder signal, and similarly, the D phase encoder waveform is obtained by equation (5) and is 7t @ (as shown in Fig. 4) and A. It is formed by shifting rcI from the phase encoder code.

At the same time, encoder waveforms 5, 6, 7 of the E phase, F phase, C phase and H phase shown in the 4th Z are shown. and 8 these encoder signals Vp, VP, Vo and VH are the fifth
As is clear from the figure, it can be expressed as follows.

VI knee VA ・5lfI60°+ VB' CQS
6σ= o, s 66 φVA+ 0.5 VB・=
(6) VP=VA-sin 30°+VB-co
s 30° = 0.50V person + 0866・VB
...(7) Vo = VA @= (30'
) + Vn-ays (30°)-0,5-VA 10 0.866 11 Va
='(8) Vo = VA ・sin (60°)
+VB -cos(60°)=0.866 conflict ■+0.
5VB (9) Therefore, the encoder signals of each A to H1141 appear as shown in FIG. 6(,) to (h) over a range of 360 degrees in electrical angle.

By detecting either the rising or falling of the waveforms shown in FIGS. 6(a) to (h), for example, by using it in a motor, it is possible to determine the rotation 1, rotation angle, angular velocity, rotation speed, and rotation direction of the motor. You can know the rotation information such as. In this way, the original oscillation A-phase encoder signal with a predetermined peak value a and this original oscillation A
By using an encoder that can obtain the original B-phase encoder signal with a phase shift of 90 degrees in electrical angle from the phase encoder signal and a predetermined peak value a, the A-phase encoder and B-phase encoder signals are set and added at a ratio of 9. By doing so, n(n is 1
(an integer greater than or equal to) n-phase encoder signals are formed near IJ, and any two of these
It is possible to inexpensively and easily form highly accurate multi-phase n-phase encoder signals by selecting the encoder signals and forming new n-phase encoder signals y and IJ in the same manner as described above. can.

The n-phase encoder signal obtained in this manner is further conventionally known as a method of increasing the encoder signal i=temporarily. (2) By increasing the resolution digitally by two or four times using a multiplication circuit or a quadruple multiplication circuit, it is possible to obtain a more accurate encoder signal. Obtainable.

For example, in the above example, eight encoder signals A-H are obtained based on the A-phase and B-phase encoder signals, but by using a multiplier circuit or a quadruple multiplier circuit,
It is possible to obtain 6 encoder signals or 4 encoder signals for 32 encoders.

Next, from the A phase, B phase, original oscillation encoder signal to the E phase, F phase
An example of a concrete circuit for creating the original encoder signals of phase, C phase and 1 (phase) is shown in FIG.

In addition, in this circuit, the part that forms all the C-phase and D-phase encoder signals is omitted, but if you create the above E-H;..., just by adding all the same circuits, you can generate the C-reciprocal Reniji/coder signal. can also be easily formed.

Referring to FIG. 7B, the A-phase encoder 1' word from the encoder is input to the terminal 9. A B-phase encoder signal from an encoder is input to the terminal 10. The outputs from the terminals 9 are connected to round-off inverting amplifier circuits 11 that respectively receive the in-phase encoder signals. The output from terminal 10 is a picture encoder signal.
] is connected to the tth inverting amplifier circuit 12. The inverting amplifier circuits 11 and 12 are connected to terminals 9 and 10, respectively, and are connected to negative input terminals 17 and 18 of operational amplifiers 15 and 16 through resistors 13 and 14, respectively.
The positive input terminal of 6 is connected to ground 2 through resistor 19, 204-.
1, connected to terminals 17.18 and op amp 15.16
A feedback resistor 24. is connected between the output terminals 22.23 of the .
25'! - Intervening. The A;1111 encoder signal and the π-phase encoder signal formed by the inverting amplifier circuit 11.12 are output from the output terminal 22.23 of the inverting amplifier circuit 11.12, respectively. Output terminal 22.2
3 is connected to an addition/amplification circuit 26 for forming an E-phase encoder signal. The summing φ amplifying circuit 26 is interposed between the terminals 22 and 23, and is connected to a series circuit of a series of resistors 27 and 28, which adds the A-phase encoder signal and the π-phase encoder signal according to the above equation (6): It consists of an operational amplifier 29 for amplifying the tE phase encoder signal added by the series circuit so that it has the same width as the X (A) phase encoder signal and the 100 (B) phase encoder signal. A connection point 60 between the resistors 27 and 28 is connected to the negative input terminal of the operational amplifier 29. The positive input terminal of the operational amplifier 29 is connected to the ground 21 side. Reference numeral 31 denotes an output terminal of the addition/amplification circuit 26, from which an E-phase absolute encoder voltage signal is output. A feedback resistor 6 is connected between the terminal 30 and the negative input terminal of the operational amplifier 29.
2 is interposed.

In parallel with the series circuit of the resistors 27 and 28, there are resistors 66 and 6 for adding the above A-phase encoder signal and ■-phase encoder signal according to the above formula (force) to form an F-phase encoder signal.
It is connected in parallel with 4 series circuits. These resistors 63 and 34
An addition/amplification circuit 65 including a series circuit called Toyoshi is connected to both terminals 66 of a series circuit made up of resistors 27 and 28.
It is formed ahead of 67.

This addition/amplification circuit 35 consists of a series circuit of the resistors 66 and 64, and an operational amplifier 68 that amplifies the next F-phase encoder signal that is added by the series circuit. Above resistance 6
A connection point 69 between 3 and 34 is connected to the negative input terminal of the operational amplifier 38.

The positive input terminal of the operational amplifier 68 is connected to the ground 16 side. Reference numeral 40 denotes an output terminal of the addition-amplification circuit 35, from which an F-phase absolute encoder voltage signal is output. A feed bank resistor 41 is interposed between the output terminal 40 and the negative input terminal of the operational amplifier 68. The Aa encoder signal is connected between the output terminal 23 of the inverting amplifier circuit 12 and the terminal 10 according to the above equation (8). The resistors 42 and 46 are interposed in a series circuit for adding all the B-phase encoder signals and adding the G-phase encoder signal. Terminals 26 and 44 are connected. An adder/amplifier circuit 45 is formed by including a series circuit including resistors 42 and 46. This addition/amplification circuit 45 consists of a series circuit made up of the resistors 64 and 65, and an operational amplifier 46 that amplifies the nine G-phase encoder signals. 47 is connected to the negative side input terminal of the operational amplifier 46.The positive side input terminal of the operational amplifier 46 is connected to the ground 13 side.48 is the output terminal of the addition/amplification circuit 45, and from this terminal 40 A G-phase absolute encoder voltage waveform signal is output. A feedback resistor 49 is interposed between the output terminal 48 and the negative input terminal of the operational amplifier 46.

Between the output terminal 22 and the terminal 10 of the inverting amplifier circuit 11, there is a series circuit of resistors 50 and 51 for adding the A-phase encoder signal and the π-phase encoder signal according to the above equation (9) to form the H-phase encoder signal. An adder circuit consisting of the following is interposed. The series circuit of resistors 50 and 51 and the operational amplifier 52 form an addition/amplification circuit 56. Resistors 50 and 51
The connection point 54 of is connected to the negative input terminal of the operational amplifier 52.The positive input terminal of the operational amplifier 52 is
Connected to 1. Therefore, the input phase encoder signal and the picture encoder signal are added at a predetermined ratio by the resistors 50 and 51 to form a linear H-phase encoder signal, and the nuclear H-phase encoder signal is amplified by the operational amplifier 52. A voltage signal is output from the output terminal 55. 56 is a feed pad resistance. The C-phase and D-phase encoder signals are similarly formed. Therefore, as shown in FIG. 4, the linear A-H phase encoder voltage signal 1. ~.

8 can be formed at equal intervals.

Referring to FIG. 8, the method of determining the resistance value of the adder circuit in FIG. 7 will be explained in a row for obtaining a G-phase encoder signal.

Now resistor 42 is R+, resistor 46 is R2% resistor R1 terminal (
Assuming that the voltage at the connection point 26 is Vx, the voltage at the terminal 9 is Vy, and the voltage at the terminal 48 is Vz, the following relational expression holds true in the adding circuit of FIG.

The above equation (10) is, therefore, a companion for obtaining the G-phase encoder signal in the adder circuit of FIG. 8, but it is assumed that the following equation holds.

0.5 VA+ 0.866 VB -Va
C121 above formula 00) ~ (Since it is one, Vx = VA y-Va VZ = VG (15), so if we decide that R1 = 5 (KΩ), then R2 = 8.
66 (KΩ) R3= o, 5x5[:Ω:l=2.5[:Ω:]
(16) K should be selected.

Note that with an encoder that can only obtain a normal A-phase encoder signal, referring to FIG. The encoder is configured to obtain a signal waveform, and by forming pulses shown by reference numeral 58, an encoder signal of 2 pulses per period is formed, and in order to further increase the electrical resolution, a doubler circuit is added. Further, pulses as shown at 59.60 are obtained.

However, if the original integer circuit configuration shown in FIG. 7 is adopted as in the present invention, 12 pulses in the CW direction can be obtained within one period T.

That is, since a large number of pulses can be obtained using a 12 multiplier circuit (it does not matter whether it exists or not), the resolution of the encoder can be improved with extremely high accuracy. Note that in the original oscillation n-multiplier circuit shown in Fig. 7, all C-phase and D-phase encoder voltage signals are not formed, but if this is also formed, as can be understood from the timing chart in Fig. 9, even more cw , ccw direction pulses can be obtained. In addition, in Figure 9, the same (,) to (0
(g) shows the A, E, F, B, G, and H phase encoder signal generation timing charts, respectively. -(h,)
('W, shows a pulse generation timing chart for encoder signals in the CCW direction.

In this way, by employing the original oscillation n-multiplier circuit of the present invention, it becomes possible to form many n-phase encoder signals across an infinite number of times. Whether or not to obtain a specific encoder store name is determined based on the design, including the configuration and cost. The 7'Cn phase encoder waveform obtained by this Din multiplier circuit is further multiplied by m by a conventionally known m (an integer greater than or equal to 2) multiplier circuit.
This makes it possible to form an encoder with even higher resolution.

This means that the pulse forming circuit for the final stage encoder in Figure 10 is
N! 61 will be used for explanation. In addition, in this diagram, the circuit 61 is schematically drawn like the eye of a goban, and is connected to the Kuchiin, Seal, and Old Seal O Seal, respectively. . Here, the mark m means the waveform quadrature circuit 62 as shown in FIG. 11, and the mark m means the waveform circuit 63 as shown in FIG. The mark is ANDl'1W64, and in the case shown in FIG. 13(a), is it an equal circuit with the AND circuit 64 shown in FIG. 13(b)? 14 (a) (2) is an equivalent circuit to the AND circuit 65 shown in FIG. 14 (b). Figure 15 shows the waveform shaping circuit 6 indicated by the above country seal.
6 shows a specific example of the circuit, which mainly includes an operational amplifier 66, a feed bank resistor 67, and a resistor 69 connected to ground 68. Figure 16 (knee 1) shows a specific circuit example of the amplifier edge/down edge detection circuit 66 indicated by the mark above, where 70 is an oscillator, 71 and 72 are Da flip-flop circuits, and 76 is an inverter. ,7
4.75 indicates a NOR gate. When the AND circuits 64 and 64 in FIGS. 11 to 16 and 13 intersect, this indicates that a CW pulse is output from the output terminal of the OR gate 7B as shown in FIG.

Furthermore, if the AND circuits 65 and 65 in FIG. 14 intersect, this indicates that a CCW pulse is output from the output terminal of the OR gate 77 as shown in FIG.

Figure 19 is a timing chart, with (a-1) in the same figure,
-..., (a-6) is shown in Figure 10 (a), .
Corresponding to (f), phase A, phase E, phase F, and phase B, respectively.

A pulse generation timing chart for encoder signals for G phase and H is shown. These timing charts are
In Fig. 10, with reference to the A-phase encoder signal VA', when rotating in the CW direction, the phase is delayed by 30 degrees in electrical angle, mE-phase encoder signal VE is generated, and the phase is further delayed by 30 degrees in electrical angle. F-phase encoder signal Vr
It can be obtained by making f. Then, sequentially, 3 in electrical angle
Six encoder signals are obtained by creating nine B-phase, G-phase, and H-phase encoder signals V o +Vo and Vuk with a 0 degree phase delay. And these six A phases,
E phase.

Encoder signal VA of F phase, B phase, G phase, and H phase.

Vx, Vy, %, Vo and VHk anti-E
L, enter phase.

Inverted encoder signals for bad phase, r phase, image, d phase and n, nu phase, VB phase, VP phase, ■ phase, VO phase and ■ phase?
, 19(b-1), . . . , (b-6). Each A phase...
, H phase, input phase..., n-phase encoder signal vA,...
. . . , VH, control, . . . , VB rising and falling signals, the up/down Φ edge check circuit 63 of the amplifier in FIG. 12
) is formed as shown in the timing chart. After that, the AND circuit 6 of the pulse forming circuit 61 in FIG.
5-1,...

65-12, the respective encoder signals are combined to form 12 encoder signals as shown in the 199th (d-1), . . . +(d12) timing charts. For example, the timing chart in (d-1) of the same figure is a combination of the A-phase encoder signal V and the B-phase encoder signal VB.

It has become. Also, A of the pulse forming circuit in FIG.
ND circuit 64-13. . . , 64-24. Therefore, each encoder signal is combined as shown in FIG. 19 (d-1
3), . . . +(a-24) 12 encoder signals as shown in the timing chart are formed. In this manner, in this embodiment, a total of nine new 24-concave encoder signals are formed.

When the rotation direction of these 2.1 encoder signals is reversed,
That is, half of the 12 encoder signals centered around the dotted line 79 are ORed by the OR gate 77 to obtain the result shown in FIG. 19 (d-CW).
The CW pulse indicating the timing of is ORed with the remaining ν of 12 encoder signals by the OR gate 76, and the result is shown in FIG.
-CW) to obtain a CCV pulse as shown in the evening/imming yard. As is clear from the above,
According to the electronic absolute encoder of the present invention, in the conventional encoder, the A phase is linearly outputted.

At this point, the original encoder signal obtained as two linear output waveforms of phase B can be multiplied by n, so
An infinite number of phase encoder signals can be obtained with extremely fine pitches.

In this way, the linearly obtained original encoder signal is formed into an infinite number of phases, that is, n phases, and after t, it is further digitally multiplied by n times as conventionally and generally adopted. By obtaining an encoder signal with multiple encoders, an encoder signal with a higher number of divisions can be obtained entirely electrically.

In other words, in the electronic absolute encoder of the present invention, even if the mechanical part of the encoder is cheap and crude, it is possible to increase the resolution electrically and generate encoder signals with high precision at a low cost. This is something you can get. In this case, if the encoder of the mechanical part has excellent resolution, it is possible to obtain an electronic absolute encoder with even higher electrical resolution at a lower cost.

FIG. 20 shows an electronic absolute encoder 8 of the present invention.
0 fully integrated electronic absolute encoder circuit 81
shows.

20, 82 is a DC-I)C converter 86 is a diode, 84 is a resistor, 85 is a voltage comparator, 8
6.87 is a power supply battery, 88.89 is a connection part, and 90 is an encoder that, when used with a magnetic encoder, detects the magnetic encoder layer number by the N and S magnetic poles of the magnetic encoder and outputs a magnetic encoder signal. Therefore, we selected an FC magnetoresistive element (MR sensor) as the magnetic sensor.
The output signals of the one or more magnetoresistive elements 90 are amplified by an amplifier circuit 91, and the amplified encoder signal is output from an output terminal 92 of the amplifier circuit 91. The Z-phase signal from the magnetoresistive element 90 is input to the error circuit 100 via the amplifier circuit 91 and its output terminal. Further, the linear original encoder signal knee 1 of the magnetoresistive element 90DA phase and B phase is amplified by the amplifier circuit 91,
The electronic amplifier IJ z-to source 4H and multiplication circuit (electronic absolute encoder times>@) 8o+c are inputted through the output terminal 92 and the connecting portion 89.

Note that this original oscillation n times multiplier circuit 80 is a t times circuit. The output terminals 93 and 94 of the CW and CCW pulses of the original oscillation quadrupling circuit 80 are connected to a counter circuit 95, and the output of the counter circuit 95 is outputted to the buffer circuit 96, and then from the output terminal 297. Encoder signals are output.

The main operations of the electronic absolute encoder circuit 81 will be explained with reference to FIG.

When power is supplied from the external input terminal 98, the voltage is D.
The signal is supplied to the C-DC converter 82, and is also supplied to the amplifier circuit 91, the electronic absolute encoder 80, the error circuit 100, and the counter circuit 95 through the entire diode 99.

Further, the above voltage is supplied to the buffer circuit 96 and the air circuit 100 through the diode 1o1i.

For example, if the rotary magnetic encoder 102 (the configuration of which will be described later) is an absolute magnetic encoder as shown in FIG. When the shaft 104 is rotated, the magnetic resistance element 9
The output of 0 changes, and this changed output signal is amplified and waveform-shaped by the amplifier circuit 91. The A-phase and B-phase square wave signals of the magnetoresistive element 90 that have been amplified and waveform-shaped are sent to an electronic absolute encoder 80 (in this case, a quadrupling circuit is used). , CW, CCW pulse ((converted, counter circuit 9
It enters 0, is counted, and output data of absolute value is obtained. This data is output to the outside through the back 7 circuit 96. At the same time, the output of the DC-DC converter 82 [
12V] passes through a diode 83 and a resistor 84 to charge the power supply batteries 86 and 87. If the power source 7 is not supplied from the outside, voltage will be applied to each circuit from the power source batteries 86 and 87. Even in this state, the shaft 104 of the rotary magnetic encoder 102 is rotated: f, and the count value increases or decreases accordingly. As a result, the absolute position of the encoder can always be known in any case, just like a general encoder on an amplifier.

At this time, if the voltage of the power supply batteries 86 and 87 decreases and becomes lower than the set voltage of the voltage comparator 85, the voltage
The output of the bar 85 is low CL) level: fC.

However, at this time, since power is not supplied to the alarm circuit 105 , no alarm signal is output from the output terminal 106 .

When the power is turned on in this state, the D-type flip-flop circuit 107 and inverter 108 shown in FIG. [■] Level: C. This is the electronic alarm in Figure 22 - Error 'A% 1
Since a slight delay occurs due to the integration circuit 112 composed of the capacitor 110 and resistor 111 of 09, the D-type flip-flop 107 and inverter 108 can have sufficient setup time, and the output of the comparator 85 is It goes into the D terminal of flip-flop 107. At the same time as the constant power is turned on, the CLK terminal of the flip-flop circuit 107 also becomes high (H) level, but this is also caused by the capacitor 11.
3 and a resistor 114. At this time, the flip-flop circuit 10 by the integrating circuit 112
The capacitor 110 is connected so that the delay of the signal to the CLKi terminal of the flip-flop circuit 107 by the integrating circuit 115 is sufficiently larger than the delay of the signal to the D terminal of the flip-flop circuit 107.
゜113, t that sets the constants of resistors 111 and 114
Therefore, according to the timing charts shown in FIGS. 23(,) to (h), the output from the flip-flop circuit 107 lowers the comparator set voltage to 116 or less during battery backup (see FIGS. 2 and 22). reference)
It turns out that the battery voltage 117 of 86.87 drops.

In FIG. 23, (b) shows the comparator output 118 of the comparator 82, (C) shows the timing chart 119 of the power supply voltage, and (d) shows the voltage timing chart 120 of the capacitor 116. 12E shows a timing chart 121 of the CLK terminal of the flip-flop circuit 107, FIG. 1F shows a timing chart 1-121 of the capacitor 110, and FIG.
g) shows a timing diagram) 121 of the D terminal of the flip-flop circuit 107, and (h) of the same figure shows the flip-flop output 124.

Next, the electronic absolute encoder circuit 81 in FIG.
In this case, if noise is introduced in the middle, data deviations due to the noise will accumulate. On this occasion,
This circuit 81 is provided with an error detection circuit 100 for detecting the data deviation. For example,
The case where it is used in the rotary magnetic encoder 102 shown in FIG. 21 will be described below. Before that, this 21st
The configuration of the rotary magnetic encoder 102 shown in the figure will be explained. Referring to FIG. 21, a cup-shaped rotary magnetic encoder case 126 made of a magnetic material is fixed with screws 127 to a flange 125 formed entirely on the fixed side. A cylindrical bearing holder 128 is integrally formed on the flange 125.
Bearings 129 and 130 are mounted on both upper and lower ends of the inner periphery of the
This bearing 129.130 allows the shaft 104'(+
- Rotatably supported. A cup-shaped magnet rotor 103 is fixed to the shaft 104.
It rotates together with 04. As this magnet rotor 106, for example, one shown in FIG. 24 is used. The cup-shaped magnet rotor 106 shown in FIG. 24, for example, has two magnetic tracks 131 and 132 formed in two stages, upper and lower, and the lower magnetic track 132 has N and S magnetic poles alternately arranged at a required pitch. The encoder magnetic field 166 is formed by radially magnetizing the k1000 poles to form a 7-hole encoder magnet. Also, on the upper magnetic track 161, there is one N for every 100 magnetic encoder magnetic poles 166.
A detection magnetized portion 134 of a pole (the pole may be an S pole) is magnetized in the radial direction. A magnetoresistive element mounting plate 138 is provided on the flange 125 to face the outer circumferential surface 135 of the magnet rotor 106 with a radial gap 136 in between, and is fixed to the flange 125 with screws 167 for mounting the magnetoresistive element 90. A mounting plate 138 facing the outer peripheral surface 165 of the magnet rotor 106 of the mounting plate 138
On the surface, there is a detection magnetized part 164 for detecting the two phases.
In addition, the magnetic encoder magnetic pole 135 is fixed to a magnetoresistive element 90 in which a detection section is formed in two stages, upper and lower.

In the case of the rotary magnetic encoder 102 using the magnet rotor 103 shown in FIGS. 21 and 24, the error detection circuit 100 shown in FIG. When all of the data up to is low level, the D-type flip-flop circuit 16 of the error detection circuit 100 in FIG.
The CLK terminal No. 9 becomes high [H] level. At this time K.H.
If one two-phase signal is output from the D terminal via the inverter with exactly 100 pulses, the output of the flip-flop circuit 139 becomes high (H) level.

This is illustrated by timing chart 140 in FIG. The same figure (,) is an output timing diagram of a pulse in the CW (or CCW) direction obtained from the IC 141-1 in FIG. 25) 142'? The same figure (b) shows the timing chart 146 of the 6-bin output of the engineering C141-3, and the same figure (
C) shows the timing chart 144 of the Z-phase signal obtained from the flip-flop circuit 169 in FIG. 22 of the error detection circuit 100, and FIG. 26(d) shows the timing chart 14 of the four outputs of the flip-flop circuit 139 in FIG.
Show El. In this timing chart 145, the 26th
In the figure, if noise occurs during section 146,
A case is shown in which the signal every 100 pulses and the Z-phase signal obtained from the above terminal are shifted.

25 shows a counter circuit 95 and a buffer circuit 96, and rotary switches SW, , SW2, and switch SW3 are used to match the Z-phase signal obtained at the beginning (ζ) with the counter value of the counter circuit 95. And rotary switch SW.

5Wzk Set to an appropriate value and switch SW3 k Z
Turn the encoder 106t to the signal side terminal 145 side and rotate it in the direction in which the count value (counter) of the encoder 106t counter circuit 95 becomes 1.
By obtaining the signal from the terminal, the counter of the counter circuit 95 is set to the regular (Naoe set. This will be explained with reference to the timing chart 148 in FIG. 27. This timing chart 148 shows the above two signals. In the timing chart, “○○○” appears at the 149th position of the rising edge of the waveform.
The value of "○○○○" is set.The value of the last two digits "○○" in this "○O○○××#" is exactly the value of "○○O○○O' of the two-phase signal. Therefore, the counter circuit 95 is set to the above-mentioned normal value.

FIG. 28 shows a specific circuit example of the electronic absolute encoder 80, which includes a quadrupling circuit 15 that multiplies the A-phase encoder signal obtained from the magnetoresistive element 90 by four.
0, this circuit 150 allows the C phase, b phase, C phase and f
A phase encoder signal is obtained. FIG. 29 shows the B-phase encoder signal obtained from the magnetoresistive element 90 at 4
A quadruple multiplier circuit 151 multiplies the signal by four times, and this circuit 151 obtains C-phase, d-phase, 9g-phase, and h-phase encoder signals. The above quadruple multiplier circuit 150. With $51, a total of 8 encoder signals of C phase, . . . , h phase can be obtained. FIG. 30 shows a specific circuit example of the CW direction pulse generation circuit 152, in which the KC and CW pulses are based on the encoder signals of the C phase, .
A pulse in the W direction is obtained. FIG. 31 shows a CCW direction pulse generation circuit 156, which obtains pulses in the CCW direction based on the C-phase, . . . , h-phase encoder signals. 32 to 34 show specific circuit examples of the amplifier circuit 91 for amplifying the encoder signal obtained from the magnetoresistive element 90.゛The amplifier circuit 90-B amplifies the encoder signal, and the amplifier circuit 90-B outputs the B obtained from the magnetoresistive element 90.
The amplifier circuit 90-Z amplifies the phase encoder signal.
The Z-phase encoder signal obtained from the magnetoresistive element 90 is amplified.

Incidentally, in the electronic absolute encoder of the present invention, a rotary magnetic encoder is used as the encoder, and a magnetoresistive element is used as the sensor to show proportionality, but other magnetic sensors such as a Hall element, a Hall IC, or a magnetic head may be used as appropriate. It goes without saying that other sensors may be used.

Furthermore, it goes without saying that the rotary magnetic encoder is not limited to the rotary magnetic encoder, and that an encoder of the example type, such as an optical encoder, may be used.

(Effects of the Invention) According to the present invention, linear waveforms of the Ag-th and B-phases are obtained from the encoder. n using the bobbin thread encoder waveform
It is possible to adapt the encoder to have a vibration waveform that is multiplied by t and n times, and convert the linear encoder waveform of this n multiplied linear waveform into a digital processing method that has been used conventionally. By using a multiplier circuit, encoder signals with an infinite number of phases can be obtained.

Therefore, even if you use an inexpensive encoder with relatively low precision, that is, only a relatively small number of encoder signals can be obtained, it is possible to increase the resolution electrically. There is an advantage that a high-precision electronic absolute encoder that can obtain pulses can be constructed easily and at low cost.

[Brief explanation of the drawing]

Figures 1 to 6 are explanatory diagrams of the process of the present invention. Figure 1 is a vector diagram of the encoder's A phase signal 'kY axis' and the pB phase signal 'z X axis, and Figure 2 is a vector diagram of the A phase signal taken on the X axis. The waveform diagram of each original oscillation encoder signal is formed from the oscillation encoder signal and the B-phase original oscillation encoder signal on the C-phase encoder signal, and FIG. Figure 4 shows the waveforms of the C-phase to H-phase original oscillation encoder signals based on the waveforms of the A-phase and B-phase original oscillation encoder signals. Waveform diagram of encoder signal of original oscillation A phase to H phase when formed, Fig. 5 it A phase, B
A vector diagram of the original oscillation encoder for phase, E phase, F phase, C phase, and H phase, and FIG. 6 is a timing chart of the original oscillation A phase to H phase encoder waveforms. Figure 7 shows the original Sn multiplier circuit that creates the original C-phase to H-phase encoders from the original A-phase and B-phase encoder signals, and Figure 8 shows how to determine the resistance value of the adder circuit in Figure 7. Fig. 9 is an explanatory diagram of the original mA-phase to H-phase encoder signals and a nox generation timing chart of the encoder signals in the CW and CCV directions based on these signals.
Figure 0 shows the pulse forming circuit for the final encoder, Figure 11 shows the waveform shaping circuit, Figure 12 shows the up/edge detection circuit, Figures 13 and 14 show the AND circuit, and Figure 15 shows the waveform shaping circuit. Figure 16 shows the up edge/down edge detection circuit, Figures 17 and 18 show the OR gate, Figure 19 shows the timing chart, Figure 20 shows the electronic absolute encoder circuit, and Figure 21 shows the rotary absolute encoder. An explanatory diagram as an example, Fig. 22 is an electronic alarm circuit, Fig. 23 is a timing chart, Fig. 24 is a magnet rotor of a rotary absolute magnetic encoder, Fig. 25 (d counter circuit and expansion circuit, Figs. 26 and 27) The figure is a timing chart, No. 28
29 and 29 are specific circuit examples of an electronic absolute encoder, FIG. 30 is a specific circuit example of a CW direction pulse generation circuit, FIG. 31 is an example of a CCW pulse generation circuit, and FIGS. 32 to 34. is a specific circuit example of an amplifier circuit. 1,...,8...Encoder waveform, 9.10
...terminal, 11.12...inverting amplifier circuit, 1
6゜14... Resistor, 15.16... Operational amplifier, 17.18... Negative input terminal, 19.20...
Resistor, 21... Earth, 22.23... Output terminal, 24.25... Feedback resistor, 26.
... Addition/amplification circuit, 27.28... Resistor, 2
9... Operational amplifier, 60... Connection point, 61
...Output terminal, 32...Feed bank resistor,
66゜64・Resistor, 35・Addition/amplification circuit, 36.37・Terminal, 68・Operation amplifier,
69... Connection point, 40... Output terminal, 41...
・Feedback resistance, 42.42...Resistance, 44
...terminal, 45...addition/amplification circuit, 46...
- Operational amplifier 47... Connection point, 48... Output terminal, 49... Feedback resistor, 50.
51... Resistor, 52... Operational amplifier, 56...
- Addition/amplification circuit, 54... connection point, 55...
Output terminal, 56... feedback resistor, 57.
~, 60... Code, 61... Norculus forming circuit for final stage encoder, 62... Waveform shaping circuit, 6
3... Up edge ◆ Down edge detection times m, 6
4.65...AND circuit, 66...Operational amplifier,
67...Feedback resistance, 68...-y
- base, 69...resistance, 70...oscillator, 7
1.72...D type flip-flop circuit, 76-
...Inno Kuichita, 74.75...NOR Gate,
76.77...OR gate, 78...timing chart, 79...dotted line, 80...electronic absolute encoder, 81...electronic absolute encoder circuit, 82...DC-DC converter , 86...Diode, 84...Resistor, 8
5... Voltage comparator, 86.87... Power supply battery, 88.89... Connection part, 90... Magnetoresistive element, 91... Amplifier circuit, 92... Output terminal, 96°94 ...Output terminal, 95...Color/recircuit, 96...Buffer circuit, 97...Output terminal, 98...Input terminal, 99...Diode, 10
0...error detection circuit, 101...diode)
”, 102...Rotary magnetic encoder, 1
03... Macnet rotor, 104... Shaft, 105... Alarm circuit, 106...
- Output terminal, 107... D-type flip-flop circuit, 108... Inverter, 109... Electronic alarm, biting error circuit, 110... Capacitor,
111...Resistor, 112...Integrator circuit,
113... Capacitor, 114... Resistor,
115... Integration circuit, 116... Comparator setting voltage, 117... Battery voltage, 118... Comparator output, 119,..., 123... Timing chart, 124... Flip-flop output,
125... Flange, 126... Rotary magnetic encoder case, 127... Screw, 1
28...Bearing holder, 129.130...Bearing, 131,132...Magnetic track, 166
...Magnetic encoder magnet 1, 164...Detection magnetization part,
165...Outer peripheral surface, 166...Gap,
167... Screw, 168... Magnetoresistive element mounting plate, 169... D-type flip-flop circuit, 1
40...Timing chart, 141-1.・・・
・, 146-6...IC, 142...pulse output timing chart in CW (CCW) direction, 1
46...I C141-6 6-bin output timing chart, 144...Z phase signal timing chart,
145... ζ output timing chart of flip-flop circuit, 146... Section, 147...
2 signal side terminal, 14B...Timing chart, 149...Rise of waveform, iso, tsi
. . . 4 multiplier circuit, 152 . . . CW pulse generation circuit, 156 . . . CCW pulse generation circuit. 1 fig. -------------------111 No. 27y No. 2? Figure 30 Figure Party-31 Figure Procedure Amendment July 1986/V-Japanese Patent Application No. 1986-61195003 No. 2 , Title of the invention Electronic absolute encoder 3, Relationship with the person making the amendment Patent applicant Address 4-9-4 Chuorinkan, Yamato City, Kanagawa Prefecture Name
Giken Co., Ltd. Shiko Giken 6, Contents of the correction (1) Insert r Figure 19-1 (a 1) to (d CW) J after "Figure 19" on page 36 of the Meikil book, line 17. (2) Figure 19 of the drawing is corrected as shown in the attached sheet.

Claims (1)

[Claims] The original oscillation A phase encoder signal with a predetermined peak value and this original oscillation A
Using an encoder that can obtain an original B-phase encoder signal with a predetermined peak value that is phase-shifted by 90 degrees in electrical angle from the phase encoder signal, add the above A-phase encoder signal and B-phase encoder signal at a set ratio. n (n is an integer greater than or equal to 1)
n-phase encoder signals are formed, and using the two selected encoder signals among the n-phase encoder signals formed above, a new n-phase encoder signal is generated between the selected two encoder signals in the same manner as above. An electronic absolute encoder that sequentially forms phase encoder signals.