JPS63310173A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize high integration and to reduce a propagation delay and to make this device high-speed, by forming an opening of a connection part, where a second-layered wiring layer of bilayer structure is connected with a diffusion layer on a substrate, more largely than the diffusion layer in the wiring direction of the second-layered wiring layer and next by using an isolation film to separate bilayer wirings. CONSTITUTION:A second-layered wiring layer 8 is separated on a selfmatching state from a first-layered wiring layer 7 (a gate electrode 3) by a side wall or a side wall insulation film 6 at a connection part where the layer 8 is connected with a diffusion layer 2 on a substrate 2. An opening part 9 is made larger than a boundary formed between an Si surface of the source or drain diffusion layer 2 and the side wall or the side wall insulation film 6, without a matching margin being taken. First and second layered wiring layers 7, 8 are separated also by an insulation film 5 except a conventional interlayer insulation film 10. Hence, high integration is realized and resistance is decreased to reduce a wiring delay, so that this device can be made high-speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention is applicable to semiconductor devices, especially LDD (11ght
The present invention relates to a MOS type semiconductor device having a lydoped drain structure and a method for manufacturing the same.

[Prior Art] Figs. 6 and 7 are explanatory diagrams of the structure and connection parts of a conventional MOS type semiconductor device, and Figs. e) Shown in the figure.

In the figure, 1 is a Si substrate, 2 is a diffusion layer, 2a is a region where the concentration of the diffusion layer is low, 2b is a region where the concentration of the diffusion layer is high, and 3
is a gate electrode, 4 is a gate insulating film, 5 is an interlayer insulating film, 6
7 is a side wall, 7 is a first wiring layer, 8 is a second wiring layer, and 9 is a connection portion (contact portion).

In general, in the LDD structure, the diffusion layer 2 consists of a low concentration region 2a and a high concentration region 2b, as shown in FIG. This refers to a structure in which diffusion does not spread below the membrane 4 and a channel length can be ensured.

In addition, in the LDD structure, the resistance of this portion is higher than that of the region 2b due to the region 2a, so that the electric field generated near the drain is relaxed, and this electric field causes the gate insulating film 4 on the region near the drain to be relaxed.
Insulated field effect transistor (hereinafter referred to as MISFET)
This suppresses the so-called hot carrier phenomenon, which is the deterioration of the characteristics of

In addition, regarding the semiconductor manufacturing process of LDD structure, Section 8(a)
The following is a description based on FIGS. 8(e) to 8(e).

First, as shown in FIG. 8(a), a gate electrode 3 is formed on the gate insulating film 4 by a conventional method, and then, as shown in FIG. 8(b), a low concentration diffusion region 2a is formed. 8th (c)
) As shown in the figure, an interlayer insulating film 6a for forming sidewalls is formed, and then an eighth (
d) As shown in the figure, a side wall 6 is formed, and finally, as shown in FIG. 8(e), a highly concentrated diffusion region 2b is formed.

By adopting the LDD structure as described above, the withstand voltage is improved, and the fluctuation in the threshold value due to the bias stress test is reduced by about two orders of magnitude compared to an element with a normal structure, thereby realizing a highly reliable transistor.

Furthermore, Japanese Patent Application Laid-Open No. 51-68776 discloses a field effect transistor (hereinafter referred to as MISFET) comprising a source region and a drain region of opposite conductivity type formed on a semiconductor substrate of negative conductivity type, wherein the drain region is A field effect transistor is disclosed that includes a central portion with high surface impurity concentration and a low impurity concentration portion surrounding the central portion. This adopts a double drain structure in order to alleviate the electric field generated near the drain region and prevent fluctuations in threshold voltage due to hot carriers. - Furthermore, in JP-A-60-194568, MISFET
In order to ensure a sufficient effective channel length of the MISFET, prevent short channel effects, and improve the degree of integration and operation time of the IC, we have developed By introducing respective impurities for forming a drain region or a source region formed by two semiconductor regions with impurity concentrations into the semiconductor substrate through the gate electrode and sidewalls provided on both sides thereof, An IC has been disclosed in which it is possible to suppress the source region or FL/drain region from wrapping around the region where the channel is to be formed, and to ensure a sufficient effective channel length.

Furthermore, Japanese Patent Application Laid-Open No. 61-20369 discloses a method for forming an LDD.

That is, this method includes the steps of forming a gate electrode on a semiconductor substrate surrounded by an element isolation region via a gate insulating film, and using the gate electrode as a mask to introduce impurities into the substrate to form a second conductivity type impurity. a step of forming a first impurity layer on the substrate, a step of depositing an insulating film over the entire surface, and removing this insulating film by reactive etching to leave it on the side surface of the gate electrode and its vicinity; A step of introducing impurities using the insulating film as a mask to form a second impurity layer of a second conductivity type to form source and drain regions, and forming a mask material layer having selective etching properties with respect to the insulating film on the entire surface. After forming, a step of selectively removing this mask material layer until a part of the remaining insulating film on the side surface of the gate electrode is exposed, and selectively removing the remaining insulating film using the remaining mask material layer, A semiconductor device comprising the steps of forming a gap between the gate electrode and the substrate, and introducing an impurity into the substrate through the gap to form a third impurity layer of a first conductivity type. This is a manufacturing method.

In this method, a third impurity layer (for example, a P-type layer) of the first conductivity type is formed only on the semiconductor substrate of the first conductivity type near the sidewalls of the gate electrode to suppress the extension of the depletion layer due to the drain voltage. By forming it partially, the contact portion of the P-type layer with the source and drain regions is reduced compared to the conventional method.

[Problems to be Solved by the Invention] Problems of the conventional MOS type semiconductor device as described above include:
The following points can be mentioned.

(1) As shown in FIG. 7, the connecting portion 9 between the two layers has conventionally formed a hole-shaped opening, but photolithography is required to prevent short-circuiting between the opening 9 and the metal of the first wiring layer 7. A combination margin a was required. This has been a bottleneck in achieving high integration, since the margin a is determined by the capability of the exposure device, and cannot simply be made smaller.

(2) For the same reason as in the previous section, for the combination allowance a,
The length of the second wiring layer 8 cannot be reduced, and the propagation delay due to this resistance makes it impossible to increase the speed.

(3) For the same reason as in the above (1), the parasitic diffusion capacitance is not reduced due to the combinational margin a, and high speed cannot be achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solve the above-mentioned problems.

[Means for solving the problems] The present invention is an MO8 type semiconductor device having an LDD structure,
It consists of a two-layer structure made of polysilicon, a high-melting point metal, or a combination of polycide made of these two layers, and the two
The opening of the connection between the second wiring layer of the layered structure and the source or drain diffusion layer formed on the substrate is larger than the source or drain diffusion layer in at least the wiring direction of the second wiring layer. formed, and the separation of the two-layer wiring is
A semiconductor device characterized in that it is formed by a sidewall of a D structure, a sidewall insulating film formed by etching an interlayer insulating film between the two-layer wiring, or an insulating film formed by both. This semiconductor device is characterized in that the thickness of the interlayer insulating film is 50 OA'' or more at the thinnest part.

The first method of manufacturing a semiconductor device of the present invention is to form a gate insulating film on the surface of a semiconductor substrate, and then form a gate electrode layer of a polycide layer consisting of a polysilicon layer, a high melting point metal layer, or a combination of the two. A first step of forming an insulating film on the entire surface of the gate electrode layer by heat treatment such as CVD or oxidation, a third step of forming a photoresist pattern on the insulating film, and a third step of forming a photoresist pattern on the insulating film. a fourth step of removing the photoresist by reactive etching, forming a gate electrode by reactive etching, and removing the photoresist; using the gate electrode as a mask, ions of the first conductivity type are implanted into the substrate to form a first conductivity type low concentration film; The fifth step is to form a layer, then the sixth step is to form an insulating film over the entire surface of the gate electrode by heat treatment such as CVD or oxidation, and the sixth step is to remove the entire surface by reactive etching to form a side wall on the side wall of the gate electrode. 7 steps, an 8th step of forming a first conductivity type high concentration layer on the substrate by ion implantation of the first conductivity type, then a 9th step of forming an insulating film by CVD or the like, and a predetermined portion on the insulating film. a tenth step of forming a photoresist pattern for forming an opening in the insulating film;
This method of manufacturing a semiconductor device is characterized by comprising an eleventh step of forming an opening in an interlayer connection portion, and a twelfth step of forming a second wiring layer.

In the second manufacturing method of the present invention, after forming a gate insulating film on the surface of a semiconductor substrate, the first step is to form a gate electrode layer of a polycide layer consisting of a polysilicon layer, a high melting point metal layer, or a combination of the two. step, by implanting ions of a first conductivity type into the substrate using the gate electrode as a mask.
a second step of forming a conductive type low concentration layer; then a third step of oxidizing the insulating film in a humid atmosphere at a temperature of 950° C. or less;
This method of manufacturing a semiconductor device is characterized in that it consists of 10 steps in which the 6th to 12th steps of the first manufacturing method are subsequently performed.

Next, in the third manufacturing method of the present invention, after forming a gate insulating film on the surface of a semiconductor substrate by a conventional method, a gate electrode layer of a polycide layer consisting of a polysilicon layer, a high melting point metal layer, or a combination of the two is formed. a first conductivity type low concentration layer is formed in the substrate by ion implantation of a first conductivity type, and a sidewall is formed on a side wall of the gate electrode.
step, then a second step of oxidizing the insulating film in a humid atmosphere at a temperature of 950° C. or less, a third step of forming a first conductivity type high concentration layer on the substrate by ion implantation of the first conductivity type, and then the above-mentioned step. This method of manufacturing a semiconductor device is characterized in that it consists of 7 steps in which the 9th to 12th steps of the first manufacturing method are performed successively.

[Operation] In the conventional method, the first-layer polysilicon wiring spacing is <1+2a as shown in FIG. Here, fI: size of the opening between polysilicon, a: alignment margin.However, in the method of the present invention, there is no need to provide alignment margin, and the minimum wiring spacing that is subject to processing limitations is sufficient as shown in FIG. .

For example, the line width and spacing of the first layer polysilicon are set to 1.
2 ura % 1.2μm, alignment margin a 1.
0 μrssl to 1.2. czm, conventional method 2Ω+2a = (1,2+1.OX 2)μm
-3.2 μm Inventive method: 1.2 μm dance, which is about half or less of the conventional method.

Since the semiconductor device of the present invention is constructed as described above, the chip area can be reduced, and the diffusion area of the source or drain diffusion layer is reduced accordingly, reducing parasitic capacitance. Similarly, the wiring length of the second layer polysilicon is shortened by this amount, the wiring resistance is reduced, the propagation delay is reduced, and high speed and low cost can be achieved.

Further, in the semiconductor device of the present invention, when polysilicon, a high melting point metal, or a combination of polycide consisting of two layers thereof is used for the gate electrode, dielectric breakdown is likely to occur because the surface is uneven.

Therefore, by setting the thickness of the insulating film between the two layers to 500 A'' or more at the thinnest portion, dielectric breakdown can be prevented.

Next, examples of the present invention will be described.

[Example] [Example 1] An example of the semiconductor device of the present invention is an N-channel MISF.
An example of application to an IC equipped with ET will be described.

FIG. 1 and FIG. 2 are explanatory diagrams of a semiconductor device of the present invention and a connecting portion thereof, respectively.

In the top view, the same symbols as those in Figures 6 to 8 are the same.
Or, since the corresponding part is shown, repeated explanation will be omitted.

In the figure, 10 is an interlayer insulating film, and 11 is a sidewall insulating film.

In FIG. 1, reference numeral 1 denotes a P- region formed on a P- type semiconductor substrate or an N- type semiconductor substrate made of silicon single crystal, as in FIG. 6, and constitutes an IC. 2
is a diffusion layer, 2a is a low concentration diffusion layer, 2b is a high concentration diffusion layer, 3 is a first wiring layer provided on a predetermined upper surface portion of the insulating film 4 and mainly used as a gate electrode, 4 5 is an insulating film provided on the top of the substrate 1 mainly used as a gate insulating film, 5 is an interlayer insulating film provided on the top of the substrate 1 to cover the semiconductor element, and 5 is an interlayer insulating film provided on the top of the substrate 1 to cover the semiconductor element. This is to electrically isolate the second wiring layer and the semiconductor element. 6 is mainly the first
Gate insulating film 4 at both ends of gate electrode portion 3 of the second wiring layer
This is an insulating sidewall provided by anisotropic etching on the upper part of the semiconductor region, which is formed at this time in order to further isolate a pair of semiconductor regions used as a drain region or a source region and to ensure a sufficient effective channel length. The diffusion layer 2a has a low concentration.

Further, reference numeral 11 denotes an insulating film on the side wall of the gate electrode 3 in the opening that makes contact between the first wiring layer 7 and the second wiring layer 8, and is formed on the upper part of the gate insulating film 4 by anisotropic etching. This sidewall insulating film has a first L
DD structure sidewall, second interlayer insulating film 10
a sidewall insulating film formed by the same mechanism as the sidewall when forming the opening (9 in FIG. 2) by anisotropic etching; and thirdly, by the combination of the first and second These differences are explained by the setting of the thickness of the interlayer insulating film 10 and the over-etching time when it is etched.

In other words, if the overetching time is long, the interlayer insulating film 10
However, the sidewalls of the gate electrode are also completely etched, and the sidewall insulating film 6 becomes only the sidewall of the LDD. Conversely, if the amount of etching is reduced, a third state is reached.

The second state shows the state when created in the process shown in Example 3, which will be described later.

In the semiconductor device of the present invention, as shown in FIG. 1, (1) the second wiring layer 8 is self-aligned by a sidewall or a sidewall insulating film 6 at a tangent to the diffusion layer 2 on the substrate; It is separated from the first wiring layer 7 (gate electrode 3).

(2) The opening 9 has no alignment margin larger than the boundary between the Si surface of the source or drain diffusion layer and the sidewall or sidewall insulating film 6.

(3) The first and second wiring layers 7 and 8 are separated by an insulating film 5 in addition to the conventional interlayer insulating film 10.

etc., which is different from conventional devices.

[Embodiment 2] Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described based on FIGS. 3(a) to 3(g).

In the figure, 12 is a photoresist pattern.

The method for manufacturing a semiconductor device of the present invention is as follows: (1) First, as shown in FIG. 3(a), after forming a gate insulating film 4 on the surface of a p-type semiconductor substrate 1, Gate electrode layer (first wiring layer 7) of a polycide layer consisting of a high melting point metal layer or a combination of the two
form.

(2) Next, as shown in FIG. 3(b), an insulating film 5 is formed on the gate electrode layer 7 by CVD. (In this case, the gate electrode 7 layer may be subjected to oxidation heat treatment, etc.) (3) As shown in FIG. 3(C), a photoresist pattern 12 is formed on the insulating film 5.

(4) As shown in Figure 3(d), reactive etching (R
The insulating film 5 is removed by etching using IE). Next, as shown in FIG. 3(e), a gate electrode 3 is similarly formed by reactive etching, and the photoresist pattern 12 is removed.

(5) As shown in FIG. 3(f), an n layer (low concentration diffusion layer 2a) is formed by implanting 31P+ ions into the substrate 1 using the gate electrode 3 as a mask.

(6) As shown in FIG. 3(g), an interlayer insulating film 6a is formed over the entire surface of the gate electrode 3 by CVD.

(7) As shown in FIG. 3(h), the entire surface is etched away by reactive etching to form sidewalls 6 on the sidewalls of the gate electrodes 3.

(8) Next, as shown in FIG. 3(i), 31P is placed on the substrate 1.
An n+ layer (an amorphous diffusion layer 2b) is formed using + or As ion implantation.

(9) As shown in FIG. 3(j), an interlayer insulating film 10 is formed by CVD.

(10) As shown in FIG. 3(k), the interlayer insulating film 10
A part of the interlayer insulating film 5 and the sidewall 6 under a predetermined portion of the wafer are removed by etching to form the sidewall 11 and the opening 9 of the connection portion.

Incidentally, at this time, the interlayer insulating film 5. Overetching amount when forming the sidewall 6 By optimizing the etching conditions for the first interlayer insulating film 10 and the opening 9 of the connection part, the insulating film 5 or between the first wiring layer 7 and the second wiring layer 8 is 11 is adjusted to 50 OA'' or more at the minimum of the membrane to prevent leakage between the two and ensure withstand voltage.

(11) Finally, as shown in FIG. 3(1), a second wiring metal layer 8 is formed by a conventional method.

By performing the above 12 steps, the structure of the semiconductor device of the present invention was realized.

[Embodiment 3] On the other hand, another method shown in FIGS. 4(a) to 4(C) will be described.

(1) First, as shown in FIG. 4(a), a gate insulating film is formed on the surface of a p-type semiconductor substrate, and then a gate electrode is formed of a polycide layer consisting of a polysilicon layer, a high melting point metal layer, or a combination of the two. A layer 3 is formed on the gate film 4 on the semiconductor substrate 1 .

(2) Next, as shown in FIG. 4(b), an n layer (low concentration diffusion layer 2a) is formed by implanting 31P'' ions into the substrate 1 using the gate electrode layer 3 as a mask.

(3) As shown in FIG. 4(C), the periphery of the gate electrode 3 is considerably larger than that of the Si substrate 1 by oxidation treatment in a humid atmosphere at a temperature of 950° C. or less (depending on temperature conditions,
A film (about 10 times larger) 6a can be formed.

(4) The following 7 steps (FIG. 3(f) and subsequent steps) of the manufacturing process (6) of Example 2 are performed.

The structure of the semiconductor device of the present invention can be realized even with the above 10 steps.

[Embodiment 4] Another method shown in FIGS. 5(a) to 5(d) will be described.

(1) As shown in FIG. 5(a), after forming a gate insulating film on the surface of an n-type semiconductor substrate by a conventional method, a polycide layer consisting of a polysilicon layer, a high melting point metal layer, or a combination of the two is formed. A gate electrode layer is formed, and sidewalls 6 are formed on the side walls of the gate electrode 3. Then, using the gate electrode 3 as a mask, an n layer (low diffusion layer 2a) is formed in the substrate 1 by implanting 31P+ ions.

(2) As shown in FIG. 5(b), the insulating film 5 is subjected to oxidation heat treatment in a humid atmosphere at a temperature of 950° C. or lower.

At this time, for the reason of the third embodiment, a large amount of the insulating film 5 can be formed only on the gate electrode 3.

(3) As shown in FIG. 5(c), an n layer (dense diffusion layer 2b) is formed by implanting 31P+ or As ions into the substrate 1.
form.

(4) Hereinafter, the following four steps [Figure 3(j) and following] of the manufacturing process (9) of Example 2 are performed.

The structure of the semiconductor device of the present invention was also realized in this paper consisting of the above seven steps.

The method for manufacturing a semiconductor device of the present invention includes: (1) Before forming the sidewall 6 in Examples 2 and 3 or after forming the sidewall 6 in Example 4, at least before forming the interlayer insulating film 10, the first layer An insulating film 5 of a predetermined thickness is formed on the wiring.

(2) In Examples 2 and 3, when forming the sidewall 6 and when etching the interlayer insulating film 10, in Example 4, when etching the interlayer insulating film 10,
Etching is performed so that the insulating film 5 on the first layer wiring remains, so that a final thickness of 500 Å or more remains.

This method differs from conventional methods in the following points.

In the embodiments of the present invention, an n-channel transistor formed on a p-type substrate has been described, but it goes without saying that the present invention can also be applied to an n-channel transistor formed on an n-type substrate.

[Effects of the Invention] By using the structure of the semiconductor device of the present invention, (1)
Since the alignment margin can be removed, the spacing between the first layer wirings becomes smaller, making it possible to achieve higher density.

(2) Since the length of the second layer wiring can be shortened, wiring resistance can be reduced and wiring delay can be reduced.

(3) Since the area of the diffusion layer could be reduced, the capacitance of the diffusion layer and the parasitic capacitance of the second layer wiring could be reduced, thereby realizing higher speed.

(4) The overall chip area became smaller, the number of effective chips in the same unit increased, and costs were reduced.

It had great effects, especially in increasing speed and reducing costs.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams of the semiconductor device and connection portion of the present invention, FIG. 3(a) to FIG. 3(g), and FIG. 4(a) to
4(C) and 5(a) to 5(C) are process explanatory diagrams of the manufacturing method in Examples 2.3 and 4 of the present invention, respectively, and FIG. 6 and 7 are conventional A structural explanatory diagram of a semiconductor device, an explanatory diagram of its connection part, and FIGS. 8(a) to 8(e) are explanatory diagrams of the manufacturing process of an LDD structure semiconductor. In the figure, 1 is a Si substrate, 2 is a diffusion layer, 2a is a low concentration diffusion layer, 2b is a dense diffusion layer, 3 and 7 are gate electrodes (first wiring layer), 4 is a gate insulating film, 5 and 10 1 is an interlayer insulating film, 6 is a sidewall, 6a is an insulating film for forming the sidewall, 8 is a second wiring layer, 9 is a connection part (contact part), 11 is a sidewall insulating film, 12 is a photoresist pattern It is. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) A MOS type semiconductor device having an LDD structure, consisting of a two-layer structure made of polysilicon, a high-melting point metal, or a combination of polycide made of these two layers, and a wiring layer as the second layer of the two-layer structure. In a semiconductor device having a structure in which a connection portion of a source or drain formed on a substrate with a diffusion layer is adjacent to a gate electrode portion of a first layer wiring, and the second layer wiring intersects the first layer wiring, an opening at a tangent between the second layer wiring and the source or drain diffusion layer is formed to be larger than the boundary between the sidewall of the LDD structure and the surface of the source or drain diffusion layer at least in the wiring direction;
and a side wall of the LDD structure or a side wall formed by etching the interlayer insulating film between the second layer wiring when forming the opening at the intersection of the gate electrode portion of the second layer wiring and the first layer wiring. A semiconductor device characterized in that the semiconductor device is separated by an insulating film or an insulating film formed by both. (2) The thickness of the insulating film between the two layers is 55 at the thinnest part.
The semiconductor device according to claim 1, characterized in that the angle is 00A° or more. (3) After forming a gate insulating film on the surface of the semiconductor substrate, a step of forming a gate electrode layer of a polysilicon layer, a high melting point metal layer, or a polycide layer consisting of a combination of the two, using CVD or oxidation on the gate electrode layer. A step of forming an insulating film on the entire surface by heat treatment such as, a step of forming a photoresist pattern on the insulating film, removing the insulating film by reactive etching, forming a gate electrode by the same reactive etching, and forming a photoresist pattern on the insulating film. a step of removing resist;
A step of forming a low concentration layer of a first conductivity type by implanting ions of a first conductivity type into the substrate using the gate electrode as a mask, a step of forming an insulating film over the entire surface of the gate electrode by heat treatment such as CVD or oxidation, and a reaction. A step of removing the entire surface by chemical etching and forming a sidewall on the side wall of the gate electrode, a step of forming a high concentration layer of the first conductivity type by implanting ions of the first conductivity type into the substrate, and then forming an insulating film by CVD or the like. a step of forming a photoresist pattern for forming an opening in a predetermined portion on the insulating film; a step of etching away a predetermined portion of the photoresist to form an opening in the connection portion between the two layers. A method for manufacturing a semiconductor device, comprising the following steps: forming a second wiring layer. (4) After forming a gate insulating film on the surface of the semiconductor substrate, a step of forming a gate electrode of a polysilicon layer, a high melting point metal layer, or a polycide layer consisting of a combination of the two, using the gate electrode as a mask, applying the gate electrode to the substrate. forming a first conductivity type low concentration layer by ion implantation of the first conductivity type;
Next, there is a step of oxidizing the insulating film in a humid atmosphere at a temperature of 950° C. or lower, a step of forming an insulating film over the entire surface of the gate electrode by heat treatment such as CVD or oxidation, and a step of removing the entire surface by reactive etching to remove the sidewalls. a step of forming a first conductivity type high concentration layer on the substrate by implanting ions of the first conductivity type into the substrate, a step of forming an insulating film by CVD or the like, and a step of forming a predetermined layer on the insulating film on the side wall of the gate electrode. a step of forming a photoresist pattern for forming an opening in a portion; a step of etching away a predetermined portion of the photoresist to form an opening in the connection portion between the two layers; forming a second wiring layer; 1. A method for manufacturing a semiconductor device, comprising the steps of: (5) After forming a gate insulating film on the surface of the semiconductor substrate, a gate electrode of a polysilicon layer, a high melting point metal layer, or a polycide layer consisting of a combination of the two is formed, and using the gate electrode as a mask, the gate electrode is a step of forming a sidewall on the sidewall, a step of forming a first conductivity type low concentration layer on the substrate by ion implantation of the first conductivity type;
A step of oxidizing the insulating film in a humid atmosphere at a temperature of 50° C. or lower, a step of forming a first conductivity type high concentration layer on the substrate by ion implantation of the first conductivity type, and then forming an insulating film by CVD or the like. a step of forming a photoresist pattern for forming an opening in a predetermined portion on the insulating film;
A method for manufacturing a semiconductor device, comprising the steps of etching away a predetermined portion of the photoresist to form an opening in the connection between the two layers, and forming a second wiring layer.