GB2151847A - Semiconductor device with metal silicide layer and fabrication process thereof. - Google Patents
Semiconductor device with metal silicide layer and fabrication process thereof. Download PDFInfo
- Publication number
- GB2151847A GB2151847A GB08431761A GB8431761A GB2151847A GB 2151847 A GB2151847 A GB 2151847A GB 08431761 A GB08431761 A GB 08431761A GB 8431761 A GB8431761 A GB 8431761A GB 2151847 A GB2151847 A GB 2151847A
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- Prior art keywords
- metal
- semiconductor device
- layer
- polysilicon layer
- doped region
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 62
- 239000002184 metal Substances 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 63
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 3
- 239000003990 capacitor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 238000010276 construction Methods 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
In a semiconductor device, e.g. two MOSFETS (QA, QB) in a semiconductor substrate 11, a metal silicide layer 19,20 connects the polysilicon gate 14 of one MOSFET (QA) to the drain or source region (17) of the other MOSFET (QB). The metal silicide layer is formed by converting part of a deposited metal layer, eg Mo, to the silicide in/situ. Other devices where the silicide can be used as an interconnection are a single MOSFET, bipolar transistors and resistors or capacitors. <IMAGE>
Description
SPECIFICATION
Semiconductor device and fabrication process thereof
The present invention relates to a semiconductor device and to a process for fabricating such a semiconductor device.
In a semiconductor device in which MIS fieldeffect transistors (MISFETS) are used as circuit components, it has been proposed to connect directly a polysilicon gate and a source or drain region doped with an impurity, in each of or between the
MISFETS. In the construction shown in Figure 1 of the accompanying drawings, for example, a polysili- con gate 2 of an n-channel MOSFET Q1 formed over a semiconductor substrate 1 is in direct contact with a portion of a source or drain region 3 of an n-channel MOSFET Q2.In order to effect this direct contact, a contact hole 5 is formed in part of an insulating film 4 over, for example, the source region of MOSFET Q2, and the source region 3 is doped with an n-type impurity to a high concentration through this hole to form an n 4 -type contact region 6, to which the gate 2 of the other n-channel
MOSFET Q1 is in direct contact.
Since the contact region 6 is formed by diffusion, its depth Xj is liable to be greater than that of the source region 3. As a result, a leak X1 is likely to occur between the n-type MOSFET Q1 and the contact region 6 which are arranged so that a field oxide film 7 is inserted between them, and a leak X2 is likely to occur because of e.g. a drop in Vth, between the contact region 6 and a drain region 9. It is considered that those leaks are the cause of deterioration of the characteristics of these transistors.
It is thought that in order to prevent these leaks, both the space a between the contact region 6 and a channel portion 8 and the width b of the fieldinsulating film 7 should be increased. To provide mask margins during the formation of the contact region 6, moreover, it is necessary to make the dimensions a and b larger. These restrictions on the dimensions a and b impede the "scale-down", i.e.
the miniaturisation, of the elements, raising the problem that a high degree of integration is difficult to achieve.
The present invention seeks to provide a device in which the contact region between e.g. a polysilicon gate and a source or drain of a field effect transistor does not suffer the defects of the prior art contacts.
To achieve this the contact region is a conductive material such as a metal silicide layer. The metal silicide layer contacts the elements in the substrate of the device. Such an arrangement may have the further advantage that the reliability of the contacts is improved.
The metal silicide layer contacts components of the device, which components may be part of the same semiconductor element, or may be two different elements. One may be a first impurity region in a semiconductor substrate (forming e.g. a source or drain region) with the other a polysilicon layer (forming e.g. a gate).
To achieve a device according to the present invention a metal silicate may be formed over a polysilicon gate and a region doped with an impurity to provide a connection between the polysilicon and the impurity-doped region. This makes the conventional contact region unneccessary, so that the instability of the characteristics and the restrictions on miniaturisation due to the contact region are eliminated.
By forming a metal film, turning it into its silicide and then removing residual metal, after the removal of the side walls of the polysilicon, moreover, the polysilicon and the impurity-doped region may be connected by the metal silicide.
Embodiments of the invention will now be described in detail, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a section through the construction of a connection which has been proposed prior to the present invention and has already been described;
Figure 2 is a section through a device being a first embodiment of the present invention;
Figure 3 is a top plan view of the embodiment of
Figure 2;
Figure 4 is a circuit diagram of the embodiment of
Figure 2;
Figures 5(A) to 5(FJ are sectional views illustrating the steps in the fabrication process of the first embodiment;
Figure 6 is a section through a device being a second embodiment of the present invention;
Figure 7 is a top plan view of the second embodiment of Figure 6; and
Figures 8(A) to (D) are sections illustrating steps in the fabrication process of the second embodiment.
Figures 2 to 4 show one embodiment of a semiconductor device of the present invention. As shown in Figures 2 and 3, n-channel MOSFETS QA and Q5 are arranged at right angles to each other on the main surface of a p-type semiconductor substrate 11, for example, and are isolated by a field insulating film 12. MOSFET QA has a polysilicon gate 14 formed on a gate-insulating film 13, and source and drain regions 15 which are doped with an n-type impurity. The other MOSFET, QB, similarly has a polysilicon gate 16 and source-drain regions 17. One end portion 14a of the polysilicon gate 14 of
MOSFET QA may extend over one of the sourcedrain regions 17 of MOSFET QB, and is connected to that source or drain region 17.More specifically, an end portion of the polysilicon gate 14 is arranged overthe source or drain region 17. One portion of a side wall 21, of silicon oxide, on the side of the polysilicon gate has been removed by, e.g., a process to form an opening 18 to the source or drain region 17 of MOSFET QB. The electrical connection between the source or drain region 17 and the polysilicon gate 14 is effected by metal silicide layers 19 and 20 which are formed so as to extend from the surface of the source or drain region 17 over the upper and side surfaces of the polysilicon gate 14.
Side walls 21 and 22 made of silicon oxide (SiO2) are formed over the side surfaces of the polysilicon gates 14 and 16, except for the contact. The device of this construction is formed into a circuit such as that shown in Figure 4. A metal silicide layer 23 connected to an element outside the Figure is formed on the upper face of the polysilicon gate 16.
The process of fabricating the device of this construction will now be described with reference to
Figures 5(A) to (F).
First of all, the field-insulating film 12 and the gate-insulating film 13 (200 A) made of silicon oxide are formed on the main surface of the p-type semiconductor substrate 11, e.g., of silicon as shown in Figure 5(A), and the polysilicon gates 14 and 16 are formed thereon by the deposition and patterning (or etching) of polysilicon. The n-type impurity ions are then implanted by a self-alignment method into the main surface of the semiconductor substrate 11, to form the source and drain regions 15 and 17. This forms the two MOSFETs QA and Os.
Next, as shown in Figure 5(B), silicon oxide films 21A and 22A (200A) are formed over the upper and side surfaces of the polysilicon gates 14 and 16 by thermal oxidation of silicon. The, after an SiO2 film (4000 - 5000A) has been formed over the whole surface by a CVD method, as shown in Figure 5(C), it is removed by reactive ion etching (RIE), or a similar method, from the upper surfaces of the polysilicon gates 14 and 16 and from the source and drain regions. During this time, the silicon oxide film is not removed from the sides of the polysilicon gates 14 and 16, to form the side walls 21 and 22. With regard to formation of the side walls, note Tsang, et al., "Fabrication of High-Performance LDDFET's With
Oxide Sidewall-Spacer Technology", inlEEE Transactions on Electron Devices, Vol. ED-29, No.4 (April 1982), pages 590-6, the contents of which is incorporated herein by reference.As shown in Figure 5(D), parts of the side walls 21 and 22 are also subjected to selective wet etching to etch away the side walls where wiring will be required using a resist film as a mask. In this embodiment, the part thus removed is a a portion of the side wall 21 of the polysilicon gate 14 of MOSFET QA. The side wall 21 of the polysilicon gate 14 is etched to form the connection opening 18 for the silicon gate 14 and the source or drain region 17. While the opening 18 is being formed, the portion of the side wall 21 of the polysilicon gate 14 which faces the opening 18 is etched away.
In addition, as shown in Figure 5(E), a metal such as molybdenum (Mo) or the like is deposited by sputtering over the whole surface to form a metal layer 24, (500 ) which is then subjected to a heat treatment in N2 gas. As a result, as shown in Figure 5(F), metal silicide layers 23, 19,20 and 25 (about 1000-2000 A) are formed over the portion at which the metal layer 24 and the silicon are in contact, i.e., the upper surface of the polysilicon gate 16, partially over the upper and side surfaces of the polysilicon gate 14, and over the source and drain regions 17, respectively. The metal silicide layer 20 formed over the side surfaces of the polysilicon gate 14, in particular, connect the polysilicon gate 14 and the source or drain region 17 directly.The gateinsulating film 13 is interposed between the polysilicon gate 14 and the source or drain region 17, but the metal silicide layers formed over these two parts are brought into connection with each other by a bridge action in which they protrude to provide a connection. Thus, the metal silicide can be formed in self-alignment with the side wall 21 and the field oxide 12; note Figure 3.
The metal layers are then etched so that the metal layer 24 which was not turned into the silicide is etched off to leave the metal silicide layers 23, 19,20 and 25 alone, completing the construction shown in
Figure 2. During this time, a mask can be used, formed overthe bridge portion, to block the etching of the metal over that portion, so that such portion, if needed for the connection at the bridge portion, may be retained between the polysilicon gate 14 and the source or drain region 17.
According to the semiconductor device with the construction described above, the metal silicide wiring step can be utilized unchanged to realize a direct contact between the polysilicon gate 14 and the source or drain region 17 by the metal silicide.
Because of the connection by the metal silicide layers 19 and 20, moreover, the connection resistance is low and the reliability is high.
The contact region is made redundant, and can be eliminated, to eliminate the danger of deterioration of the characteristics due to leaks between the
MOSFETs and the channel portions. As a result, as shown in Figure 2, the dimension as (0.3 Fm) between the opening 18 and the gate 16 and the dimension b1 (1 ,um) of the field insulating film 12 can both be reduced, to effect a high degree of integration of the elements.
Figures 6 and 7 show another embodiment of the present invention, in which a polysilicon gate 34 of one MOSFET Qc is connected directly to one of source-drain regions 35, i.e., a source region 35a in the present embodiment, by a metal silicide layer 36.
As shown in Figure 8(A), more specifically, the polysilicon gate 34 is formed on a p-type semiconductor substrate 31 over a gate-insulating film 33, and is then doped with an n-type impurity to form the source-drain regions 35. As shown in Figure 8(B), after a SiO2 film is formed by the CVD method, a silicon oxide film (side walls 37 at both sides) 37A is then formed on both the side surfaces and the upper surface of the polysilicon gate 34.
One side wall 37 of the polysilicon gate 34 is etched away through an opening, as shown in Figure 8(C). As further shown in Figure 8(C), the silicon oxide film on the upper surface of the polysilicon gate 34 and on the side wall 37 etched away has also been removed, e.g., by RIE. In addition, as shown in
Figure 8(D), a metal layer 39 is formed over the whole surface and is turned into its silicide, e.g., by heat treatment to form the metal silicide layer 36 extending over the source region 35a to one side surface and the upper surface of the polysilicon gate 34.
The metal layer is etched away to leave the metal silicide layer 36, and form the semiconductor construction shown in Figures 6 and 7.
Since the contact region can be omitted in the present embodiment as well, characteristic deterioration can be prevented to increase the reliability, and facilitate the fabrication.
Since the contact region can be omitted to remove the danger of deterioration of characteristics due to leaks, moreover, no masking margin need be considered when determining the dimensions of the metal silicide layer 36 of Figure 7, so that the dimensions can be reduced to enable miniaturization of the elements.
As can be appreciated from the foregoing, the following beneficial and advantageous results are obtained through use of the present invention:
(1) After the side walls of the polysilicon gates are removed, the metal silicide is formed overthe polysilicon gate and the source or drain region to provide connection therebetween. As a result, the contact region, which is necessary in the prior art, can be omitted to remove the deterioration of characteristics due to leaks, so that a highly reliable connection structure can be obtained.
(2) Because the contact region is not necessary, leaks between the MOSFETs and the channel portions do not occur, so that the dimensions of the opening over the source or drain region and of the field-insulating film can be reduced, enabling the miniaturization of the elements to provide a high degree of integration.
(3) Since the metal silicide steps of the prior art, other than the step of etching away the side walls of the polysilicon gate, can be used almost unchanged, the process can be simplified to facilitate fabrication.
(4) Since there is no necessity for a contact region, the source and drain regions can be made shallower to suit them for "scale-down".
Although the invention has been described above in connection with embodiments thereof, it should not be limited to these embodiments but can be modified in various ways without departing from the gist thereof. For example, the metal of the metal silicide need not be limited to Mo alone; platinum (Pt), tungsten (W), titanium (Ti) or tantalum (Ta) can be used therefor. Moreover, the silicide pattern may be changed as required, in accordance with the circuit.
The description above is directed mainly to the case in which the present invention is applied to a connection between the gate and the source or drain region of a MOSFET, providing the background of the field of application thereof. However, the present invention is not limited thereto, but can be applied to a bipolar transistor or any other circuit wiring, e.g., to the case in which, e.g., polysilicon is used as a wiring material and is connected to an impuritydoped region such as a resistor or capacitor.
The present invention also has application in applying lightly doped Drain/Source Field Effect
Transistor (LDDFET) structure to switching MOS
FETs of memory cells of a DRAM or a SRAM.
While I have shown and described various embodiments in accordance with the present invention, it is understood that the same is not limited thereto, but is susceptible of numerous changes and modifications as known to those skilled in the art.
Claims (24)
1. A semiconductor device comprising:
a) a semiconductor substrate having a first impurity doped region of a semiconductor element in a surface region thereof;
b) a polysilicon layer, which is part of the or another semiconductor element, over the semiconductor substrate; and
c) a metal silicide layer extending from the first impurity doped region to the polysilicon layer directliy to connect electrically the first impurity doped region and the polysilicon layer.
2. A semiconductor device according to claim 1, wherein the polysilicon layer and the first impurity doped region overlap and are separated from each other by an insulating layer on the semiconductor substrate.
3. A semiconductor device according to claim 1 or claim 2, further comprising:
d) a field oxide film on the semiconductor substrate;
e) a thin insulator film on the semiconductor substrate; and
f) a side wall of insulator material at the sides of the polysilicon layer except for portions of the sides in contact with the metal silicide layer;
wherein the polysilicon layer is on said thin insulator film and the field oxide film; wherein said first impurity doped region is in self-alignment with the polysilicon layer and the field oxide film; and wherein the metal silicide layer is in self-alignment with the field oxide film and the side wall.
4. A semiconductor device according to any one of claims 1 to 3 wherein the first impurity doped region is a source or drain region of a first field effect transistor and the polysilicon layer is a gate electrode of a second field effect transistor.
5. A semiconductor device according to claim 4, wherein the first and second field effect transistors are MISFETS.
6. A semiconductor device according to claim 4, wherein the first and second field effect transistors are MOSFETS.
7. A semiconductor device according to claim 6, wherein the first and second MOSFETS are substantially at right angles to each other.
8. A semiconductor device substantially as herein described with reference to and as illustrated in
Figures 2 to 5 or Figures 6 to 8 of the accompanying drawings.
9. A process of fabricating a semiconductor device, comprising the steps of:
a) forming at least one element of the semiconductor device, the at least one element including an impurity doped region in a surface region of a semiconductor substrate and a polysilicon layer extending over the semiconductor substrate;
b) forming a metal film, of a metal which forms a silicide, continuously extending from the polysilicon layer to the impurity doped region; and
c) selectively turning the metal layer into the silicidethereoftoform a metal silicide layer over the polysilicon layer and the impurity doped region.
10. A process according to claim 9, wherein, after step c), portions of the metal layer not turned into the silicide are removed by etching.
11. A process according to claim 9 or claim 10, wherein the polysilicon layer has insulating side walls at the sides thereof, and wherein, prior to forming the metal layer, portions of the insulating side walls closest to the impurity doped region are removed, whereby the metal layer is formed directly contacting the sides of the polysilicon layer.
12. A process according to any one of claims 9 to 11, wherein there are at least one plurality of elements, with one of the elements including the impurity doped region and another of the elements including the polysilicon layer.
13. A process according to any one of claims 9 to 11,wherein there is a single element including both the impurity doped region and the polysilicon layer.
14. A process of fabricating a semiconductor device substantially as any one herein described with reference to Figures 2 to 8 of the accompanying drawings.
15. An electrical connection between components of elements of a semiconductor device, the semiconductor device being formed using a semiconductor substrate, comprising:
(a) a first component of the semiconductor device in a surface region of the substrate;
(b) a second component of the semiconductor device including a polysilicon layer over the substrate; and
(c) an electrical connection directly electrically connecting the first and second components, the electrical connection being made of a metal silicide.
16. A device according to claim 15, wherein the polysilicon layer is on an insulating layer on the semiconductor substrate.
17. A device according to claim 16 or claim 16, wherein the first component is an impurity-doped region extending to the surface of the substrate.
18. A device according to any one of claims 15 to 17, wherein the first component is a source or drain region of a MISFET, and the second component is a gate electrode of the same or another MISFET.
19. An electrical connection according to any one of claims 15 to 18, wherein the side surfaces of the polysilicon layer are covered with an insulating layer except for the portions of the side surfaces of the polysilicon layer contacting the metal silicide.
20. An electrical connection according to any one of claims 15 to 19, wherein a part of the second component extends over a part of the first component.
21. A method of forming an electrical connection between two components of elements in a semiconductor device, the semiconductor device being formed in part in a semiconductor substrate, comprising the steps of:
(a) forming a metal layer, of a metal which forms a metal silicide, extending continuously at least from the first component to the second component so that it contacts both components; and
(b) subjecting the metal layer to a heat treatment to react the metal of the metal layer with material of the first and second components contacting the metal layer to form the metal silicide, whereby the metal silicide forms at least part of an electrical connection between the two components.
22. A method according to claim 21, wherein the first component is an impurity-doped region formed in a surface region of the semiconductor substrate, and the second component is a polysilicon layer formed over the semiconductor substrate.
23. A method of forming an electrical connection according to claim 21 or claim 22, wherein the first and second components are spaced from each other, and wherein the heat treatment is carried out so that the metal of the metal layer forms the metal silicideto cause the metal silicide in contactwiththe first component and the metal silicide in contact with the second component to extend across the space between the first and second components.
24. Product formed by the process of any one of claims 21 to 23.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58241963A JPS60134466A (en) | 1983-12-23 | 1983-12-23 | Semiconductor device and manufacture thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8431761D0 GB8431761D0 (en) | 1985-01-30 |
| GB2151847A true GB2151847A (en) | 1985-07-24 |
| GB2151847B GB2151847B (en) | 1987-11-25 |
Family
ID=17082176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08431761A Expired GB2151847B (en) | 1983-12-23 | 1984-12-17 | Semiconductor device with metal silicide layer and fabrication |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS60134466A (en) |
| KR (1) | KR850005138A (en) |
| GB (1) | GB2151847B (en) |
| HK (1) | HK41890A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2177255A (en) * | 1985-06-28 | 1987-01-14 | Northern Telecom Ltd | VLSI MOSFET circuits using refractory metal and/or refractory metal silicide |
| GB2180991A (en) * | 1985-08-28 | 1987-04-08 | Mitsubishi Electric Corp | Silicide electrode for semiconductor device |
| US4729969A (en) * | 1985-09-05 | 1988-03-08 | Mitsubishi Denki Kabushiki Kaisha | Method for forming silicide electrode in semiconductor device |
| WO1989011732A1 (en) * | 1988-05-24 | 1989-11-30 | Micron Technology, Inc. | Tisi2 local interconnects |
| WO1989011733A1 (en) * | 1988-05-24 | 1989-11-30 | Micron Technology, Inc. | Alpha shielded tisi2 local interconnects |
| US5053349A (en) * | 1988-06-16 | 1991-10-01 | Kabushiki Kaisha Toshiba | Method for interconnecting semiconductor devices |
| EP0450375A1 (en) * | 1990-04-02 | 1991-10-09 | National Semiconductor Corporation | Interconnect and method of manufacture for semiconductor devices |
| EP0463373A2 (en) * | 1990-06-29 | 1992-01-02 | Texas Instruments Incorporated | Local interconnect using a material comprising tungsten |
| EP0463458A1 (en) * | 1990-06-28 | 1992-01-02 | International Business Machines Corporation | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| EP0497595A2 (en) * | 1991-01-31 | 1992-08-05 | STMicroelectronics, Inc. | Local interconnect for integrated circuits |
| US5223456A (en) * | 1990-05-02 | 1993-06-29 | Quality Semiconductor Inc. | High density local interconnect in an integrated circit using metal silicide |
| US5231042A (en) * | 1990-04-02 | 1993-07-27 | National Semiconductor Corporation | Formation of silicide contacts using a sidewall oxide process |
| US5254874A (en) * | 1990-05-02 | 1993-10-19 | Quality Semiconductor Inc. | High density local interconnect in a semiconductor circuit using metal silicide |
| US5424572A (en) * | 1990-04-02 | 1995-06-13 | National Semiconductor Corporation | Spacer formation in a semiconductor structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0520771A (en) * | 1991-07-11 | 1993-01-29 | Mitsubishi Electric Corp | Array type disk device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4128670A (en) * | 1977-11-11 | 1978-12-05 | International Business Machines Corporation | Fabrication method for integrated circuits with polysilicon lines having low sheet resistance |
| GB2019091A (en) * | 1978-04-11 | 1979-10-24 | Siemens Ag | Semiconductor store |
| GB2038552A (en) * | 1978-12-29 | 1980-07-23 | Western Electric Co | Composite conductor structure for a semiconductor device |
| GB2083284A (en) * | 1980-08-27 | 1982-03-17 | Philips Nv | Metal silicide on polycrystalline silicon layers |
| GB2087148A (en) * | 1980-11-07 | 1982-05-19 | Hitachi Ltd | Composite conductor structure for semiconductor devices |
-
1983
- 1983-12-23 JP JP58241963A patent/JPS60134466A/en active Pending
-
1984
- 1984-12-17 GB GB08431761A patent/GB2151847B/en not_active Expired
- 1984-12-20 KR KR1019840008170A patent/KR850005138A/en not_active Application Discontinuation
-
1990
- 1990-05-31 HK HK418/90A patent/HK41890A/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4128670A (en) * | 1977-11-11 | 1978-12-05 | International Business Machines Corporation | Fabrication method for integrated circuits with polysilicon lines having low sheet resistance |
| GB2019091A (en) * | 1978-04-11 | 1979-10-24 | Siemens Ag | Semiconductor store |
| GB2038552A (en) * | 1978-12-29 | 1980-07-23 | Western Electric Co | Composite conductor structure for a semiconductor device |
| GB2083284A (en) * | 1980-08-27 | 1982-03-17 | Philips Nv | Metal silicide on polycrystalline silicon layers |
| GB2087148A (en) * | 1980-11-07 | 1982-05-19 | Hitachi Ltd | Composite conductor structure for semiconductor devices |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2177255A (en) * | 1985-06-28 | 1987-01-14 | Northern Telecom Ltd | VLSI MOSFET circuits using refractory metal and/or refractory metal silicide |
| GB2177255B (en) * | 1985-06-28 | 1989-04-26 | Northern Telecom Ltd | Vlsi mosfet circuits using refractory metal and/or refractory metal silicide |
| GB2180991A (en) * | 1985-08-28 | 1987-04-08 | Mitsubishi Electric Corp | Silicide electrode for semiconductor device |
| US4729969A (en) * | 1985-09-05 | 1988-03-08 | Mitsubishi Denki Kabushiki Kaisha | Method for forming silicide electrode in semiconductor device |
| WO1989011732A1 (en) * | 1988-05-24 | 1989-11-30 | Micron Technology, Inc. | Tisi2 local interconnects |
| WO1989011733A1 (en) * | 1988-05-24 | 1989-11-30 | Micron Technology, Inc. | Alpha shielded tisi2 local interconnects |
| US5053349A (en) * | 1988-06-16 | 1991-10-01 | Kabushiki Kaisha Toshiba | Method for interconnecting semiconductor devices |
| US5231042A (en) * | 1990-04-02 | 1993-07-27 | National Semiconductor Corporation | Formation of silicide contacts using a sidewall oxide process |
| US5107321A (en) * | 1990-04-02 | 1992-04-21 | National Semiconductor Corporation | Interconnect method for semiconductor devices |
| EP0450375A1 (en) * | 1990-04-02 | 1991-10-09 | National Semiconductor Corporation | Interconnect and method of manufacture for semiconductor devices |
| US5424572A (en) * | 1990-04-02 | 1995-06-13 | National Semiconductor Corporation | Spacer formation in a semiconductor structure |
| US5223456A (en) * | 1990-05-02 | 1993-06-29 | Quality Semiconductor Inc. | High density local interconnect in an integrated circit using metal silicide |
| US5254874A (en) * | 1990-05-02 | 1993-10-19 | Quality Semiconductor Inc. | High density local interconnect in a semiconductor circuit using metal silicide |
| EP0463458A1 (en) * | 1990-06-28 | 1992-01-02 | International Business Machines Corporation | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| US5453400A (en) * | 1990-06-28 | 1995-09-26 | International Business Machines Corporation | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| US5672901A (en) * | 1990-06-28 | 1997-09-30 | International Business Machines Corporation | Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits |
| EP0463373A2 (en) * | 1990-06-29 | 1992-01-02 | Texas Instruments Incorporated | Local interconnect using a material comprising tungsten |
| EP0463373A3 (en) * | 1990-06-29 | 1992-03-25 | Texas Instruments Incorporated | Local interconnect using a material comprising tungsten |
| EP0497595A2 (en) * | 1991-01-31 | 1992-08-05 | STMicroelectronics, Inc. | Local interconnect for integrated circuits |
| EP0497595A3 (en) * | 1991-01-31 | 1992-09-30 | Sgs-Thomson Microelectronics, Inc. | Local interconnect for integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| HK41890A (en) | 1990-06-08 |
| KR850005138A (en) | 1985-08-21 |
| GB2151847B (en) | 1987-11-25 |
| GB8431761D0 (en) | 1985-01-30 |
| JPS60134466A (en) | 1985-07-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19941217 |