JPS63308366A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the voltage dependency of the capacity value of a capacitor as well as to make it possible to use the capacitor in a highly precise circuit by a method wherein the capacitor is constituted by antiparallel connection of first and the second MOS capacitors. CONSTITUTION:The title semiconductor integrated circuit has the capacitor on which the first MOS capacitor 13, containing the gate insulating film 10-1 provided on the surface of a p-type silicon semiconductor substrate 1, the conducting film 11-1 consisting of polycrystalline silicon provided on the gate insulating film 10-1, and n<+> type regions 8-1 and 8-2 selectively provided on the part adjoining to the section directly under the conductive film 11-1 on the surface of the p-type semiconductor substrate 1, and the second MOS capacitor 14 (consisting of a gate insulating film 10-2, a conductive film 1102 and n<+> type regions 8-3 and 9-4) of substantially same shape as the capacitor 13 are connected in parallel in different directions with each other. As a result, the effect of the bias voltage in the neighborhood of zero point can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit with a high MO8 capacity.

[Traditional seconds]

It has been known that the capacitance value of MO8 and kd changes depending on the potential difference between the two electrodes. Therefore, rsMO is applied to switched capacitor circuits (hereinafter referred to as SC circuits) such as switched capacitor filters where this capacitance changes and σ becomes a problem.
8 capacitance is not used, but the capacitance between 2# polycrystalline silicon electrodes 3 and 4 as shown in Figure 3.

Alternatively, the capacitance between the polycrystalline silicon 116 and the aluminum electrode 7 as shown in FIG. 4 was used.

[Problem that the invention seeks to solve]

The above-mentioned conventional semiconductor integrated circuit uses a capacitance between two layers of polycrystalline silicon electrodes or a capacitance between a polycrystalline silicon electrode and an aluminum electrode as a capacitor element, and therefore has the disadvantage that the process is complicated. or.

In the latter case, since the interlayer insulating film between the polycrystalline silicon electrode used as a dielectric and the aluminum electrode becomes thick, there is also a drawback that the capacitance value becomes small (and the t'i' product becomes low).

[Means to resolve issues]

The semiconductor integrated circuit of the present invention includes a gate insulating film provided on the surface of the first conductive type semiconductor substrate, a conductive film provided on the gate insulating film, and a fourth insulating film provided on the surface of the fourteenth conductive type semiconductor substrate. a second conductivity type region selectively provided adjacent to the lower part of the mountain, and the MO8O8 capacitors of the substantially PII-shaped vessel 1, the second MO8 capacitors, and the 9 capacitors are connected in parallel in mutually different directions. It has a capacitive element consisting of:

〔Example〕

Next, an embodiment of the present invention will be described and explained with reference to the drawings.

&1 Figure σ is a sectional view of a cow wrap tip showing the main parts of the first embodiment of the present invention, and Figure 2 is a circuit diagram.

In this embodiment, σ is a p-type semiconductor substrate made of silicon.
11[The gate provided at T is 10-1.

A conductive film 11-1 made of polycrystalline silicon provided on the gate P edge 144110-1 and an
A first MO8 capacitor 13 including a + type region 81.8-2 and a second MO8 capacitor 14 having substantially the same shape as the first MO8 capacitor 13 (gate P edge film 10-2, conductive film 11-2#) fl+
The mold regions 8-3 and 8-4 have capacitive elements connected in parallel in different directions.

Then the first one. A channel exists on the surface of each of the second MO8 capacitors when the applied voltage is 00. In other words, it is a deprevuzine type. Furthermore, 8-1 and 8-2.8-3 and 8-4
ri may be connected to each other to form a closed region, or may be connected by an aluminum electrode. Again 1
Although not shown, the aluminum electrode 12-2 connected to the fourth electrode 11-1 is connected to the aluminum 1 pole 12-3 connected to the n+ type region 83, and similarly the aluminum electrode 12-2 connected to the Kn+ type region 8-1. 4 to the aluminum electrode 12-1 connected to
Albanium electrode 12- connected to Yi film 11-2
4 is connected.

Taking the first MO8 answer amount l3 of this embodiment as an example, MO8O
8. Explain volume-pressure dependence.

The MOS capacity is #*character #, and the conductive film 11-1 has a proper capacitance Coxri 'ox'.

Cox = - Ox where t6zri gate insulation [permittivity of 10-1, 6
0 is expressed by the dielectric constant of vacuum, tOxtrJ, which is the thickness of the gate insulating film.

However, when a negative voltage is applied, holes gather on the surface and become depleted. In this case, the gate insulation capacitance C
A depletion layer capacitance C+> is inserted in series with ox, and the capacitance decreases as the voltage V applied to the conductive film 11-1 changes from 0 to a valve. When a negative and positive voltage is further applied, the surface is finally inverted to a p-type. When this happens, the depletion r＠does not change significantly and remains at a nearly constant value.

FIG. 5 is a C-■ characteristic diagram showing the voltage dependence of the MO8 capacitance explained above.

FIG. 6 shows the voltage dependence of the capacitive element of the first embodiment.
−■Characteristic diagram.

Since the C-■ characteristic of the first MO8 capacitor is the same as that shown in FIG. 5, it is a concave line represented by a dashed line. Next, the C-7 curve of the first MO8 capacity is inverted, centering on the CV% riO point of the second M08 capacity of opposite polarity, that is, the curve is represented by a two-dot chain line. Therefore, the total capacity is symmetrical about the zero point, as shown by the solid line. This greatly reduces the influence of bias voltage near the 0 point.

FIG. 7 is a circuit diagram of the main part of the second embodiment.

This is a case where a plurality of unit capacitances are used so that the relative ratio of capacitances is not affected by pattern overetching during diffusion. Unit volume - Jl (15-1 to 15-5) to 5
The MO8O8 capacitor of Wl is connected in parallel, and further has a second MO8 capacitor in which five unit capacitors are connected in parallel with the first MO8O8 capacitor with opposite polarity. The first one. The second MO8 capacitors are connected in parallel to form one capacitive element.

The unit volumes 1it15-1 to 15-10 have substantially the shape and material of -J-.

Similar to the first embodiment, this capacitance configuration greatly reduces the influence of the bias voltage near the 0 point, as shown in FIG.

Note that the number of unit capacities is not limited to 10, and may vary depending on the manufacturing process and capacity. You can choose as appropriate considering the accuracy of the two children.

〔Effect of the invention〕

As explained above, the present invention has the first aspect. By connecting the second MO8 capacitor in antiparallel to form a capacitive element, the voltage dependence of the capacitance value can be significantly reduced compared to the conventional method. #! This has the effect of reducing the cost of integrated circuits or improving the degree of integration.

[Brief explanation of drawings]

1 and 2 are a sectional view and a circuit diagram of a conductor chip showing the main parts of the first embodiment of the present invention, respectively, and FIGS. A cross-sectional view of the cow conductor chip showing the main part of the second conventional example, Fig. 5 riMO8h amount 0C-V
FIG. 6 is a C-■ characteristic diagram of the capacitive element of the first embodiment, and FIG. 7 is a circuit diagram of the main part of the second embodiment of the present invention. 1...P-type semiconductor substrate, 2...Interlayer insulating film, 3゜4...Polycrystalline silicon electrode%5-1
．． 5-2... Aluminum electrode, 6...
・Polycrystalline silicon electrode. 7... Aluminum electrode, 8-1 to 8-4...
...N+ type region 9...Field insulating film, 10-1.10-2...Gate insulating film, 11
-i, 11'-2... Conductive film %12-1~
12-4... Aluminum electrode, 13...
...First MO8O8 Capacity 4...Second MOS
Capacity, 15-1 to 15-10...Unit capacity. Agent Patent Attorney Uchihara Oto No. 7 [! 1 Month ZIID Figure 3 燉熁り KaD Electric Tile V 5th Drawing P La Voltage 14 6 Figure 7

Claims (1)

[Claims] a gate insulating film provided on the surface of the first conductivity type semiconductor substrate; a conductive film provided on the gate insulating film;
a second conductivity type region selectively provided immediately below the conductive film on the surface of the conductive type semiconductor substrate, the first MOS capacitor and the second MOS capacitor having substantially the same shape; A semiconductor integrated circuit characterized by having capacitive elements connected in parallel in different directions.