JP2563456B2 - MIS type capacitive element - Google Patents
MIS type capacitive elementInfo
- Publication number
- JP2563456B2 JP2563456B2 JP63070064A JP7006488A JP2563456B2 JP 2563456 B2 JP2563456 B2 JP 2563456B2 JP 63070064 A JP63070064 A JP 63070064A JP 7006488 A JP7006488 A JP 7006488A JP 2563456 B2 JP2563456 B2 JP 2563456B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitance
- type
- semiconductor
- mis
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路、特にリニア回路等で用い
られる対称な回路形式の下で使用するのに好適なMIS形
半導体容量素子に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS semiconductor capacitor suitable for use in a semiconductor integrated circuit, particularly a symmetrical circuit format used in a linear circuit or the like.
従来の技術 半導体集積回路内へ集積化される容量素子の一つとし
て、MIS形容量素子が知られている。2. Description of the Related Art A MIS type capacitive element is known as one of capacitive elements integrated in a semiconductor integrated circuit.
第3図は、バイポーラ形半導体集積回路内に作り込ま
れるMIS形容量素子の構造を示す図であり、P形シリコ
ン基板1の上に形成したN型エピタキシャル層をP+形絶
縁分離領域2で島状に分離して形成したN型エピタキシ
ャル島領域3の中に、この領域よりも不純物濃度の高い
N型拡散領域4ならびに高不純物濃度のN型コンタクト
拡散領域5を作り込み、さらに、N型拡散領域4の表面
を覆う二酸化シリコン膜6の上に一方の電極となる金属
層7を形成するとともに、N型コンタクト拡散領域5に
他方の電極となる金属層8を付設した構造となってい
る。なお、9は高不純物濃度のN型埋込領域である。こ
のMIS型容量素子では二酸化シリコン膜6を誘電体層と
する容量が形成される。FIG. 3 is a diagram showing the structure of an MIS type capacitor element built in a bipolar type semiconductor integrated circuit, in which an N type epitaxial layer formed on a P type silicon substrate 1 is formed as a P + type insulating isolation region 2. In the N-type epitaxial island region 3 formed separately in an island shape, an N-type diffusion region 4 having a higher impurity concentration and an N-type contact diffusion region 5 having a higher impurity concentration than this region are formed, and further, an N-type A metal layer 7 to be one electrode is formed on the silicon dioxide film 6 covering the surface of the diffusion region 4, and a metal layer 8 to be the other electrode is additionally provided to the N-type contact diffusion region 5. . Reference numeral 9 is an N-type buried region having a high impurity concentration. In this MIS type capacitance element, a capacitance having the silicon dioxide film 6 as a dielectric layer is formed.
発明が解決しようとする課題 このような構造のMIS型容量素子では、電極8の側に
N型拡散領域4によって付与される直列抵抗とP型基板
5との間に形成されるPN接合によって付与される接合容
量が付加されて非対称性を示す。このため、リニア信号
処理で多用される対照的な回路(例えば、差動増幅回
路)に従来のMIS型容量素子を用いると、PN接合による
寄生容量が一方の信号ラインに付与され、他方の信号ラ
インには付与されない状態となり、他方の信号ラインで
所定の周波数特性が得られても、一方の信号ラインの周
波数特性が劣化して、信号処理回路の対称性が損なわれ
るという欠点を有していた。In the MIS type capacitance element having such a structure, it is provided by the PN junction formed between the P type substrate 5 and the series resistance provided by the N type diffusion region 4 on the electrode 8 side. The added junction capacitance exhibits asymmetry. For this reason, when a conventional MIS type capacitive element is used in a contrasting circuit often used in linear signal processing (for example, a differential amplifier circuit), a parasitic capacitance due to a PN junction is given to one signal line and the other signal is applied. Even if a predetermined frequency characteristic is obtained in the other signal line, the frequency characteristic of one signal line deteriorates and the symmetry of the signal processing circuit is impaired. It was
本発明は、上記の問題点の排除を意図するもので、両
電極に付与される寄生容量の対称性を図ることを目的と
する。The present invention is intended to eliminate the above-mentioned problems, and an object thereof is to achieve symmetry of parasitic capacitances applied to both electrodes.
課題を解決するための手段 本発明のMIS型容量素子は、平面形状の面積がほぼ等
しい一導電型の第1,第2の島領域を逆導電型の半導体基
板に形成し、上記第1,第2の島領域内に夫々一導電型の
第1,第2の拡散領域を形成し、上記第1,第2の拡散領域
上の絶縁膜の上に夫々金属電極を形成し、上記第1の拡
散領域にコンタクトする半導体側電極ならびに上記第2
拡散領域にコンタクトする半導体側電極を形成して、第
1容量および第2容量を作り込み、上記第1容量の金属
電極と上記第2容量の半導体側電極を接続し、上記第2
容量の金属電極と上記第1容量の半導体側電極を接続し
た構成となっている。Means for Solving the Problems In the MIS type capacitance element of the present invention, first conductivity type first and second island regions having substantially the same planar area are formed on a semiconductor substrate of opposite conductivity type, and First conductivity type first and second diffusion regions are formed in the second island region, and metal electrodes are formed on the insulating films on the first and second diffusion regions, respectively. Side electrode contacting the diffusion region of
A semiconductor-side electrode that contacts the diffusion region is formed to form a first capacitor and a second capacitor, the metal electrode of the first capacitor and the semiconductor-side electrode of the second capacitor are connected to each other, and
The configuration is such that the metal electrode of the capacitor is connected to the semiconductor-side electrode of the first capacitor.
作用 この構成によれば、半導体基板と島領域とPN接合によ
る寄生容量は半導体側電極に必ず付与されるが、第1容
量と第2容量を逆向きにして並列接続するので、MIS型
容量素子の両電極の寄生容量を対称にすることができ、
例えば、対称的な回路に接続した場合、2つの信号ライ
ンの一方のみの周波数特性を劣化させるのではなく、同
等に劣化させるので、信号ライン間の位相は対称的に変
化しない。Operation According to this structure, the parasitic capacitance due to the semiconductor substrate, the island region, and the PN junction is surely given to the semiconductor-side electrode, but since the first capacitance and the second capacitance are reversed and connected in parallel, the MIS-type capacitance element The parasitic capacitance of both electrodes can be made symmetrical,
For example, when connected to a symmetrical circuit, the frequency characteristic of only one of the two signal lines is not deteriorated but is deteriorated equally, so that the phase between the signal lines does not change symmetrically.
実 施 例 以下に図面を参照して本発明のMIS型容量素子につい
て詳しく説明する。Example Hereinafter, the MIS type capacitance element of the present invention will be described in detail with reference to the drawings.
第1図は、バイポーラ集積回路内に作り込まれた本発
明のMIS型容量素子の形状を示す平面図であり、2個のM
IS型容量素子C1とC2が並設されている。これらのMIS型
容量素子C1,C2のX−X線およびY−Y線に沿った断面
構造は、第3図で示した構造と同じである。ところで、
本発明のMIS型容量素子では、第1容量C1と第2容量C2
の周囲はP+型絶縁分離領域2によって包囲され、互いに
分離されているが、容量形成域10と11の上に位置し、第
1容量および第2容量の各一方の電極となる金属層12と
13の一部が、第2容量および第1容量の側にまで延び、
金属層12が第2容量の半導体側電極窓14内の半導体基板
面(コンタクト拡散領域面)に接続され、一方、金属層
13が第1容量の半導体側電極窓15内の半導体基板面に接
続された接合構造となっている。この構造によれば、金
属層12と13を端子とし、この間に第1容量C1と第2容量
C2が並列接続された複合型のMIS型容量素子が実現され
る。FIG. 1 is a plan view showing the shape of the MIS type capacitance element of the present invention built in a bipolar integrated circuit.
IS type capacitance elements C 1 and C 2 are arranged in parallel. The cross-sectional structures of these MIS type capacitance elements C 1 and C 2 taken along the line X-X and the line Y-Y are the same as the structure shown in FIG. by the way,
In the MIS type capacitor of the present invention, the first capacitor C 1 and the second capacitor C 2
Although surrounded by the P + -type insulating isolation region 2 and isolated from each other, the metal layer 12 is located on the capacitance forming regions 10 and 11 and serves as one electrode of the first capacitance and the second capacitance. When
A part of 13 extends to the side of the second capacity and the first capacity,
The metal layer 12 is connected to the semiconductor substrate surface (contact diffusion region surface) in the semiconductor-side electrode window 14 of the second capacitor, while the metal layer 12
A junction structure 13 is connected to the semiconductor substrate surface in the semiconductor-side electrode window 15 of the first capacitor. According to this structure, the metal layers 12 and 13 are used as terminals, and the first capacitance C 1 and the second capacitance are provided between them.
A composite MIS type capacitive element in which C 2 is connected in parallel is realized.
第2図は、第1図で示したMIS型容量素子の等価回路
図であり、端子(金属層)13には、第1容量によっても
たらされる直列抵抗R1と接合容量Cj1が付加され、一
方、端子(金属層)12には、第2容量によってもたらさ
れる直列抵抗R2と接合容量Cj2が付加されたものとな
る。したがって、端子12と13の対称性が著るしく向上す
る。特に、第1容量と第2容量の寸法を等しく設定し、
両容量素子の形状を対称とするならば、端子12と13の対
称性はほぼ完全に近いものとなる。FIG. 2 is an equivalent circuit diagram of the MIS type capacitance element shown in FIG. 1, in which the terminal resistance (metal layer) 13 has a series resistance R 1 and a junction capacitance C j1 provided by the first capacitance, On the other hand, the terminal (metal layer) 12 has a series resistance R 2 and a junction capacitance C j2 added by the second capacitance added thereto. Therefore, the symmetry of the terminals 12 and 13 is significantly improved. In particular, the dimensions of the first and second capacitors are set equal,
If the shapes of both capacitance elements are symmetrical, the symmetry of the terminals 12 and 13 will be almost perfect.
以上の説明ではバイポーラ集積回路内に作り込まれた
MIS型容量素子を例示したが、MOS集積回路内へ作り込む
場合でも同様の構成とすればよい。この場合には、直列
抵抗に起因する対称性の低下が阻止される。In the above explanation, it was built in the bipolar integrated circuit.
Although the MIS type capacitance element has been illustrated, the same configuration may be used when it is built in a MOS integrated circuit. In this case, the reduction in symmetry due to the series resistance is prevented.
発明の効果 本発明によれば、第1容量と第2容量を逆並列接続し
てMIS型容量素子を構成するので、両電極に付与されるP
N接合の寄生容量が対称的になり、例えば、本発明のMIS
容量素子を対称的な回路に接続した場合、2つの信号ラ
インの一方のみの周波数特性を劣化させるのではなく、
同等に劣化させるので、信号ライン間の位相が相対的に
変化しないという格別の効果が得られる。また、この容
量素子を作り込むには、集積回路の拡散プロセスを変更
する必要がなく、プロセスに対応したマスクの変更で実
現できる。EFFECTS OF THE INVENTION According to the present invention, the first capacitor and the second capacitor are connected in anti-parallel to form the MIS type capacitor element, so that P applied to both electrodes
The parasitic capacitance of the N-junction becomes symmetrical, and for example, the MIS of the present invention
When the capacitive element is connected to a symmetrical circuit, the frequency characteristic of only one of the two signal lines is not deteriorated,
Since they are equally deteriorated, a special effect that the phase between the signal lines does not change relatively is obtained. Further, in order to build this capacitance element, it is not necessary to change the diffusion process of the integrated circuit, and it can be realized by changing the mask corresponding to the process.
第1図は本発明のMIS型容量素子の形状を示す平面図、
第2図は第1図で示すMIS型容量素子の等価回路図、第
3図はバイポーラ集積回路内に作り込まれた従来のMIS
型容量素子の断面構造図である。 1……P型シリコン基板、2……P+型絶縁分離領域、3
……N型エピタキシャル島領域、4……N型拡散領域、
5……N型コンタクト拡散領域、6……二酸化シリコン
膜、7,8……金属層、9……N+型埋込領域、10,11……容
量形成域、12,13……金属層(端子)、14,15……半導体
側電極窓、R1,R2……直列抵抗、Cj1,Cj2……接合容量。FIG. 1 is a plan view showing the shape of the MIS type capacitance element of the present invention,
FIG. 2 is an equivalent circuit diagram of the MIS type capacitance element shown in FIG. 1, and FIG. 3 is a conventional MIS built in a bipolar integrated circuit.
It is a section construction drawing of a type capacity element. 1 ... P-type silicon substrate, 2 ... P + type insulation isolation region, 3
... N-type epitaxial island region, 4 ... N-type diffusion region,
5 ... N-type contact diffusion region, 6 ... silicon dioxide film, 7,8 ... metal layer, 9 ... N + type buried region, 10,11 ... capacity forming region, 12,13 ... metal layer (Terminal), 14,15 …… Semiconductor side electrode window, R 1 , R 2 …… Series resistance, C j1 , C j2 …… Junction capacitance.
フロントページの続き (56)参考文献 特開 昭49−104586(JP,A) 特開 昭59−55047(JP,A) 特開 昭61−268057(JP,A) 特開 昭57−207358(JP,A)Continuation of the front page (56) References JP-A-49-104586 (JP, A) JP-A-59-55047 (JP, A) JP-A-61-268057 (JP, A) JP-A-57-207358 (JP , A)
Claims (1)
1,第2の島領域を逆導電型の半導体基板に形成し、上記
第1,第2の島領域内に夫々一導電型の第1,第2の拡散領
域を形成し、上記第1,第2の拡散領域上の絶縁膜の上に
夫々金属電極を形成し、上記第1の拡散領域にコンタク
トする半導体側電極ならびに上記第2拡散領域にコンタ
クトする半導体側電極を形成して、第1容量および第2
容量を作り込み、上記第1容量の金属電極と上記第2容
量の半導体側電極を接続し、上記第2容量の金属電極と
上記第1容量の半導体側電極を接続したことを特徴とす
るMIS型容量素子。1. A one-conductivity-type first plate having a substantially equal planar shape area.
The first and second island regions are formed on a semiconductor substrate of opposite conductivity type, and the first and second diffusion regions of one conductivity type are formed in the first and second island regions, respectively. A metal electrode is formed on each insulating film on the second diffusion region, a semiconductor-side electrode that contacts the first diffusion region and a semiconductor-side electrode that contacts the second diffusion region are formed, and Capacity and second
A MIS is characterized in that a capacitance is built in, the metal electrode of the first capacitance is connected to the semiconductor side electrode of the second capacitance, and the metal electrode of the second capacitance is connected to the semiconductor side electrode of the first capacitance. Type capacitive element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63070064A JP2563456B2 (en) | 1988-03-24 | 1988-03-24 | MIS type capacitive element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63070064A JP2563456B2 (en) | 1988-03-24 | 1988-03-24 | MIS type capacitive element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01241858A JPH01241858A (en) | 1989-09-26 |
JP2563456B2 true JP2563456B2 (en) | 1996-12-11 |
Family
ID=13420735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63070064A Expired - Fee Related JP2563456B2 (en) | 1988-03-24 | 1988-03-24 | MIS type capacitive element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2563456B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0794570A1 (en) * | 1996-03-06 | 1997-09-10 | STMicroelectronics S.r.l. | Integrated device with pads |
JP5476747B2 (en) * | 2009-03-05 | 2014-04-23 | 日産自動車株式会社 | Semiconductor device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5955047A (en) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | Semiconductor device and manufacture thereof |
-
1988
- 1988-03-24 JP JP63070064A patent/JP2563456B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH01241858A (en) | 1989-09-26 |
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Legal Events
Date | Code | Title | Description |
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LAPS | Cancellation because of no payment of annual fees |