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JPS6328035A - Reduction stepper - Google Patents

Reduction stepper

Info

Publication number
JPS6328035A
JPS6328035A JP61172387A JP17238786A JPS6328035A JP S6328035 A JPS6328035 A JP S6328035A JP 61172387 A JP61172387 A JP 61172387A JP 17238786 A JP17238786 A JP 17238786A JP S6328035 A JPS6328035 A JP S6328035A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
pins
substrate
flatness
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61172387A
Other languages
Japanese (ja)
Inventor
Naoya Ito
直也 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61172387A priority Critical patent/JPS6328035A/en
Publication of JPS6328035A publication Critical patent/JPS6328035A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691Handling of masks or workpieces

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To eliminate the gradation of a projecting image by individually independently moving upward or downward a plurality of substrate supporting pins provided in a region for supporting a semiconductor substrate. CONSTITUTION:A recess 6 is formed on the upper surface of a semiconductor substrate clamping jig body 5, a groove 7 for sucking in a vacuum the peripheral edge of a semicondnctor substrate 2 is formed on the peripheral edge of the recess 6, a plurality of substrate supporting pins 1, 1, ... are arranged in the recess 6, and the pins 1 are respectively connected to linear driving elements moving upward or downward individually independently. Further, a measuring instrument 4 for measuring the flatness of the substrate 1 supported by the pins 1, 1, ... and a controller 12 for regulating the height positions of the pins 1 by driving linear driving elements 3 by the output of the instrument 4 are provided. When the substrate 2 is placed on the body 5, the pins 1 are so moved by the elements 3 so that the substrate becomes the same plane.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は縮小投影露光装置、特に半導体基板表面の平面
度を測定し、平面度を矯正できる半導体基板固定治具を
具備する縮小投影露光装置に関する。
Detailed Description of the Invention [Industrial Application Field] The present invention relates to a reduction projection exposure apparatus, particularly a reduction projection exposure apparatus equipped with a semiconductor substrate fixing jig that can measure the flatness of a semiconductor substrate surface and correct the flatness. Regarding.

[従来の技術] 従来、この種縮小投影露光装置の露光ステージに半導体
基板を固定する治具は半導体基板の裏面に接する治具表
面の加工精度を良くし、治具表面の平面度を上げること
により半導体基板表面の平面度を上げていた。
[Prior Art] Conventionally, a jig for fixing a semiconductor substrate to the exposure stage of this type of reduction projection exposure apparatus has been designed to improve the processing accuracy of the jig surface that contacts the back surface of the semiconductor substrate and to increase the flatness of the jig surface. This increases the flatness of the semiconductor substrate surface.

[発明が解決しようとする問題点] 現在、縮小投影露光装置は解像力の向上がはかられてい
る。解像力の向上をはかると、縮小投影レンズの焦点深
度が浅くなるという問題が生じる。
[Problems to be Solved by the Invention] At present, efforts are being made to improve the resolution of reduction projection exposure apparatuses. If the resolution is improved, a problem arises in that the depth of focus of the reduction projection lens becomes shallower.

上述した従来の半導体基板固定治具は半導体基板表面の
平面度を矯正することができないため、縮小投影レンズ
の焦点深度が浅いと、レンズ像面の半導体表面に対する
傾斜や、レンズ像面の湾曲が大きかったり、固定治具の
平面度、ウェハーの平面度が悪かったりした場合に、半
導体基板表面が焦点深度の範囲からはずれて像がぼけて
しまい、希望する解像力が得られないという欠点が必る
The conventional semiconductor substrate fixing jig described above cannot correct the flatness of the semiconductor substrate surface, so if the depth of focus of the reduction projection lens is shallow, the lens image plane may be tilted with respect to the semiconductor surface or the lens image plane may be curved. If the size of the wafer is too large, or the flatness of the fixture or wafer is poor, the semiconductor substrate surface will be out of the depth of focus range and the image will become blurry, resulting in the inability to obtain the desired resolution. .

また半導体基板と固定治具との間にゴミなどの異物をは
さんだ場合も同様の問題を生じる。
A similar problem also occurs when foreign matter such as dust is caught between the semiconductor substrate and the fixing jig.

[発明の従来技術に対する相違点] 上述した従来の半導体基板固定治具を有する縮小投影露
光装置に対し、本発明は半導体基板の平面度を複数本の
ピンにより補正する構造に独創的内容を有する。
[Differences between the invention and the prior art] In contrast to the above-described conventional reduction projection exposure apparatus having a semiconductor substrate fixing jig, the present invention has an original content in a structure in which the flatness of a semiconductor substrate is corrected using a plurality of pins. .

[問題点を解決するための手段] 本発明はフォトレジストを被覆した半導体基板と露光マ
スクとの位置合わせを行って露光を施す縮小投影露光装
置において、半導体基板を支持する領域内に設けられた
複数本の基板支持用ピンと、該ピンを個々に独立させて
上下動させる駆動素子と、前記ピンにより支持された半
導体基板の平面度を測定する測定器と、該測定器の出力
により駆動素子を駆動させて各ピンの高さ位置を調整す
る制御部とを有することを特徴とする縮小投影露光装置
でおる。
[Means for Solving the Problems] The present invention provides a reduction projection exposure apparatus that performs exposure by aligning a semiconductor substrate coated with a photoresist with an exposure mask. A plurality of substrate supporting pins, a driving element that moves the pins up and down independently, a measuring device that measures the flatness of the semiconductor substrate supported by the pins, and a driving element using the output of the measuring device. The reduction projection exposure apparatus is characterized in that it has a control section that is driven to adjust the height position of each pin.

[実施例] 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

(実施例1) 第1図に示すように本実施例1は半導体基板固定治具本
体5の上面に凹部6を設け、凹部6の周縁部に半導体基
板2の周縁を真空吸着する溝7を形成し、凹部6内に複
数本の基板支持用ピン1゜1・・・を配設し、各ピン1
を個々に独立ざぜて上下動ざぜるリニア駆動素子3にそ
れぞれ連結する。
(Example 1) As shown in FIG. 1, in this example 1, a recess 6 is provided on the upper surface of the semiconductor substrate fixing jig main body 5, and a groove 7 for vacuum suctioning the periphery of the semiconductor substrate 2 is provided at the periphery of the recess 6. A plurality of substrate support pins 1゜1... are arranged in the recess 6, and each pin 1
are connected to linear drive elements 3 that move up and down individually.

さらに0、ピン1,1・・・により支持された半導体基
板2の平面度を測定する測定器4と、測定器4の出力に
より各リニア駆動素子3を駆動させて各ピン1の高さ位
置を調整する制御部12とを装置したものである。
Furthermore, a measuring device 4 is provided to measure the flatness of the semiconductor substrate 2 supported by the pins 1, 1, . This device is equipped with a control section 12 that adjusts the .

実施例において、半導体基板2が半導体基板固定治具本
体5上に載せられると、凹部6及び周辺固定用@7が真
空に引かれて半導体基板2が半導体基板固定治具5に吸
着される。次に半導体基板固定治具5が載ったX−Yス
テージが動いて平面度測定器4により最初の露光範囲内
の半導体基板表面の平面度を測定し、それぞれのピン1
がリニア駆動素子3により半導体基板表面が平面になる
ように動く。さらに前もって調べであるレンズ像面の傾
斜及び湾曲に半導体基板2の表面がおうようにピン1が
動き、露光を行なう。次の露光位置にX−Yステージが
動き、上記の動作を行ない露光を行なうというシーケン
スを繰返して1枚の半導体基板の露光が終了する。
In the embodiment, when the semiconductor substrate 2 is placed on the semiconductor substrate fixing jig main body 5, the recess 6 and the peripheral fixing @7 are evacuated and the semiconductor substrate 2 is attracted to the semiconductor substrate fixing jig 5. Next, the X-Y stage on which the semiconductor substrate fixing jig 5 is mounted moves, and the flatness measuring device 4 measures the flatness of the semiconductor substrate surface within the initial exposure range.
is moved by the linear drive element 3 so that the surface of the semiconductor substrate becomes flat. Further, the pin 1 moves so that the surface of the semiconductor substrate 2 is aligned with the inclination and curvature of the lens image plane, which have been determined in advance, to perform exposure. The X-Y stage moves to the next exposure position, and the sequence of performing the above operations and performing exposure is repeated to complete the exposure of one semiconductor substrate.

第2図、第3図、第4図を用いて半導体基板が矯正され
る様子を説明する。
The manner in which the semiconductor substrate is corrected will be explained using FIGS. 2, 3, and 4.

第2図は半導体基板2が半導体基板固定治具5上に載せ
られ、真空吸着されたところを示す。半導体基板2の平
面度の悪さや傾き、それぞれのピン1の製造誤差や高ざ
の違いなどにより、半導体基板2の表面が平面になって
いない。この半導体基板2の表面の平面度を平面度測定
器4で測定し、その結果をもとにして制御部12の指令
により各リニア駆動素子3が半導体基板2の表面が平面
になるように動くと、第3図に示した状態になる。例え
ば、第2図の状態からリニア駆動素子3a、 3b。
FIG. 2 shows the semiconductor substrate 2 placed on the semiconductor substrate fixing jig 5 and vacuum-adsorbed. The surface of the semiconductor substrate 2 is not flat due to poor flatness or inclination of the semiconductor substrate 2, manufacturing errors or differences in height of each pin 1, and the like. The flatness of the surface of the semiconductor substrate 2 is measured by a flatness measuring device 4, and based on the results, each linear drive element 3 is moved according to a command from the control unit 12 so that the surface of the semiconductor substrate 2 becomes flat. Then, the state shown in FIG. 3 is reached. For example, from the state shown in FIG. 2, the linear drive elements 3a and 3b.

3dが縮み、素子3Cが少し縮むことによりピンIa。3d shrinks, and the element 3C shrinks a little, causing pin Ia.

1b、 1C,ldがそれぞれの縮み量に対応して下が
り、半導体基板2の表面が第3図にように平面になる。
1b, 1C, and ld decrease in accordance with the respective shrinkage amounts, and the surface of the semiconductor substrate 2 becomes flat as shown in FIG.

その後、前もって測定して求めであるレンズ像面の傾斜
及び湾曲に一致するように制御部12の指令を受けてリ
ニア駆動素子3a、 3b、 3dが伸びでピンla、
 1b、 1dが上がり第4図に示すような状態になる
Thereafter, the linear drive elements 3a, 3b, and 3d extend to match the inclination and curvature of the lens image plane, which have been measured and determined in advance, in response to a command from the control unit 12, and the pin la,
1b and 1d rise, resulting in the state shown in FIG.

(実施例2) 第5図は本発明の実施例2の縦断面図であり第6図は第
5図中のチャック11の詳細図である。半導体基板2が
X−Yステージ10上に載せられると、周辺固定用溝7
が真空に引かれて半導体基板2はX−Yステージ10に
固定される。ステージ駆動用モータ8によりX−Yステ
ージ10が動いて、半導体基板2が露光位置まで移動す
る。縮小投影レンズ12の下に縮小投影レンズ12に対
して移動しないように固定されたチャック11の凹部6
の真空が引かれて半導体基板2がチャック11に固定さ
れる。
(Embodiment 2) FIG. 5 is a longitudinal sectional view of Embodiment 2 of the present invention, and FIG. 6 is a detailed view of the chuck 11 in FIG. 5. When the semiconductor substrate 2 is placed on the X-Y stage 10, the peripheral fixing groove 7
is evacuated and the semiconductor substrate 2 is fixed to the XY stage 10. The XY stage 10 is moved by the stage drive motor 8, and the semiconductor substrate 2 is moved to the exposure position. A recess 6 of the chuck 11 is fixed under the reduction projection lens 12 so as not to move relative to the reduction projection lens 12.
A vacuum is drawn, and the semiconductor substrate 2 is fixed to the chuck 11.

次に平面度測定器4により半導体基板表面の露光範囲内
の平面度を測定し、その情報をもとにして制御部12の
指令によりリニア駆動素子3及びピン1が動いて半導体
基板表面の矯正及び半導体基板表面が縮小投影レンズ1
3の像面の傾斜及び湾曲と一致するように補正を加え、
露光を施す。次にチャック11の凹部6の真空をきり、
X−Yステージ10が動き半導体基板2が次の露光位置
まで動く。
Next, the flatness of the semiconductor substrate surface within the exposure range is measured by the flatness measuring device 4, and based on the information, the linear drive element 3 and pin 1 are moved by commands from the control unit 12 to correct the semiconductor substrate surface. and the semiconductor substrate surface is a reduction projection lens 1
Add correction to match the inclination and curvature of the image plane in 3.
Apply exposure. Next, the vacuum in the recess 6 of the chuck 11 is released,
The X-Y stage 10 moves and the semiconductor substrate 2 moves to the next exposure position.

9はローラである。9 is a roller.

[発明の効果] 以上説明したように本発明は半導体基板表面の矯正を行
なうようにしたので、縮小投影レンズの高解力化にとも
なう焦点深度の狭小化により、縮小投影レンズのレンズ
像面傾斜、湾曲、また半導体基板の平面度や半導体基板
固定治具の平面度、半導体基板と半導体基板固定治具と
の間にゴミなどをはさむことなどの影響により半導体基
板表面が焦点深度の範囲からずれ、それに伴う投影像の
ぼけをなくすことができる効果を有するものである。
[Effects of the Invention] As explained above, the present invention corrects the surface of the semiconductor substrate, so that the lens image plane tilt and curvature of the reduction projection lens are reduced due to the narrowing of the depth of focus accompanying the increase in resolution of the reduction projection lens. In addition, due to the flatness of the semiconductor substrate, the flatness of the semiconductor substrate fixing jig, and the presence of dust between the semiconductor substrate and the semiconductor substrate fixing jig, the surface of the semiconductor substrate may deviate from the depth of focus range. This has the effect of eliminating the accompanying blurring of the projected image.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の縮小投影露光装置が有する半導体基板
固定治具の断面図、第2図は半導体基板が半導体基板固
定治具上に載せられて真空吸着されたところを示す図、
第3図は半導体基板表面の平面度を測定し、表面を平面
になるように矯正したところを示す図、第4図は半導体
基板表面がレンズ像面の傾斜及び湾曲にあうようにざら
に矯正を加えたところを示す図、第5図は本発明の実施
例2の縦断面図、第6図は第5図中のチャックを示す詳
細図である。 1・・・ピン       2・・・半導体基板3・・
・リニア駆動素子  4・・・平面度測定器5・・・半
導体基板固定治具本体 6・・・凹部       7・・・周辺固定用溝8・
・・ステージ駆動用モータ 9・・・ローラ      10・・・X−Yステージ
11・・・チャック
FIG. 1 is a cross-sectional view of a semiconductor substrate fixing jig included in the reduction projection exposure apparatus of the present invention, and FIG. 2 is a diagram showing a semiconductor substrate placed on the semiconductor substrate fixing jig and vacuum suctioned.
Figure 3 shows the flatness of the semiconductor substrate surface measured and corrected to make it flat, and Figure 4 shows the semiconductor substrate surface roughly corrected to match the inclination and curvature of the lens image plane. FIG. 5 is a vertical sectional view of the second embodiment of the present invention, and FIG. 6 is a detailed view showing the chuck in FIG. 5. 1...Pin 2...Semiconductor substrate 3...
・Linear drive element 4...Flatness measuring device 5...Semiconductor substrate fixing jig body 6...Concavity 7...Peripheral fixing groove 8・
...Stage drive motor 9...Roller 10...X-Y stage 11...Chuck

Claims (1)

【特許請求の範囲】[Claims] (1)フォトレジストを被覆した半導体基板と露光マス
クとの位置合わせを行つて露光を施す縮小投影露光装置
において、半導体基板を支持する領域内に設けられた複
数本の基板支持用ピンと、該ピンを個々に独立させて上
下動させる駆動素子と、前記ピンにより支持された半導
体基板の平面度を測定する測定器と、該測定器の出力に
より駆動素子を駆動させて各ピンの高さ位置を調整する
制御部とを有することを特徴とする縮小投影露光装置。
(1) In a reduction projection exposure apparatus that performs exposure by aligning a semiconductor substrate coated with a photoresist with an exposure mask, a plurality of substrate support pins provided in an area supporting the semiconductor substrate and the pins are provided. a driving element that individually moves up and down the pins, a measuring device that measures the flatness of the semiconductor substrate supported by the pins, and a driving element that is driven by the output of the measuring device to measure the height position of each pin. 1. A reduction projection exposure apparatus, comprising: a control section for adjustment.
JP61172387A 1986-07-22 1986-07-22 Reduction stepper Pending JPS6328035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61172387A JPS6328035A (en) 1986-07-22 1986-07-22 Reduction stepper

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61172387A JPS6328035A (en) 1986-07-22 1986-07-22 Reduction stepper

Publications (1)

Publication Number Publication Date
JPS6328035A true JPS6328035A (en) 1988-02-05

Family

ID=15940979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61172387A Pending JPS6328035A (en) 1986-07-22 1986-07-22 Reduction stepper

Country Status (1)

Country Link
JP (1) JPS6328035A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181054A (en) * 1994-12-26 1996-07-12 Nikon Corp Stage apparatus and controlling method therefor
US7459386B2 (en) 2004-11-16 2008-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming solder bumps of increased height
JP2009010085A (en) * 2007-06-27 2009-01-15 Dainippon Screen Mfg Co Ltd Decompression-drying device
JP2010109369A (en) * 2008-10-31 2010-05-13 Asml Netherlands Bv Calibration method and lithographic apparatus for calibrating optimum take over height of substrate
JP2011204784A (en) * 2010-03-24 2011-10-13 Yaskawa Electric Corp Workpiece supporting mechanism, supporting method, and conveying system including the same
JP2013026233A (en) * 2011-07-14 2013-02-04 Toshiba Corp Stage device and process device
JP2014502784A (en) * 2010-12-20 2014-02-03 エーファウ・グループ・エー・タルナー・ゲーエムベーハー Receiving means for mounting wafers
JP2015099927A (en) * 2014-12-16 2015-05-28 株式会社東芝 Substrate holding device, pattern transfer device, and pattern transfer method
JP2017195411A (en) * 2017-07-14 2017-10-26 芝浦メカトロニクス株式会社 Suction stage, bonding device, and bonding method
JP2021503103A (en) * 2017-11-20 2021-02-04 エーエスエムエル ネザーランズ ビー.ブイ. Board holder, board support, method of clamping the board to the clamping system, and lithography equipment

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181054A (en) * 1994-12-26 1996-07-12 Nikon Corp Stage apparatus and controlling method therefor
US7459386B2 (en) 2004-11-16 2008-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming solder bumps of increased height
JP2009010085A (en) * 2007-06-27 2009-01-15 Dainippon Screen Mfg Co Ltd Decompression-drying device
US8384882B2 (en) 2008-10-31 2013-02-26 Asml Netherlands B.V. Calibration method and lithographic apparatus for calibrating an optimum take over height of a substrate
JP2010109369A (en) * 2008-10-31 2010-05-13 Asml Netherlands Bv Calibration method and lithographic apparatus for calibrating optimum take over height of substrate
JP2011204784A (en) * 2010-03-24 2011-10-13 Yaskawa Electric Corp Workpiece supporting mechanism, supporting method, and conveying system including the same
US10886156B2 (en) 2010-12-20 2021-01-05 Ev Group E. Thallner Gmbh Accomodating device for retaining wafers
JP2014502784A (en) * 2010-12-20 2014-02-03 エーファウ・グループ・エー・タルナー・ゲーエムベーハー Receiving means for mounting wafers
US10325798B2 (en) 2010-12-20 2019-06-18 Ev Group E. Thallner Gmbh Accommodating device for retaining wafers
US11355374B2 (en) 2010-12-20 2022-06-07 Ev Group E. Thallner Gmbh Accommodating device for retaining wafers
US11756818B2 (en) 2010-12-20 2023-09-12 Ev Group E. Thallner Gmbh Accommodating device for retaining wafers
US9021983B2 (en) 2011-07-14 2015-05-05 Kabushiki Kaisha Toshiba Stage apparatus and process apparatus
JP2013026233A (en) * 2011-07-14 2013-02-04 Toshiba Corp Stage device and process device
JP2015099927A (en) * 2014-12-16 2015-05-28 株式会社東芝 Substrate holding device, pattern transfer device, and pattern transfer method
JP2017195411A (en) * 2017-07-14 2017-10-26 芝浦メカトロニクス株式会社 Suction stage, bonding device, and bonding method
JP2021503103A (en) * 2017-11-20 2021-02-04 エーエスエムエル ネザーランズ ビー.ブイ. Board holder, board support, method of clamping the board to the clamping system, and lithography equipment
US11187998B2 (en) 2017-11-20 2021-11-30 Asml Netherlands B.V. Substrate holder, substrate support and method of clamping a substrate to a clamping system

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