JPS63273337A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63273337A JPS63273337A JP62108323A JP10832387A JPS63273337A JP S63273337 A JPS63273337 A JP S63273337A JP 62108323 A JP62108323 A JP 62108323A JP 10832387 A JP10832387 A JP 10832387A JP S63273337 A JPS63273337 A JP S63273337A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor device
- film
- layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004642 Polyimide Substances 0.000 claims abstract description 13
- 229920001721 polyimide Polymers 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052737 gold Inorganic materials 0.000 abstract description 18
- 239000010931 gold Substances 0.000 abstract description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052697 platinum Inorganic materials 0.000 abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 4
- 239000010936 titanium Substances 0.000 abstract description 4
- 229910052719 titanium Inorganic materials 0.000 abstract description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にバンプの
形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming bumps.
近年、ICカードの需要が高まってくるにつれて’l’
AB (Tape Automated Bondin
g) I Cの重要性が増してきている。In recent years, as the demand for IC cards has increased, 'l'
AB (Tape Automated Bondin)
g) The importance of IC is increasing.
TABICを形成する手段の1つとして、ウェーハ上に
バンプを形成する方法がある。以下従来のバンプの形成
方法を第2図を用いて説明する。One method for forming TABIC is to form bumps on a wafer. A conventional bump forming method will be described below with reference to FIG.
まず第2図(a)に示すように、半導体基板101に半
導体素子を形成したのち絶縁膜102を形成する9次い
でこの絶縁膜102上のポンディングパッド形成領域に
金属配線層、例えばアルミニウムから成る電極103を
形成する。次で全面に絶縁物からなるパッシベーション
11%104を形成し、ポンディングパッド形成領域お
よびダイシング領域を開口し、バンプとなる金属をめっ
きする際の電極となる金属配線層、例えばアルミニウム
膜105を全面に被着し、その後、バンプ形成用金属、
例えば金との密着性を良好にする為のチタン膜106と
金とアルミニウム膜105の反応防止用金属として白金
pA107をスパッタ法により形成し、ポンディングパ
ッド形成領域をおおうようにしてパターニングする。First, as shown in FIG. 2(a), a semiconductor element is formed on a semiconductor substrate 101, and then an insulating film 102 is formed.9 Next, a metal wiring layer, for example, made of aluminum, is formed on a bonding pad forming area on this insulating film 102. Electrodes 103 are formed. Next, a passivation 11% 104 made of an insulator is formed on the entire surface, a bonding pad formation area and a dicing area are opened, and a metal wiring layer, for example, an aluminum film 105, which will be an electrode when plating metal that will become a bump, is formed on the entire surface. and then the metal for bump formation,
For example, platinum pA 107 is formed by sputtering as a metal for preventing a reaction between the titanium film 106 and the gold and aluminum film 105 to improve adhesion with gold, and is patterned to cover the region where the bonding pad is to be formed.
次に、第2図(b)に示すように、通常の光食刻法によ
り、ポンディングパッド形成領域部を開口したフォトレ
ジスト層109Aを形成した後、金めつき法により被着
して金バンプ110を形成する。Next, as shown in FIG. 2(b), a photoresist layer 109A with openings in the bonding pad forming area is formed by ordinary photolithography, and then gold is deposited by gold plating. A bump 110 is formed.
次に第2図(c)に示すように、フォトレジスト層10
9Aを除去した後、金バンプ110及び白金膜107を
マスクとしてアルミニウム膜105を除去することによ
り金バンプ110を有する半導体装置が完成する。Next, as shown in FIG. 2(c), a photoresist layer 10
After removing 9A, the aluminum film 105 is removed using the gold bumps 110 and the platinum film 107 as a mask, thereby completing a semiconductor device having the gold bumps 110.
上述した従来のバンプ形成方法によるバンプ構造では、
金めつきの際に、金が、マスクとなったフォトレジスト
N9Aの上部横方向に伸びていく為、出来上りのバブの
形状は、金バンプ110と半導体装置表面との間に、第
2図(’C)に示すような空隙112が形成される。In the bump structure by the conventional bump formation method described above,
During gold plating, the gold extends laterally across the upper part of the photoresist N9A, which serves as a mask, so the shape of the completed bubble is formed between the gold bump 110 and the surface of the semiconductor device, as shown in Figure 2 (' A void 112 as shown in C) is formed.
そして、バンプ付きのICチップにリード電極をボンデ
ィングする際、ボンディング圧力によって金バンプ11
0がつぶれ、空隙112を埋めるにとどまらず、ICチ
ップにクラックを生じさせて歩留を悪くしたり、信頼性
を低下させるという欠点がある。When bonding a lead electrode to an IC chip with bumps, the gold bumps 11 are bonded by bonding pressure.
There is a drawback that the 0 is crushed and not only fills the void 112, but also causes cracks in the IC chip, which impairs yield and reduces reliability.
本発明の目的は、ボンディング時のバンプのつぶれによ
るストレスが半導体基板に加わることが少ない構造のバ
ンプを有する歩留り及び信頼性の向上した半導体装置の
製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device with improved yield and reliability, which has a bump structure in which less stress is applied to a semiconductor substrate due to crushing of the bump during bonding.
本発明の半導体装置の製造方法は、半導体基板上に形成
された電極配線のバンプ形成用領域の外周部にポリイミ
ド層を選択的に形成する工程と、少くとも前記電極配線
のバンプ形成用領域を除き前記ポリイミド層間を覆うフ
ォトレジスト層を形成する工程と、前記電極配線のバン
プ形成用領域にめっき法によりバンプを形成する工程と
を含んで構成される。The method for manufacturing a semiconductor device of the present invention includes a step of selectively forming a polyimide layer on the outer periphery of a bump formation region of an electrode wiring formed on a semiconductor substrate, and a step of selectively forming a polyimide layer on the outer periphery of a bump formation region of an electrode wiring formed on a semiconductor substrate. The method includes a step of forming a photoresist layer covering between the polyimide layers, and a step of forming a bump in a bump forming region of the electrode wiring by a plating method.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第1図(a)〜(C)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず第1図(a)に示すように、従来と同様に、半導体
基板101上に絶縁WA102を介してアルミニウム電
極103を形成したのち、パッシベーション1104.
めっき電極用のアルミニウム膜105及びバターニング
された一チタン膜106と白金plA107をそれぞれ
形成する。First, as shown in FIG. 1(a), as in the conventional case, an aluminum electrode 103 is formed on a semiconductor substrate 101 via an insulating WA 102, and then passivation 1104.
An aluminum film 105, a patterned titanium film 106, and platinum plA 107 are respectively formed for plating electrodes.
次に、バンプを形成すべき白金膜107等からなる電極
配線上は開口され、バンプ形成用領域120の周囲をお
おい、それぞれのバンプ形成用領域に対しては独立する
ポリイミド層108を、通常の光食刻法を用いて、フォ
トレジストをマスクとしてヒドラジンでエツチングする
ことにより形成する。Next, an opening is made on the electrode wiring made of platinum film 107 or the like on which bumps are to be formed, and a polyimide layer 108 is formed, which is independent of the bump forming area 120, to cover the periphery of the bump forming area 120. It is formed by etching with hydrazine using a photoresist as a mask using a photolithography method.
次に第1図(b)に示すように、少なくとも電極配線の
バンプ形成用領域120上を開口するようなフォトレジ
ストパターン109を通常の光食刻法により形成した後
、めっき法により、金を約10μmを厚さにめっきして
金バンプ110を形成する。Next, as shown in FIG. 1(b), after forming a photoresist pattern 109 with an opening on at least the bump forming region 120 of the electrode wiring by a normal photoetching method, gold is deposited by a plating method. Gold bumps 110 are formed by plating to a thickness of about 10 μm.
以下第1図(c)に示すように、フォトレジストJ’1
109を除去して金バンプ110及びポリイミド層10
8をマスクとしてアルミニウム膜105をエツチング除
去することによりバンプ付きの半導体装置が完成する。As shown in FIG. 1(c) below, photoresist J'1
109 is removed to form gold bumps 110 and polyimide layer 10.
By etching and removing the aluminum film 105 using 8 as a mask, a semiconductor device with bumps is completed.
このようにして形成された半導体装直においては、金バ
ンプ110と半導体装置の表面との間にはポリイミド層
108が存在するため、後工程でこの金バンプ110に
リード電極をボンディングした場合のボンディング圧力
によるストレスは緩和される。このため半導体チップに
クラックを生じることがなくなる。In the semiconductor device formed in this way, since the polyimide layer 108 exists between the gold bumps 110 and the surface of the semiconductor device, bonding will be difficult when lead electrodes are bonded to the gold bumps 110 in a later process. Stress caused by pressure is alleviated. This prevents cracks from occurring in the semiconductor chip.
尚、上気実施例においてはバンプを形成する金属として
金を用いた場合について説明したが、銅を用いてもよい
ことは勿論である。Incidentally, in the above embodiment, a case has been described in which gold is used as the metal for forming the bumps, but it goes without saying that copper may also be used.
以上説明したように本発明は、電極配線のバンプ形成用
領域の外周部にポリイミド層を形成することにより、リ
ード電極をボンデインする時のバンプのつぶれによるス
トレスが半導体基板に加わることが少なくなるという効
果がある。このため半導体装置の製造歩留及び信頼性は
向上する。As explained above, in the present invention, by forming a polyimide layer on the outer periphery of the bump forming area of the electrode wiring, the stress caused by crushing the bumps when bonding the lead electrodes is reduced on the semiconductor substrate. effective. Therefore, the manufacturing yield and reliability of semiconductor devices are improved.
第1図(a)〜(C)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図(a
)〜(C)は従来の半導体装置の製造方法を説明する為
の工程順に示した半導体チップの断面図である。
101・・・半導体基板、102・・・絶縁膜、103
・・・アルミニウム膜極、104・・・パッシベーショ
ン膜、105・・・アルミニウム膜、106・・・チタ
ン膜、107・・・白金膜、108・・・ポリイミド層
、109・・・フォトレジスト層、110・・・金バン
プ、112・・・空隙、120・・・パブ形成用領域。
代理人 弁理士 内 原 音′
−〈1(a) to 1(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device. 101... Semiconductor substrate, 102... Insulating film, 103
... Aluminum film electrode, 104 ... Passivation film, 105 ... Aluminum film, 106 ... Titanium film, 107 ... Platinum film, 108 ... Polyimide layer, 109 ... Photoresist layer, 110...Gold bump, 112...Gap, 120...Pub formation area. Agent Patent Attorney Oto Uchihara −〈
Claims (1)
域の外周部にポリイミド層を選択的に形成する工程と、
少くとも前記電極配線のバンプ形成用領域を除き前記ポ
リイミド層間を覆うフォトレジスト層を形成する工程と
、前記電極配線のバンプ形成用領域にめっき法によりバ
ンプを形成する工程とを含むことを特徴とする半導体装
置の製造方法。selectively forming a polyimide layer on the outer periphery of a bump formation region of an electrode wiring formed on a semiconductor substrate;
It is characterized by comprising the steps of: forming a photoresist layer covering between the polyimide layers except for at least the bump formation area of the electrode wiring; and forming a bump in the bump formation area of the electrode wiring by a plating method. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62108323A JPS63273337A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62108323A JPS63273337A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63273337A true JPS63273337A (en) | 1988-11-10 |
Family
ID=14481793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62108323A Pending JPS63273337A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63273337A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5244833A (en) * | 1989-07-26 | 1993-09-14 | International Business Machines Corporation | Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139942A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
-
1987
- 1987-04-30 JP JP62108323A patent/JPS63273337A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139942A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5244833A (en) * | 1989-07-26 | 1993-09-14 | International Business Machines Corporation | Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer |
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