JP3389517B2 - Chip size package and manufacturing method thereof - Google Patents
Chip size package and manufacturing method thereofInfo
- Publication number
- JP3389517B2 JP3389517B2 JP35178398A JP35178398A JP3389517B2 JP 3389517 B2 JP3389517 B2 JP 3389517B2 JP 35178398 A JP35178398 A JP 35178398A JP 35178398 A JP35178398 A JP 35178398A JP 3389517 B2 JP3389517 B2 JP 3389517B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- chip size
- opening
- forming
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
- H01L2224/11902—Multiple masking steps
- H01L2224/11903—Multiple masking steps using different masks
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップサイズパッ
ケージ及びその製造方法に関する。チップサイズパッケ
ージ（Chip Size Package）は、ＣＳＰとも呼ばれ、チ
ップサイズと同等か、わずかに大きいパッケージの総称
であり、高密度実装を目的としたパッケージである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package and its manufacturing method. A chip size package is also called a CSP and is a generic term for packages that are equal to or slightly larger than the chip size, and are packages intended for high-density mounting.
【０００２】[0002]
【従来の技術】従来、この分野では、一般にＢＧＡ（Ba
ll Grid Array）と呼ばれ、面状に配列された複数のハ
ンダボールを持つ構造、ファインピッチＢＧＡと呼ば
れ、ＢＧＡのボールピッチをさらに狭ピッチにしてＰＫ
Ｇ外形がチップサイズに近くなった構造等が知られてい
る。2. Description of the Related Art Conventionally, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, called a fine pitch BGA.
A structure in which the G outer shape is close to the chip size is known.
【０００３】また、最近では、「日経マイクロデバイ
ス」１９９８年８月号 ４４頁〜７１頁に記載されたウ
エハーＣＳＰがある。このウエハーＣＳＰは、基本的に
は、チップのダイシング前に配線やアレイ状のパッドを
ウエハープロセス（前工程）で作り込むＣＳＰである。
この技術によって、ウエハープロセスとパッケージ・プ
ロセス（後工程）が一体化され、パッケージ・コストが
大幅に低減できるようになることが期待されている。Recently, there is a wafer CSP described in "Nikkei Microdevice", August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring and array pads are formed in a wafer process (pre-process) before dicing of chips.
With this technology, it is expected that the wafer process and the package process (post-process) will be integrated and the package cost can be significantly reduced.
【０００４】ウエーハＣＳＰの種類には、封止樹脂型と
再配線型がある。このうち、再配線型は、図１３に示す
ように、封止樹脂を使わず、再配線を形成した構造であ
る。チップ５１の表面にＡｌ電極５２、Ｃｕから成る配
線層５３、絶縁層５４が積層され、配線層５３上にはメ
タル・ポスト５５が形成され、その上に半田バンプ５６
が形成されている。配線層５３は、半田バンプ５６をチ
ップ上に所定のアレイ状に配置するための再配線として
用いられる。There are two types of wafer CSP, a sealing resin type and a rewiring type. Among them, the rewiring type has a structure in which rewiring is formed without using a sealing resin, as shown in FIG. An Al electrode 52, a wiring layer 53 made of Cu, and an insulating layer 54 are laminated on the surface of the chip 51, a metal post 55 is formed on the wiring layer 53, and a solder bump 56 is formed thereon.
Are formed. The wiring layer 53 is used as a rewiring for arranging the solder bumps 56 on the chip in a predetermined array.
【０００５】以下、従来のチップサイズパッケージの製
造方法を図１４乃至図１７を参照しながら説明する。A conventional method of manufacturing a chip size package will be described below with reference to FIGS.
【０００６】図１４に示すように、半導体基板６１上に
Ａｌ電極パッド６２を形成し、これを覆うようにＳｉＮ
から成るパッシベーション膜６３を形成する。Ａｌ電極
パッド６２上には、後に形成する配線層との電気的接続
をとるために開口を設ける。As shown in FIG. 14, an Al electrode pad 62 is formed on a semiconductor substrate 61, and SiN is formed so as to cover it.
A passivation film 63 of is formed. An opening is provided on the Al electrode pad 62 for electrical connection with a wiring layer to be formed later.
【０００７】そして、図１５に示すように、全面にＣｒ
から成るバリア層６４およびＣｕから成るメッキ用電極
層６５をスパッタ法により形成する。このバリア層６４
は、Ｃｕから成る配線層６７とＡｌ電極パッド６２との
間に介在して、ＣｕとＡｌが相互に侵入することを防止
している。Then, as shown in FIG. 15, Cr is formed on the entire surface.
A barrier layer 64 made of and a plating electrode layer 65 made of Cu are formed by a sputtering method. This barrier layer 64
Is interposed between the wiring layer 67 made of Cu and the Al electrode pad 62 to prevent Cu and Al from entering each other.
【０００８】次に、図１６に示すように、メッキ用電極
層６５上の所定の領域にホトレジスト層６６を形成し、
電解メッキによりＣｕから成る配線層６７を形成する。Next, as shown in FIG. 16, a photoresist layer 66 is formed in a predetermined region on the plating electrode layer 65,
A wiring layer 67 made of Cu is formed by electrolytic plating.
【０００９】そして、図１７に示すように、配線層６７
をマスクにして、メッキ用電極層６５およびバリア層６
６をウエットエッチングにより除去する。Then, as shown in FIG.
Using as a mask, the electrode layer 65 for plating and the barrier layer 6
6 is removed by wet etching.
【００１０】[0010]
【発明が解決しようとする課題】上記従来技術のよう
に、Ａｌ電極パッドと半田バンプとを接続する配線層の
材料として、機械的強度、耐湿性などの信頼性確保の観
点からＣｕを用いるられる。As in the prior art described above, Cu is used as the material of the wiring layer that connects the Al electrode pad and the solder bump from the viewpoint of securing reliability such as mechanical strength and moisture resistance. .
【００１１】しかしながら、Ｃｕはエッチングが困難で
あることから、メッキ技術による成膜が必要であり、通
常のＳｉウエーハプロセスで処理できない。本発明は、
このような課題の鑑みてなされたものであり、再配線層
の形成工程を既存のＳｉウエーハプロセスの工程フロー
内に含めて、ウエーハＣＳＰの製造工程を容易にし、か
つ簡略化することを目的としている。However, since Cu is difficult to etch, it is necessary to form a film by a plating technique, and Cu cannot be processed by a normal Si wafer process. The present invention is
The present invention has been made in view of such problems, and aims to facilitate and simplify the manufacturing process of the wafer CSP by including the process of forming the redistribution layer in the process flow of the existing Si wafer process. There is.
【００１２】[0012]
【課題を解決するための手段】上記の課題を解決するた
めに、本発明は金属電極パッドと半田バンプとを接続す
る再配線層をＡｌ合金で形成する。これに伴って、Ａｌ
合金から成る再配線層の機械的強度および耐湿性対策と
して、この配線層をＳｉＮなどのパッシベーション膜で
被覆する。再配線層とＡｌ電極パッドとの間、再配線層
と柱状電極との間にはバリア層を形成する。In order to solve the above problems, the present invention forms a rewiring layer for connecting a metal electrode pad and a solder bump with an Al alloy. Along with this, Al
As a measure against the mechanical strength and moisture resistance of the rewiring layer made of an alloy, this wiring layer is covered with a passivation film such as SiN. A barrier layer is formed between the redistribution layer and the Al electrode pad and between the redistribution layer and the columnar electrode.
【００１３】これにより、信頼性を確保しながら再配線
層を既存のＳｉウエーハプロセスの工程フロー内に含め
ることが可能になる。This makes it possible to include the redistribution layer in the process flow of the existing Si wafer process while ensuring reliability.
【００１４】また、再配線層に平面でみて複数のスリッ
トを設けることにより、熱ストレスなどに対する機械的
強度を向上することができる。Further, by providing the rewiring layer with a plurality of slits in a plan view, it is possible to improve the mechanical strength against heat stress and the like.
【００１５】[0015]
【発明の実施の形態】次に、本発明の第１の実施例を図
１乃至図７を参照しながら説明する。BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to FIGS.
【００１６】まず、図１に示すように、半導体基板１上
に、Ａｌ合金層と第１のバリアメタル層から成る金属電
極パッド２を形成する。Ａｌ合金層は、例えば、スパッ
タ法により、Ａｌ−Ｓｉ合金（Ｓｉ：１％〜２％）、Ａ
ｌ−Ｓｉ−Ｃｕ合金（Ｓｉ：１％〜２％、Ｃｕ：０．１
％〜０．５％）を堆積して形成する。第１のバリアメタ
ル層としては、スパッタ法により、Ａｌ合金層の反射防
止膜としても用いられるＴｉＮ層を形成する。そして、
全面にＳｉＯ２膜／ＳｉＮ膜から成る層間絶縁膜３（膜
厚：８０００Å〜１００００Å）をＣＶＤ法により形成
する。Ａｌ電極パッド２上には、後に形成する配線層４
との電気的接続をとるために開口を設ける。First, as shown in FIG. 1, a metal electrode pad 2 composed of an Al alloy layer and a first barrier metal layer is formed on a semiconductor substrate 1. The Al alloy layer is formed of, for example, an Al-Si alloy (Si: 1% to 2%), A by a sputtering method.
1-Si-Cu alloy (Si: 1% to 2%, Cu: 0.1
% -0.5%) is deposited and formed. As the first barrier metal layer, a TiN layer which is also used as an antireflection film of an Al alloy layer is formed by a sputtering method. And
An interlayer insulating film 3 (thickness: 8000Å to 10000Å) made of a SiO 2 film / SiN film is formed on the entire surface by a CVD method. A wiring layer 4 to be formed later is formed on the Al electrode pad 2.
An opening is provided for electrical connection with.
【００１７】次に、図２に示すように、Ａｌ合金層と第
２のバリア層から成る配線層４を形成する。第２のバリ
ア層は、ＴｉＮから成り、後に形成する柱状端子と配線
層４との間に介在して、バリアメタルの働きをする。配
線層４は、上記開口を介して金属電極パッド２と接続さ
れる。この配線層４は、金属電極パッド２と同様のプロ
セスで形成することができる。Next, as shown in FIG. 2, a wiring layer 4 composed of an Al alloy layer and a second barrier layer is formed. The second barrier layer is made of TiN, and acts as a barrier metal by interposing between a columnar terminal formed later and the wiring layer 4. The wiring layer 4 is connected to the metal electrode pad 2 through the opening. The wiring layer 4 can be formed by the same process as the metal electrode pad 2.
【００１８】そして、全面にＳｉＮから成るパッシベー
ション膜５（膜厚：８０００Å〜１００００Å）をＣＶ
Ｄ法により形成する。金属電極パッド２上のパッシベー
ション膜５には第１の開口部６をエッチングにより設け
る。Then, a CV passivation film 5 (film thickness: 8000Å to 10000Å) made of SiN is formed on the entire surface.
It is formed by the D method. A first opening 6 is provided in the passivation film 5 on the metal electrode pad 2 by etching.
【００１９】次に、図３に示すように、全面にポリイミ
ド層７を塗布形成し、露光・現像処置により、第１の開
口部６上の前記ポリイミド層７に第２の開口部８を設け
る。ここで、後に形成する柱状端子をできるだけ長くす
るために、ポリイミド層７はできる限り厚く形成するこ
とが望まれる。そこで、ポリイミド層７は、感度の良い
ネガ系ポリイミドを用いるとよい。これにより、２０μ
〜２５μの膜厚を有するポリイミド層７を形成し、加工
することができる。Next, as shown in FIG. 3, a polyimide layer 7 is applied and formed on the entire surface, and a second opening 8 is formed in the polyimide layer 7 on the first opening 6 by exposing and developing. . Here, in order to make the columnar terminals formed later be as long as possible, it is desired that the polyimide layer 7 be formed as thick as possible. Therefore, the polyimide layer 7 is preferably made of a negative sensitive polyimide having high sensitivity. With this, 20μ
The polyimide layer 7 having a film thickness of ˜25 μ can be formed and processed.
【００２０】次に、図４に示すように、Ｃｕから成るメ
ッキ用電極層９（膜厚：１０００Å〜２０００Å）をス
パッタ法により形成した後に、図５に示すように、第２
の開口部６を露出させるように、ホトレジスト層１０を
メッキ用電極層９上に形成し、電解メッキにより、第１
の開口部６および第２の開口部８にＣｕから成る柱状端
子１１（メタル・ポスト）を形成する。続いて、柱状端
子１１上に電解メッキにより、Ａｕ層／Ｎｉ層からなる
第３のバリアメタル層１２、半田バンプ１３を形成す
る。Next, as shown in FIG. 4, a plating electrode layer 9 (film thickness: 1000Å to 2000Å) made of Cu is formed by a sputtering method, and then a second electrode is formed as shown in FIG.
Forming a photoresist layer 10 on the electrode layer 9 for plating so as to expose the opening 6 of
A columnar terminal 11 (metal post) made of Cu is formed in the opening 6 and the second opening 8. Then, a third barrier metal layer 12 composed of an Au layer / Ni layer and a solder bump 13 are formed on the columnar terminal 11 by electrolytic plating.
【００２１】図６に示すように、ホトレジスト層１０を
除去し、さらにメッキ用電極層９の不要部分をエッチン
グ除去する。この後、半導体基板１をスクライブ工程で
チップに分割して、チップサイズパッケージを完成す
る。なお、半田バンプ１３は、電解メッキで形成せず、
半田を柱状端子１１にＳＭＴ技術を用いて機械的に固着
して形成してもよい。As shown in FIG. 6, the photoresist layer 10 is removed, and unnecessary portions of the plating electrode layer 9 are removed by etching. After that, the semiconductor substrate 1 is divided into chips by a scribing process to complete a chip size package. The solder bumps 13 are not formed by electrolytic plating,
The solder may be mechanically fixed to the columnar terminals 11 by using the SMT technique.
【００２２】図７は、チップサイズパッケージの平面図
である。同図に示すように、半田バンプ１３と金属電極
パッド２とを接続する配線層４に複数のスリット１４
（配線層を貫通する孔）を設けることにより、熱ストレ
スなどに対する機械的強度を向上することができる。こ
れは、配線層４自体だけでなく、配線層４の下層にある
ＬＳＩの配線やデバイスへのストレスを緩和する働きを
する。このスリットは、配線層４をエッチングによりパ
ターニングするときに同時に形成する。FIG. 7 is a plan view of the chip size package. As shown in the figure, a plurality of slits 14 are formed in the wiring layer 4 connecting the solder bumps 13 and the metal electrode pads 2.
By providing (a hole penetrating the wiring layer), mechanical strength against heat stress and the like can be improved. This serves to relieve stress not only on the wiring layer 4 itself but also on the wiring and devices of the LSI underlying the wiring layer 4. This slit is formed at the same time when the wiring layer 4 is patterned by etching.
【００２３】次に、本発明の第２の実施例を図８乃至図
１２を参照しながら説明する。半導体基板上１１上に金
属電極層１２、層間絶縁膜１３、配線層１４を形成する
ところは第１の実施例と同様である。この実施例では、
配線層１４をＡｌ合金単層で構成したところが異なる。
図８に示すように、全面にＳｉＮから成るパッシベーシ
ョン膜１５（膜厚：８０００Å〜１００００Å）をＣＶ
Ｄ法により形成する。金属電極パッド１２上のパッシベ
ーション膜１５には第１の開口部１６をエッチングによ
り設ける。Next, a second embodiment of the present invention will be described with reference to FIGS. The metal electrode layer 12, the interlayer insulating film 13, and the wiring layer 14 are formed on the semiconductor substrate 11 as in the first embodiment. In this example,
The difference is that the wiring layer 14 is composed of an Al alloy single layer.
As shown in FIG. 8, a CV passivation film 15 (film thickness: 8000Å to 10000Å) made of SiN is formed on the entire surface.
It is formed by the D method. A first opening 16 is formed in the passivation film 15 on the metal electrode pad 12 by etching.
【００２４】次に、図９に示すように、全面にポリイミ
ド層１７を塗布形成し、露光・現像処置により、第１の
開口部１６上の前記ポリイミド層１７に第２の開口部１
８を設ける。ここで、ポリイミド層１７として、第１の
実施例と同様の理由によりネガ系ポリイミドを用いると
よい。Next, as shown in FIG. 9, a polyimide layer 17 is applied and formed on the entire surface, and exposure / development processing is performed to form the second opening 1 in the polyimide layer 17 on the first opening 16.
8 is provided. Here, a negative polyimide is preferably used as the polyimide layer 17 for the same reason as in the first embodiment.
【００２５】次に、図１０に示すように、第２の開口部
１８上に第３の開口部１９を有するホトレジスト層２０
を形成した後に、メッキ用電極層２１をスパッタ法によ
り形成する。メッキ用電極層２１は、Ｃｕ層／Ｃｒ層の
２層構造から成り、配線層１４と後に形成する柱状端子
２３との間に介在する部分が第２のバリアメタル層２４
として働く。Next, as shown in FIG. 10, a photoresist layer 20 having a third opening 19 on the second opening 18.
After forming, the plating electrode layer 21 is formed by the sputtering method. The plating electrode layer 21 has a two-layer structure of a Cu layer / Cr layer, and a portion interposed between the wiring layer 14 and a columnar terminal 23 formed later is the second barrier metal layer 24.
Work as.
【００２６】次に、図１１に示すように、さらにホトレ
ジスト層２２を形成し、柱状端子形成領域を画定した後
に、電解メッキにより、Ｃｕから成る柱状端子２３、Ａ
ｕ層／Ｎｉ層から成る第３のバリアメタル層２５を形成
する。ここでは、いわゆるリフトオフ法を用いている。
これは、通常のエッチングでは、上記のＣｒ層が除去困
難だからである。Next, as shown in FIG. 11, a photoresist layer 22 is further formed to define a columnar terminal forming region, and then the columnar terminals 23 and A made of Cu are formed by electrolytic plating.
A third barrier metal layer 25 composed of u layer / Ni layer is formed. Here, a so-called lift-off method is used.
This is because the above Cr layer is difficult to remove by ordinary etching.
【００２７】次に、図１２に示すように、リフトオフに
より、ホトレジスト層２０，２２を除去すると同時にメ
ッキ用電極層２１の不要部分を除去する。以下の工程
は、第１の実施例と同様のため省略する。Then, as shown in FIG. 12, the photoresist layers 20 and 22 are removed by lift-off, and at the same time, unnecessary portions of the plating electrode layer 21 are removed. The subsequent steps are the same as those in the first embodiment, and will be omitted.
【００２８】[0028]
【発明の効果】本発明によれば、チップサイズパッケー
ジの信頼性を確保しながら、金属電極パッドとアレイ状
に配置される半田バンプとを結線する再配線層の形成工
程を既存のＳｉウエーハプロセスの工程フロー内に含め
ることが可能になり、工程の簡略化、後工程と前工程の
一体化を促進することができる。According to the present invention, the step of forming the rewiring layer for connecting the metal electrode pads and the solder bumps arranged in an array is performed with the existing Si wafer process while ensuring the reliability of the chip size package. Can be included in the process flow, and the simplification of the process and the integration of the post-process and the pre-process can be promoted.
【図１】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 1 is a cross-sectional view showing a chip size package and a manufacturing method thereof according to an embodiment of the present invention.
【図２】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 2 is a cross-sectional view showing a chip size package and a method of manufacturing the same according to an embodiment of the present invention.
【図３】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 3 is a cross-sectional view showing a chip size package and a method for manufacturing the same according to an exemplary embodiment of the present invention.
【図４】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 4 is a cross-sectional view showing a chip size package and a method for manufacturing the same according to an embodiment of the present invention.
【図５】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 5 is a cross-sectional view showing a chip size package and a method for manufacturing the same according to an exemplary embodiment of the present invention.
【図６】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 6 is a cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.
【図７】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す平面図である。FIG. 7 is a plan view showing a chip size package and a method of manufacturing the same according to an exemplary embodiment of the present invention.
【図８】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 8 is a cross-sectional view showing a chip size package and a method for manufacturing the same according to an embodiment of the present invention.
【図９】本発明の実施形態に係るチップサイズパッケー
ジ及びその製造方法を示す断面図である。FIG. 9 is a cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.
【図１０】本発明の実施形態に係るチップサイズパッケ
ージ及びその製造方法を示す断面図である。FIG. 10 is a cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.
【図１１】本発明の実施形態に係るチップサイズパッケ
ージ及びその製造方法を示す断面図である。FIG. 11 is a cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.
【図１２】本発明の実施形態に係るチップサイズパッケ
ージ及びその製造方法を示す断面図である。FIG. 12 is a cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.
【図１３】従来例に係るチップサイズパッケージの製造
方法を示す断面図である。FIG. 13 is a cross-sectional view showing a method of manufacturing a chip size package according to a conventional example.
【図１４】従来例に係るチップサイズパッケージの製造
方法を示す断面図である。FIG. 14 is a cross-sectional view showing a method of manufacturing a chip size package according to a conventional example.
【図１５】従来例に係るチップサイズパッケージの製造
方法を示す断面図である。FIG. 15 is a cross-sectional view showing a method of manufacturing a chip size package according to a conventional example.
【図１６】従来例に係るチップサイズパッケージの製造
方法を示す断面図である。FIG. 16 is a cross-sectional view showing a method of manufacturing a chip size package according to a conventional example.
【図１７】従来例に係るチップサイズパッケージの製造
方法を示す断面図である。FIG. 17 is a cross-sectional view showing the method of manufacturing the chip size package according to the conventional example.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平８−45990（ＪＰ，Ａ) 特開 平６−53211（ＪＰ，Ａ) 特開 平９−107048（ＪＰ，Ａ) 特開2000−36509（ＪＰ，Ａ) 特開2000−91339（ＪＰ，Ａ) 特開 平９−64049（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/312 H01L 23/12 501 ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-8-45990 (JP, A) JP-A-6-53211 (JP, A) JP-A-9-1007048 (JP, A) JP-A-2000-36509 (JP, A) JP 2000-91339 (JP, A) JP 9-64049 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 21/312 H01L 23/12 501
Claims (3)
リアメタル層から成る金属電極パッドを形成する工程
と、前記金属電極パッド上に開口を有する層間絶縁膜を
形成する工程と、Ａｌ合金層の単層から成る配線層を形
成する工程と、全面にパッシベーション膜を形成する工
程と、前記配線層上の前記パッシベーション膜に第１の
開口部を設ける工程と、全面にポリイミド層を形成する
工程と、前記第１の開口部上の前記ポリイミド層に第２
の開口部を設ける工程と、前記第２の開口部上に第３の
開口部を有するホトレジスト層を形成する工程と、全面
にＣｕ層とＣｒ層の２層構造から成るメッキ用電極層を
形成する工程と、電解メッキ法により前記第１および第
２の開口部にＣｕから成る柱状端子を形成する工程と、
リフトオフにより前記ホトレジスト層およびメッキ用電
極層の不要部分を除去する工程とを有することを特徴と
するチップサイズパッケージの製造方法。 1. An Al alloy layer and a first bar on a semiconductor substrate.
Process of forming metal electrode pad composed of rear metal layer
And an interlayer insulating film having an opening on the metal electrode pad.
Forming process and forming a wiring layer consisting of a single Al alloy layer
And the process of forming a passivation film on the entire surface
The first passivation film on the wiring layer.
Step of forming an opening and forming a polyimide layer on the entire surface
And a second step on the polyimide layer on the first opening.
And the step of providing a third opening on the second opening.
The process of forming a photoresist layer having an opening and the entire surface
And a plating electrode layer consisting of a two-layer structure of a Cu layer and a Cr layer.
The step of forming and the first and the second by the electroplating method.
A step of forming a columnar terminal made of Cu in the second opening,
By lift-off, the photoresist layer and plating
And a step of removing an unnecessary portion of the polar layer.
Method for manufacturing chip size package.
設けたことを特徴とする請求項１に記載のチップサイズ
パッケージの製造方法。 2. The wiring layer has a plurality of slits when seen in a plan view.
The chip size according to claim 1, wherein the chip size is provided.
Package manufacturing method.
ｌ−Ｓｉ−Ｃｕ合金であることを特徴とする請求項１記
載のチップサイズパッケージの製造方法。 3. The Al alloy layer is an Al--Si alloy or A
It is an l-Si-Cu alloy, The claim 1 statement characterized by the above-mentioned.
Manufacturing method of chip size package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35178398A JP3389517B2 (en) | 1998-12-10 | 1998-12-10 | Chip size package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35178398A JP3389517B2 (en) | 1998-12-10 | 1998-12-10 | Chip size package and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000183090A JP2000183090A (en) | 2000-06-30 |
| JP3389517B2 true JP3389517B2 (en) | 2003-03-24 |
Family
ID=18419584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35178398A Expired - Fee Related JP3389517B2 (en) | 1998-12-10 | 1998-12-10 | Chip size package and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3389517B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11387192B2 (en) | 2019-12-31 | 2022-07-12 | Samsung Electronics Co., Ltd. | Semiconductor package |
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|---|---|---|---|---|
| KR100377127B1 (en) * | 2000-10-10 | 2003-03-26 | 임관일 | Method for fabricating a chip size package in a wafer level |
| JP3848080B2 (en) * | 2000-12-19 | 2006-11-22 | 富士通株式会社 | Manufacturing method of semiconductor device |
| DE10231385B4 (en) | 2001-07-10 | 2007-02-22 | Samsung Electronics Co., Ltd., Suwon | Semiconductor chip with bond pads and associated multi-chip package |
| JP2004273591A (en) * | 2003-03-06 | 2004-09-30 | Seiko Epson Corp | Semiconductor device and its fabricating process |
| JP4119866B2 (en) | 2004-05-12 | 2008-07-16 | 富士通株式会社 | Semiconductor device |
| US8022544B2 (en) | 2004-07-09 | 2011-09-20 | Megica Corporation | Chip structure |
| US7452803B2 (en) | 2004-08-12 | 2008-11-18 | Megica Corporation | Method for fabricating chip structure |
| JP4777644B2 (en) * | 2004-12-24 | 2011-09-21 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
| TWI330863B (en) | 2005-05-18 | 2010-09-21 | Megica Corp | Semiconductor chip with coil element over passivation layer |
| US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
| TWI305951B (en) | 2005-07-22 | 2009-02-01 | Megica Corp | Method for forming a double embossing structure |
| JP5107529B2 (en) | 2006-05-09 | 2012-12-26 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2008283216A (en) * | 2008-07-28 | 2008-11-20 | Oki Electric Ind Co Ltd | Semiconductor device, and manufacturing method thereof |
| KR101032706B1 (en) * | 2008-09-08 | 2011-05-06 | 삼성전기주식회사 | Semiconductor package and method of manufacturing the same |
| JP5908218B2 (en) * | 2011-05-10 | 2016-04-26 | エスアイアイ・セミコンダクタ株式会社 | Optical sensor and optical sensor manufacturing method |
-
1998
- 1998-12-10 JP JP35178398A patent/JP3389517B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11387192B2 (en) | 2019-12-31 | 2022-07-12 | Samsung Electronics Co., Ltd. | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000183090A (en) | 2000-06-30 |
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