JPS63253598A - Rom device - Google Patents

Abstract

PURPOSE:To reduce the electric current consumption of a ROM device, by setting the ROM device to its operating state only when address signals change and to a standby state when no change takes place in the address signals. CONSTITUTION:When delaying pulses 47 are added to a clock inputting terminal, an address holding circuit 1 fetches and holds address inputting signals 21 and uses the holding content as address signals 22. A discordance detecting circuit 2 compares the signals 22 with address inputting signals 31 and, when they coincide with each other, sets low-level signals to discordance signals 33. When they do not coincide with each other, the circuit 2 sets high-level signals to the discordance signals 33. A delaying pulse generating circuit 6 generates delaying pulses 44 of a 1st stage and delaying pulses 47 of a 2nd stage from change in the discordance signal. An output data holding circuit 7 holds the output data of a ROM 8 by using the pulses 44 as clock input and sets the holding content as output data 52. When the current address input signal 31 coincides with the last address signal 22 and when a standby requesting signal is inputted from the outside to an input terminal 4, the ROM 8 is set to a standby state by the output of a NAND gate 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a ROM using a current sense type sense amplifier.
Regarding equipment.

[Conventional technology]

Generally, when a ROM device is used asynchronously, it needs to be able to be referenced at any time.

FIG. 6 shows an example of a ROM using a general current sense type sense amplifier.

In the conventional ROM device, when the ROM is placed in a standby state, the standby request terminal 18 is set to a high level in FIG. 6, and when the ROM is placed in an operating state, the standby request terminal 18 is always set to a low level. .

In the operating state, the input to the gate terminal of the N-channel MOS transistor 11 is in the form of negative feedback from the point a, and the levels at the point a and the gate terminal are balanced. Since the level at this time is intermediate,
Current flows through P-channel MOS transistor 12. Further, the gate terminal of P-channel MOS transistor 13 also becomes an intermediate level, and current flows through N-channel MOS transistor 14. Furthermore, since point a, which is the input to the NOR gate 15, is at an intermediate level, this NOR
A current also flows inside the R gate 15.

[Problem that the invention seeks to solve]

Although the ROM device using the conventional current sense type sense amplifier described above could be put into a standby state (
For example, by inputting a high level to the standby request terminal 18 in FIG. ), it is difficult to make it active only when it is referenced when operating asynchronously, so it must be in the active state at all times so that it can be referenced at any time, and as a result, current always flows. This has the disadvantage that current consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ROM device that can solve the above-mentioned drawbacks and reduce current consumption.

[Problem that the invention seeks to solve]

The ROM device of the present invention has an address holding circuit that holds an address signal from the previous reference, and detects a mismatch by comparing the address signal held by the address holding circuit from the previous reference with the current address signal. A mismatch detection circuit, a delayed pulse generation circuit that generates a single pulse delayed in two stages from a change in the mismatch signal generated when the mismatch detection circuit detects a mismatch, and a delayed pulse generation circuit that generates a first stage delayed pulse generated by the delayed pulse generation circuit. An output data holding circuit that holds the output data of the ROM as a clock input is provided, and the second stage delay pulse generated by the delayed pulse generation circuit is used as the clock for the address holding circuit, and the above part is operated without an external standby request. The ROM is configured to be activated only when a match signal is generated.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In this embodiment, address holding circuit 1. Mismatch detection circuit 2.
Delayed pulse generation circuit 6. Output data holding circuit 7. ROM
8. It is composed of a NAND gate 3 and an inverter 5.

As shown in detail in FIG. 2, the address holding circuit 1 includes D-type flip-flops 2 equal to the number of address signals.
4, and a delay pulse 47, which will be described later, is connected to the clock input terminal.
When is applied, the address input signal 21 is captured and held,
The held content is assumed to be the address signal 22.

As shown in detail in FIG. 3, the mismatch detection circuit 2 consists of exclusive OR circuits 34 and one OR circuit 35, the number of which is equal to the number of address signals. are compared, and if they match, the low level is set, and if they do not match, the high level is set as the mismatch signal 33. The address signal 22 and the address input signal 31 are the address signal at the previous reference held by the address holding circuit 1 (hereinafter referred to as the previous address signal) and the current address input signal.

The delayed pulse generating circuit 4 generates a fixed length pulse delayed in two steps from the change of the mismatch signal from low level to high level, and as shown in detail in FIG. , two one-pulse generating circuits 4
3 and 46.

The mismatch signal 33 is delayed by a delay circuit 42, and a one-pulse generation circuit 43 generates one pulse from the change of the output of the delay circuit 42 from low level to high level,
The pulse is output as the first stage delayed pulse 44.

Also, the mismatch signal 33 delayed by the delay circuit 42
is further delayed by a delay circuit 45, and a one-pulse generation circuit 46 generates one pulse from the change of the output of the delay circuit 45 from low level to high level, and this pulse is output as a second-stage delayed pulse 47. This delayed pulse 47 is supplied to the clock input terminal of the address holding circuit 1 as a clock.

The output data holding circuit 7 receives the delayed pulse 44 generated by the delayed pulse generating circuit 6 as a clock input and outputs the RO.
It holds the output data of M8, and as shown in FIG. When a delay pulse 44 is applied to the clock input terminal, input data 51 is taken in and held, and the held contents are used as output data 52.

The ROM 5 itself is the same as that shown in FIG. Previous address signal 22 given externally and current address input signal 3
1 match, the mismatch signal 33 from the mismatch detection circuit 2 becomes low level, and the output of the NAND gate 3 becomes high level. The output of NAND gate 3 is ROM
The ROM 8 is connected to the standby request terminal 18 of the ROM 8, and the ROM 8 enters a standby state, thereby reducing current consumption.

Also, when there is a standby request from the outside, the standby request signal input terminal 4 from the outside is at a high level, the output of the inverter 5 is at a low level, and the output of the NAND gate 3 is at a high level, and the ROM 8 is placed in a standby state.

When there is no standby request from the outside and the previous address signal and the current address signal do not match, that is, when the address signal changes, the standby request signal input terminal 4 from the outside goes low level and the output of the inverter 5 goes low. The mismatch signal 33 becomes high level, the output of the NAND gate 3 becomes low level, and the ROM 8 becomes operational.

At this time, when the mismatch signal 33 changes from low level to high level, the first stage delay pulse 44 generated by the delay pulse generation circuit 6 causes the output data holding circuit 7 to store the output data of the ROIVI 8 corresponding to the new address signal. Hold.

Furthermore, the second stage delay pulse 47 generated by the delay pulse generation circuit 6 causes the address holding circuit 1 to newly take in and hold the current address. At this point, the address signal 22 held by the address holding circuit 1 matches the current address signal, so the mismatch signal 33 is at low level.
The output of NAND gate 3 becomes high level, and ROM8
is again in a standby state.

〔Effect of the invention〕

As is clear from the above explanation, according to the ROM device of the present invention, the ROM is put into the operating state only when there is a change in the address signal, and the ROM is put into the standby state when there is no change in the address signal. The effect of reducing current consumption can be obtained by cutting off the current that is constantly consumed.

In particular, when a customer connects and uses their own ROM and other circuits, such as in a custom LSI, it is possible to reduce the current consumption when the ROM is not used without requiring special consideration, which is a very significant effect. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a ROM device according to an embodiment of the present invention, and FIGS. 2, 3, 4, and 5 are respectively an address holding circuit, a mismatch detection circuit, and
A detailed circuit diagram of a delayed pulse generation circuit and an output data holding circuit, and FIG. 6 are circuit examples of a ROM device using a general current sense type sense amplifier. 1... Address holding circuit, 2... Mismatch detection circuit,
3...NAND gate, 5...Inverter, 6...
・Delayed pulse generation circuit, 7...output data holding circuit,
8...ROM, 11.14-N channel MOS transistor, 12,13.17...P channel MOS
Transistor, 15...NOR gate, 16...R
OM cell, 42.45...Delay circuit, 43.46...
・One pulse generation circuit.

Claims (1)

[Claims] In a ROM device using a current sense type sense amplifier, there is provided an address holding circuit that holds an address signal from the previous reference, and an address signal held by the address holding circuit from the previous reference. a mismatch detection circuit that detects a mismatch by comparing the current address signal with the current address signal; and a delayed pulse generation circuit that generates a one-pulse delayed by two stages from a change in the mismatch signal that occurs when the mismatch detection circuit detects the mismatch. and an output data holding circuit that uses the first stage delay pulse generated by the delay pulse generation circuit as a clock input and holds the output data of the ROM, and the second stage delay pulse generated by the delay pulse generation circuit is A ROM device characterized in that the ROM is configured to be used as a clock for the address holding circuit and to enter an operating state only when the mismatch signal is generated without an external standby request.