JPS63237408A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JPS63237408A JPS63237408A JP62070220A JP7022087A JPS63237408A JP S63237408 A JPS63237408 A JP S63237408A JP 62070220 A JP62070220 A JP 62070220A JP 7022087 A JP7022087 A JP 7022087A JP S63237408 A JPS63237408 A JP S63237408A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- grooves
- thin film
- silicon single
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000010409 thin film Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 4
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 2
- 239000007853 buffer solution Substances 0.000 abstract 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体デバイス用基板に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a substrate for semiconductor devices.
従来半導体デバイスを製造する一方法として、保持基板
上にシリコン酸化膜を介してシリコン単結晶の薄膜を接
合した直径数士鶴のSOI (Sen+1−condu
ctor on In5ujator)基板の単結晶
薄膜上に多数の電気回路を形成させた後数鰭角に切断す
る方法がある。そして基板1を回転刃3を使用したダイ
シングソーで切断する際に第4図のようにシリコン単結
晶薄膜2に欠損が生ずる云わゆ−るチッピングが起ると
、電気回路が損傷を受け、動作不良や動作不能になる問
題があった。Conventionally, as a method for manufacturing semiconductor devices, SOI (Sen+1-condu), in which a thin film of silicon single crystal is bonded to a holding substrate via a silicon oxide film, is used.
There is a method in which a large number of electric circuits are formed on a single crystal thin film of a substrate and then cut into several angles. When the substrate 1 is cut with a dicing saw using the rotary blade 3, if so-called chipping occurs, which causes defects in the silicon single crystal thin film 2 as shown in FIG. There were problems that caused it to malfunction or become inoperable.
〔問題点を解決するための手段及び作用〕この発明は前
記の問題点を解決するために、SOI基板のシリコン単
結晶薄膜に予め切断パターンに沿った溝を設けるように
したものである。そして線溝の深さは薄膜の厚さより大
きく、その巾は切断機の刀の厚さより大きい寸法にして
おけば、切断する際に薄膜は損傷を受けることがなく、
従って電気回路もチッピングによる動作不良は生じない
。また、保持基板と薄膜の間は酸化膜で分離されており
、且つ各層間の結合力はシリコン単体中の結合力より弱
いので、切断時に保持基板に欠損が生じてもシリコン薄
膜迄伝搬することがない。[Means and operations for solving the problems] In order to solve the above-mentioned problems, the present invention is such that grooves are formed in advance along the cutting pattern in the silicon single crystal thin film of the SOI substrate. If the depth of the wire groove is greater than the thickness of the thin film and its width is greater than the thickness of the cutting machine's blade, the thin film will not be damaged during cutting.
Therefore, malfunctions due to chipping do not occur in the electric circuit. In addition, the holding substrate and the thin film are separated by an oxide film, and the bonding force between each layer is weaker than the bonding force in silicon itself, so even if a defect occurs in the holding substrate during cutting, it will not propagate to the silicon thin film. There is no.
〔実施例(1)〕
本発明のSOI基板の一実施例を図面によって説明する
。[Example (1)] An example of the SOI substrate of the present invention will be described with reference to the drawings.
第1図は本発明の501基板の平面図であり、第2図A
乃至Eは製造工程を示す図である。第2図Aのようにシ
リコン単結晶の基板4を空気中で加熱し、その表面に厚
さ1500A程度の5in2膜5を形成させる。次に生
成したSiO□膜5の表面にレジスト6を塗布したのち
第1図のような巾Wが約100ミクロンの所望切断パタ
ーンを露光処理し、緩衝ぶつ酸溶液でSiO□膜5をエ
ツチング処理し、B図のように溝7aを形成させる。次
にKOH水溶液中でエツチング処理すると0図のように
レジスト6と、基板4の露出部が深さ約5μ除去されて
溝7が形成される。次にD図のように溝7を形成した面
上に、A図と同じ基板のSiO□膜を接合する。最後に
E図のように溝7の裏側の面を研摩し厚さ5μ以下のシ
リコン単結晶薄膜4aとすれば所望パターンの溝7を設
けたsoi g板lが得られる。FIG. 1 is a plan view of the 501 substrate of the present invention, and FIG.
9 to E are diagrams showing manufacturing steps. As shown in FIG. 2A, a silicon single crystal substrate 4 is heated in air to form a 5in2 film 5 with a thickness of about 1500 Å on its surface. Next, a resist 6 is applied to the surface of the generated SiO□ film 5, and then a desired cutting pattern with a width W of about 100 microns as shown in Fig. 1 is exposed to light, and the SiO□ film 5 is etched with a buffered acid solution. Then, grooves 7a are formed as shown in Figure B. Next, by etching in a KOH aqueous solution, the resist 6 and the exposed portion of the substrate 4 are removed to a depth of about 5 μm to form a groove 7, as shown in FIG. Next, the SiO□ film of the same substrate as in Fig. A is bonded onto the surface on which the groove 7 is formed as shown in Fig. D. Finally, as shown in Fig. E, the surface on the back side of the grooves 7 is polished to form a silicon single crystal thin film 4a having a thickness of 5 μm or less, thereby obtaining a SOIG plate 1 having grooves 7 in a desired pattern.
このようにして製造されたSO1基板の溝7に沿ってグ
イシングツ−で切断したところ全くチッピングは発生せ
ず、良好な切断片が得られた。When the SO1 substrate manufactured in this way was cut with a cutting tool along the groove 7, no chipping occurred and a good cut piece was obtained.
〔実施例(2)〕
他の実施例を第3図によって説明する。先ずA図に示す
ように実施例+1)と同様な方法で表面にSiO□膜5
を形成させたシリコン単結晶基板4を二枚作る。[Embodiment (2)] Another embodiment will be described with reference to FIG. First, as shown in Figure A, a SiO□ film 5 is formed on the surface using the same method as in Example +1).
Two silicon single-crystal substrates 4 on which are formed are prepared.
次にB図のように二枚の基板のSiO□膜面を接合する
。そして一方の単結晶基板4を厚さ5μ以下のfH1i
4aとなるまで研磨する。その後この薄膜4a面に第1
図のような所望の切断パターンにパターニングを施し、
CF、ガス等でドライエツチングしてD図のような溝7
を設けた501基板lが得られた。Next, as shown in Figure B, the SiO□ film surfaces of the two substrates are bonded. Then, one single crystal substrate 4 is formed into an fH1i with a thickness of 5μ or less.
Polish until it reaches 4a. After that, a first
Pattern the desired cutting pattern as shown in the figure,
Dry etching with CF, gas, etc. to create grooves 7 as shown in figure D.
A 501 substrate l was obtained.
このようにして製造された501基板1の溝に沿ってグ
イシングツ−で切断したところ、全くチッピングは発生
せず、良好な切断片が得られた。When the 501 substrate 1 manufactured in this manner was cut with a cutting tool along the groove, no chipping occurred at all, and a good cut piece was obtained.
以上説明したようにこの発明はSO■基板のシリコン単
結晶薄膜に予め切断パターンに沿った溝を設けたので、
この溝に沿って切断すれば薄膜を損傷することなく切断
することができる。従ってこのSOI基板を使用しその
薄膜上に電気回路を形成して半導体ディバスを製造した
場合、切断時にチッピングによるデバイスの不良が発生
することがなく、製品の品質と歩留りの向上に極めて顕
著な成果かえられる。As explained above, in this invention, grooves are formed in advance along the cutting pattern in the silicon single crystal thin film of the SO■ substrate.
By cutting along this groove, the thin film can be cut without damaging it. Therefore, when this SOI substrate is used and an electric circuit is formed on the thin film to manufacture a semiconductor device, device defects due to chipping do not occur during cutting, resulting in extremely significant improvements in product quality and yield. I can be hatched.
第1図は本発明のSo1基板の平面図であり、第2.3
図は本発明のSO1基板の製造工程を示す図、第4図は
切断状況を示す図である。
1・・・So1基板、2,4a・・・シリコン単結晶薄
膜、4・・・シリコン単結晶基板、5・・・シリコン酸
化膜、7.7a・・・溝。
特許出願人 住友金属鉱山株式会社
第1図
第4図Fig. 1 is a plan view of the So1 substrate of the present invention, and Fig. 2.3 is a plan view of the So1 substrate of the present invention.
The figure shows the manufacturing process of the SO1 substrate of the present invention, and FIG. 4 shows the cutting situation. DESCRIPTION OF SYMBOLS 1... So1 substrate, 2,4a... Silicon single crystal thin film, 4... Silicon single crystal substrate, 5... Silicon oxide film, 7.7a... Groove. Patent applicant Sumitomo Metal Mining Co., Ltd. Figure 1 Figure 4
Claims (1)
の薄膜を接合したSOI基板において、前記シリコン単
結晶側に、基板の切断パターンに沿って溝を設けたこと
を特徴とする半導体デバイス用基板。1. A substrate for a semiconductor device, characterized in that, in an SOI substrate in which a thin film of silicon single crystal is bonded to a holding substrate via a silicon oxide film, a groove is provided on the silicon single crystal side along a cutting pattern of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62070220A JPS63237408A (en) | 1987-03-26 | 1987-03-26 | Substrate for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62070220A JPS63237408A (en) | 1987-03-26 | 1987-03-26 | Substrate for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63237408A true JPS63237408A (en) | 1988-10-03 |
Family
ID=13425245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62070220A Pending JPS63237408A (en) | 1987-03-26 | 1987-03-26 | Substrate for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63237408A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5466631A (en) * | 1991-10-11 | 1995-11-14 | Canon Kabushiki Kaisha | Method for producing semiconductor articles |
JP2001015683A (en) * | 1999-04-02 | 2001-01-19 | Interuniv Micro Electronica Centrum Vzw | Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9431368B2 (en) | 1999-10-01 | 2016-08-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5852846A (en) * | 1981-09-25 | 1983-03-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS615544A (en) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-03-26 JP JP62070220A patent/JPS63237408A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5852846A (en) * | 1981-09-25 | 1983-03-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS615544A (en) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5466631A (en) * | 1991-10-11 | 1995-11-14 | Canon Kabushiki Kaisha | Method for producing semiconductor articles |
JP2001015683A (en) * | 1999-04-02 | 2001-01-19 | Interuniv Micro Electronica Centrum Vzw | Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same |
US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
US9564414B2 (en) | 1999-10-01 | 2017-02-07 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US9431368B2 (en) | 1999-10-01 | 2016-08-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US8053329B2 (en) | 2000-02-16 | 2011-11-08 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7335572B2 (en) | 2000-02-16 | 2008-02-26 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7387944B2 (en) | 2000-02-16 | 2008-06-17 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9082627B2 (en) | 2000-02-16 | 2015-07-14 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9331149B2 (en) | 2000-02-16 | 2016-05-03 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9391143B2 (en) | 2000-02-16 | 2016-07-12 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US10312217B2 (en) | 2000-02-16 | 2019-06-04 | Invensas Bonding Technologies, Inc. | Method for low temperature bonding and bonded structure |
US7037755B2 (en) | 2000-03-22 | 2006-05-02 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6627531B2 (en) | 2000-03-22 | 2003-09-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
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