JPH0387012A - Adhered wafer and manufacture thereof - Google Patents
Adhered wafer and manufacture thereofInfo
- Publication number
- JPH0387012A JPH0387012A JP15930190A JP15930190A JPH0387012A JP H0387012 A JPH0387012 A JP H0387012A JP 15930190 A JP15930190 A JP 15930190A JP 15930190 A JP15930190 A JP 15930190A JP H0387012 A JPH0387012 A JP H0387012A
- Authority
- JP
- Japan
- Prior art keywords
- bonded wafer
- substrate
- wafer
- bonded
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 115
- 235000012431 wafers Nutrition 0.000 claims description 96
- 238000000034 method Methods 0.000 claims description 39
- 238000000227 grinding Methods 0.000 claims description 29
- 238000005498 polishing Methods 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 22
- 239000010409 thin film Substances 0.000 claims description 3
- 238000005336 cracking Methods 0.000 abstract description 8
- 238000005520 cutting process Methods 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 description 13
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000000428 dust Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
接合ウェハおよびその製造方法、特に高品質なシリコン
・オン・インシュレータ(Silicon onIns
ulator、 5ol)ウェハを得るためのSOIウ
ェハの構造とその製造方法に関し、
接合Solの製造において、素子基板の端面に鋭角な段
差が生じることによる素子基板の欠けとゴミの発生、お
よび素子基板の割れを防止することができる構造のSO
Iとそれの製造方法を提供することを目的とし、
2枚以上のウェハを接合した後に生じる接合ウェハの不
連続な端面を端面研削処理によって連続した丸めの端面
とすることを特徴とする接合ウニへの製造方法、および
素子を形成すべき基板および該基板を支持すべき基板を
接合して得られる接合ウェハの端面が連続した曲面を有
することを特徴とする接合ウェハを含み構成する。[Detailed Description of the Invention] [Summary] Bonded wafers and methods of manufacturing the same, particularly high quality silicon on insulators.
Regarding the structure of an SOI wafer and its manufacturing method for obtaining a SOI wafer (ulator, 5ol), in the manufacturing of bonded Sol, chipping of the element substrate and generation of dust due to sharp steps on the end face of the element substrate, and generation of dust on the element substrate. SO with a structure that can prevent cracking
The object of the present invention is to provide a bonded wafer I and a method for manufacturing the same, which is characterized in that a discontinuous end surface of a bonded wafer that occurs after bonding two or more wafers is made into a continuous rounded end surface by an edge grinding process. and a bonded wafer characterized in that the end surface of the bonded wafer obtained by bonding a substrate on which an element is to be formed and a substrate to support the substrate has a continuous curved surface.
本発明は接合ウェハおよびその製造方法、特に高品質な
シリコン・オン・インシュレータ(Sil−icon
on In5ulator、 501)ウェハを得るた
めのS○Iウェハの構造とその製造方法に関する。The present invention relates to a bonded wafer and a method for manufacturing the same, particularly a high quality silicon-on-insulator (Sil-icon).
on In5lator, 501) relates to the structure of an S○I wafer for obtaining a wafer and its manufacturing method.
近年の半導体の利用分野は拡大して増々高性能、高品質
なものが求められ、特に、高速化と耐環境化されたデバ
イスが要求されている。このため、S○■基板を用いた
デバイスが提供されているが、通常のシリコン基板(ウ
ェハ)並みの結晶性が得られず、形成される素子の特性
や歩留りが良くないので、SOIウェハの結晶性を向上
させる方法が要請されている。In recent years, the field of use of semiconductors has expanded, and higher performance and higher quality are required. In particular, devices with higher speed and environmental resistance are required. For this reason, devices using SOI wafers have been provided, but they do not have the same crystallinity as ordinary silicon substrates (wafers), and the characteristics and yield of the formed elements are poor. There is a need for a method to improve crystallinity.
従来のSOIウェハにおいては、メルト法、SI MO
X (Separation by 1wplante
d Oxygen)法、そして接合法(貼合わせ法)等
が知られている。For conventional SOI wafers, melt method, SI MO
X (Separation by 1wplante
d Oxygen) method, bonding method (bonding method), etc. are known.
しかし、メルト法、SIMOX法は各れもその製造法の
原理的な問題から、良質な結晶を得ることが極めて難し
いとされている。一方、接合法は、良質な結晶同士を接
着させるので、良質なSol基板が得られるという利点
がある。However, it is said that it is extremely difficult to obtain high-quality crystals in both the melt method and the SIMOX method due to fundamental problems in their manufacturing methods. On the other hand, the bonding method has the advantage that a high quality Sol substrate can be obtained since high quality crystals are bonded together.
多層LSI構造に有利なメルト法を第4図を参照して説
明すると、第4図(a)の模式的な斜視図に示されるよ
うに、表面にsho、膜32が形成されたウェハ31に
複数個の島33を形成する。島33は図面の簡略化のた
め6個しか示していないが、実際にはもっと多くの島が
ウェハ31全面にわたって形成される。この島33に単
結晶シリコン領域を形成してデバイスを作るのである。The melting method, which is advantageous for multilayer LSI structures, will be explained with reference to FIG. 4. As shown in the schematic perspective view of FIG. A plurality of islands 33 are formed. Although only six islands 33 are shown to simplify the drawing, more islands are actually formed over the entire surface of the wafer 31. A device is fabricated by forming a single crystal silicon region on this island 33.
第4図(b)は島33の部分の断面図で、sorを作る
ために、全面に多結晶シリコン(ポリシリコン)34を
堆積し、次いでレーザビームを照射してポリシリコンを
溶融すると、第4図(C)に示されるように、溶融され
たポリシリコンは島33内に流れ込み、次いで再結晶化
して単結晶シリコン層36となる。FIG. 4(b) is a cross-sectional view of the island 33. In order to make a sor, polycrystalline silicon (polysilicon) 34 is deposited on the entire surface, and then a laser beam is irradiated to melt the polysilicon. As shown in FIG. 4(C), the melted polysilicon flows into the islands 33 and is then recrystallized to become a single crystal silicon layer 36.
このメルト法においては、図に線で示す結晶欠陥37が
Sin、膜32から発生し、例えば島33が10口の大
きさのものである場合、周辺から2 、5 **程度は
結晶欠陥が多く、その結果島の寸法の約374において
単結晶シリコン領域を作ることができないという歩留り
上の問題がある。In this melt method, crystal defects 37 shown by lines in the figure are generated from the Sin film 32. For example, if the island 33 has a size of 10 holes, the crystal defects 37 from the periphery are about 2.5**. As a result, there is a yield problem in that it is not possible to create single crystal silicon regions at approximately 374 cm in island size.
SIMOX法では、第5図を参照すると、先ず第5図(
a)に示されるように、シリコン基板(ウェハ)41に
酸素イオン(○+)を上から注入し、シリコン基板41
の深さのほぼ中央部分に打ち込んで酸素注入層42(図
に短い線を交叉させて示す)を形成する。In the SIMOX method, referring to Figure 5, first of all, Figure 5 (
As shown in a), oxygen ions (○+) are implanted into the silicon substrate (wafer) 41 from above, and the silicon substrate 41
An oxygen implantation layer 42 (shown as crossed by short lines in the figure) is formed by implanting the oxygen implantation layer 42 approximately at the center of the depth.
次いで、第5図(b)に示すように、1200−125
0℃のアニールを行うと、酸素注入層はSin、層43
となって、その上方に5OI44が作られる。Then, as shown in FIG. 5(b), 1200-125
When annealing is performed at 0°C, the oxygen implanted layer is made of Sin, and the layer 43
Therefore, 5OI44 is created above it.
しかし、この方法では、5OI44内に砂地で示すよう
に酸素45が残留し、シリコン中の酸素が結晶欠陥の原
因となるので、SIMOX法で高品質なSOIを得るこ
とは難しい。However, with this method, oxygen 45 remains in the 5OI 44 as shown by the sandy area, and oxygen in silicon causes crystal defects, so it is difficult to obtain high quality SOI using the SIMOX method.
そこで接合SO■が開発されるに至ったもので、この方
法では、表面を酸化した素子基板(素子を形成する方の
基板)とそれの支持基板とを接着した後に、素子基板の
表面を研削し、次いで周辺をエツチングし、最後に研磨
する方法を行う。This led to the development of bonding SO■, which involves bonding an element substrate with an oxidized surface (the substrate on which the element will be formed) and its supporting substrate, and then grinding the surface of the element substrate. Then, the surrounding area is etched and finally polished.
接合Solを第6図を参照してやや詳細に説明すると、
CZ法で引上げた単結晶シリコンのCZ結晶51の表面
には引上げに際してCZ結晶51を回転させるので多数
の筋52が形威されている(第6図(a))、そこで、
円筒加工によってCZ結晶51表面の面取りを行って表
面を均一に滑らかにする。(第6図(b))。次いで、
オリエンテーション・フラット加工〈オリフラ加工)に
よって第6図(C)に示すように、CZ結晶51の一側
面を除去する。The junction Sol will be explained in more detail with reference to FIG.
Since the CZ crystal 51 is rotated during pulling, many lines 52 are formed on the surface of the single-crystal silicon CZ crystal 51 pulled by the CZ method (Fig. 6(a)).
The surface of the CZ crystal 51 is chamfered by cylindrical processing to make the surface uniform and smooth. (Figure 6(b)). Then,
One side of the CZ crystal 51 is removed by orientation flat processing (orientation flat processing) as shown in FIG. 6(C).
次に、スライシングによって第6図(d)に示されるウ
ェハ53(厚さ約0.111)を作り、それの面取りを
行って第6図(e)に示すように、ウェハ53の端面を
丸くし、次いでラッピングによって第6図(f)に示さ
れる厚さ500〜700μmのウェハ53を作り、次い
で研磨によってウェハ53の表面をミラー表面にするゆ
ウェハの端面を面取りする理由は、ラフピングにおいて
砥粒のまわり込みを良くして砥粒の停滞を防止すること
に加え、でき上がったウェハの搬送、処理において、面
取りしてないとほぼ垂直な端面の形成する角がかけてゴ
ミを生じたリウエハが割れたりすることを回避するため
である。Next, a wafer 53 (thickness approximately 0.111 mm) as shown in FIG. 6(d) is made by slicing, and the end surface of the wafer 53 is rounded by chamfering as shown in FIG. 6(e). Then, by lapping, a wafer 53 having a thickness of 500 to 700 μm is made as shown in FIG. 6(f), and then by polishing, the surface of the wafer 53 is made into a mirror surface. In addition to preventing the abrasive grains from stagnation by improving the wraparound of the grains, during the transportation and processing of the finished wafer, if the edges are not chamfered, the corners formed by the almost vertical end faces will be bent and the re-wafers will be removed. This is to avoid cracking.
次に、面取り加工したウェハ53の表面を酸化してSi
ng膜54を形威し、かかるウェハ53の2枚を第6図
(g)に示すように接着する。図において、上方のもの
は素子基板53a、下方は支持基板53bであり、ウェ
ハの大きさ、酸化膜の膜厚は説明のため誇張して模式的
に画いである。ウェハ53の表面はミラー表面(鏡面仕
上げ)になっているので、素子基板53aと支持基板5
3bは室温で貼合わされる。次いで、1200℃のアニ
ールによってSiO□膜54に取込まれた空気に含まれ
る水分のうち水素を除去し、酸素とシリコンの結合によ
って素子基板53aと支持基板53bを強固に接合させ
る。Next, the surface of the chamfered wafer 53 is oxidized to form Si.
The NG film 54 is applied and two of the wafers 53 are bonded together as shown in FIG. 6(g). In the figure, the upper part is the element substrate 53a, the lower part is the support substrate 53b, and the size of the wafer and the thickness of the oxide film are exaggerated for illustration purposes. Since the surface of the wafer 53 has a mirror surface (mirror finish), the element substrate 53a and the support substrate 5
3b is laminated at room temperature. Next, hydrogen is removed from the moisture contained in the air taken into the SiO□ film 54 by annealing at 1200° C., and the element substrate 53a and the support substrate 53b are firmly bonded by the bond between oxygen and silicon.
次いで、ラッピングによって素子基板53aを上方から
研磨し、第6図(h)に示すように、SiO!膜54全
540.2〜10μm程度素子基板53a側を残す。そ
して、前記ラフピングによって鏡面仕上げされた素子基
板53aの表面上に次のエツチングによってマスク材と
なるテープ55を貼りつける。Next, the element substrate 53a is polished from above by lapping, and as shown in FIG. 6(h), SiO! Approximately 540.2 to 10 μm of the entire film 54 is left on the element substrate 53a side. Then, a tape 55 serving as a mask material is pasted on the surface of the element substrate 53a, which has been mirror-finished by the rough polishing, in the next etching process.
続いてウェットエツチングによってテープ55でマスク
されない周辺部分をエツチングする(第6図(i))。Subsequently, the peripheral portions not masked by the tape 55 are etched by wet etching (FIG. 6(i)).
この時、接着面での5i02膜の厚さは0.1〜5μm
程度となり、このSi0g膜がSOIのインシュレータ
である。At this time, the thickness of the 5i02 film on the adhesive surface is 0.1 to 5 μm.
This Si0g film is the insulator of SOI.
第6図(i)に示す周辺エツチング後の素子基板53a
を観察すると、その端面ばほぼ垂直になっていて鋭角な
段差が生じているので、上部の角の部分がウェハの洗浄
や搬送中に生じる振動によって他の物につき当たると角
の部分が欠け、場合によっては素子基板53aが割れる
ことが経験された。Element substrate 53a after peripheral etching shown in FIG. 6(i)
When observing the wafer, the end surface is almost vertical and there is a sharp step, so if the upper corner hits another object due to vibrations that occur during wafer cleaning or transportation, the corner will chip. It has been experienced that the element substrate 53a cracks in some cases.
また、第6図(h)に示される素子基板53aのラッピ
ングにおいて、素子基板53aの側面は同図に点線で示
す接着面56に対して鋭角になっているために、その部
分にラッピングに用いる砥粒がたまり、砥粒の流れが全
般的にみて均一でないので、ラフピングが均一に行われ
ず、ラッピング仕上げ面が完全なミラー表面にならない
問題も経験された。Furthermore, in the wrapping of the element substrate 53a shown in FIG. 6(h), since the side surface of the element substrate 53a is at an acute angle with respect to the adhesive surface 56 shown by the dotted line in the figure, the side surface of the element substrate 53a is used for wrapping. Because the abrasive particles accumulate and the flow of the abrasive particles is not uniform overall, problems were also experienced in which the rough lapping was not performed uniformly and the lapped surface did not become a perfect mirror surface.
そこで本発明は、接合Solの製造において、素子基板
の端面に鋭角な段差が生じることによる素子基板の欠け
とゴミの発生、および素子基板の割れを防止することが
できる構造のSolとそれの製造方法を提供することを
目的とする。Therefore, the present invention provides a Sol with a structure that can prevent chipping of the element substrate, generation of dust, and cracking of the element substrate due to the occurrence of sharp steps on the end face of the element substrate in the manufacture of the bonded Sol, and its manufacture. The purpose is to provide a method.
本発明による接合ウェハの製造方法は上記目的達成のた
め、2枚以上のウェハを接合した後に生じる接合ウェハ
の不連続な端面を端面研削処理によって連続した丸めの
端面とするものである。In order to achieve the above-mentioned objective, the method for manufacturing a bonded wafer according to the present invention is to turn the discontinuous end face of the bonded wafer that occurs after bonding two or more wafers into a continuous rounded end face by an end face grinding process.
本発明の接合ウェハの製造方法においては、接合ウェハ
の端面研削を行い、次いで素子を形成すべき基板を薄膜
化する場合であってもよく、前記接合ウェハの端面研削
後更に研磨する場合であってもよい。ここでの素子を形
成すべき基板の薄膜化としては研磨、または研削及び研
磨により行う場合が挙げられる。In the method for manufacturing a bonded wafer of the present invention, the edge of the bonded wafer may be ground, and then the substrate on which elements are to be formed may be thinned, or the bonded wafer may be further polished after the edge of the bonded wafer is ground. You can. The substrate on which the element is to be formed may be thinned by polishing, or by grinding and polishing.
本発明の接合ウェハの製造方法においては、接合ウェハ
の素子を形成すべき基板を薄膜化し、次いで接合ウェハ
の端面研削を行う場合であってもよく、前記接合ウェハ
の端面研削後更に研磨する場合であってもよい。ここで
の素子を形成すべき基板の薄膜化としては研磨、または
研削および研磨により行う場合が挙げられる。In the method for manufacturing a bonded wafer of the present invention, the substrate on which the elements of the bonded wafer are to be formed may be made into a thin film, and then the edge of the bonded wafer may be ground, and the bonded wafer may be further polished after the edge of the bonded wafer is ground. It may be. The substrate on which the element is to be formed may be thinned by polishing, or by grinding and polishing.
本発明による接合ウェハは上記目的達成のため、素子を
形成すべき基板および該基板を支持すべき基板を接合し
て得られる接合ウェハの端面が連続した曲面を有するも
のである。In order to achieve the above object, the bonded wafer according to the present invention is obtained by bonding a substrate on which elements are to be formed and a substrate to support the substrate, and the end surface of the bonded wafer has a continuous curved surface.
本発明の接合ウェハにおいては、素子を形成すべき基板
と該基板を支持すべき基板が絶縁膜を介して接合してい
る場合であってもよく、また、接合ウェハの端面が鏡面
になっている場合であってもよい。In the bonded wafer of the present invention, the substrate on which elements are to be formed and the substrate to support the substrate may be bonded via an insulating film, and the end surface of the bonded wafer may be mirror-finished. This may be the case.
第2図は本発明の原理図で、先ず、第2図(a)に示す
ように、素子を形成すべき基板(以下、素子基板という
)11と素子基板11を支持すべき基板(以下、支持基
板という) 12とを接着して接合ウェハ14を作る。FIG. 2 is a diagram showing the principle of the present invention. First, as shown in FIG. (referred to as a supporting substrate) 12 to form a bonded wafer 14.
次いで、第2図(b)に示すように、接合ウェハ14の
端面を面取りする。続いて、素子基板11を第1図(c
)に示すように、研削し研磨する。なお、ここでは接合
ウェハ14の端面を連続した曲面となるように面取りし
た後、素子基板11を薄膜化する場合であるが、素子基
板を薄膜化した後接合ウェハの端面を面取りする場合で
あってもよい。Next, as shown in FIG. 2(b), the end face of the bonded wafer 14 is chamfered. Subsequently, the element substrate 11 is shown in FIG.
) Grind and polish as shown. Here, the case is that the end face of the bonded wafer 14 is chamfered to form a continuous curved surface, and then the element substrate 11 is made into a thin film. You can.
すなわち本発明によると、接合した素子基板11と支持
基板12(接合ウェハ)の端面の形成する不連続面が端
面を丸めることによって連続した丸みをもった面となり
、従来のような鋭角な段差によって作られる角がなくな
るので、この接合soIの洗浄、搬送中の振動によって
端面が他の物に接触したとしても欠けたり割れたりする
ことが防止され、さらには素子基板の研磨が支障なく行
われ素子基板の表面が精度の高いミラー表面となるので
ある。In other words, according to the present invention, the discontinuous surface formed by the end surfaces of the bonded element substrate 11 and support substrate 12 (bonded wafer) becomes a continuous rounded surface by rounding the end surfaces, and the discontinuous surface formed by the end surfaces of the bonded element substrate 11 and the support substrate 12 (bonded wafer) becomes a continuous rounded surface, and the discontinuous surface formed by the end surface of the bonded element substrate 11 and the support substrate 12 (bonded wafer) becomes a continuous rounded surface, and the discontinuous surface formed by the end surface of the bonded element substrate 11 and the support substrate 12 (bonded wafer) becomes a continuous rounded surface. Since there are no corners to be formed, chipping or cracking can be prevented even if the end face comes into contact with another object due to vibration during cleaning and transportation of the bonded soI, and furthermore, polishing of the element substrate can be performed without any trouble, and the element can be easily polished. The surface of the substrate becomes a highly accurate mirror surface.
以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.
本発明の第1実施例は第1図(a)〜(c)の断面図に
示され、これらの図において、説明のためウェハの大き
さ、酸化膜の膜厚は誇張して模式的に示される。素子基
板11と支持基板12はそれぞれ端面が面取りされ、そ
れぞれの表面には、形成される素子の種類によって定め
られる膜厚のSi○2膜13膜形3されている。一般に
2つの5in2膜13を合わせたその膜厚は0.1〜5
.0μmの範囲内に設定される。これらの基板は、従来
例の場合と同様に先ず室温で機械的に接着され、次いで
1200℃のアニールを行い、Sin、膜13中に取込
まれた水分のうち水素を除去し、酸素とシリコンの結合
によって強固に接合されて接合ウェハ14を構成する。A first embodiment of the present invention is shown in cross-sectional views in FIGS. 1(a) to (c), and in these figures, the size of the wafer and the thickness of the oxide film are exaggerated and schematically illustrated for the sake of explanation. shown. The end faces of the element substrate 11 and the support substrate 12 are each chamfered, and a Si2 film 13 having a thickness determined depending on the type of element to be formed is formed on each surface. Generally, the combined film thickness of two 5in2 films 13 is 0.1 to 5.
.. It is set within the range of 0 μm. These substrates are first mechanically bonded at room temperature as in the case of the conventional example, and then annealed at 1200°C to remove hydrogen from the moisture taken into the film 13 and to remove oxygen and silicon. The bonded wafer 14 is firmly bonded by bonding.
この状態で2枚の基板によって形成される端面ば不連続
面となっている(第1図(a〉)。In this state, the end surface formed by the two substrates becomes a discontinuous surface (FIG. 1(a)).
次に、第1図(b)に示すように、2枚の基板の接合ウ
ェハ14の端面の面取りを端面研削処理により行って、
不連続な面であった端面を連続した曲面をもつ端面にす
る。Next, as shown in FIG. 1(b), the end faces of the bonded wafer 14 of the two substrates are chamfered by an end face grinding process.
Turn a discontinuous end face into a continuous curved end face.
なお、接合ウェハ14の不連続な端面の面取りを行うに
は、第3図に示される知られたグラインダーを用い、チ
ャック21で保持した接合ウェハ14の端面をグライン
ダーのグラインド面22に当て、次いでアーム23でチ
ャック21を矢印方向に動かして端面を研削する。アー
ム23は図示していない駆動源に連結され、この駆動源
はアーム23を自動的に操作するようになっていて、面
取り作業は機械的に自動化して進められる。In order to chamfer the discontinuous end face of the bonded wafer 14, use a known grinder shown in FIG. The chuck 21 is moved in the direction of the arrow by the arm 23 to grind the end face. The arm 23 is connected to a drive source (not shown), and this drive source automatically operates the arm 23, so that the chamfering work is mechanically automated.
次いで、第1図(C)に示すように、素子基板11の研
削と研磨(ラフピング)を行う。このラッピングにおい
ては、素子基板11の側面は、両基板の接着面15に対
して鈍角を形成するので、砥粒の流れが阻害されること
なくスムーズに行われるので、ラフピングは素子基板1
1の全表面にわたって均一に高精度になされてミラー表
面が形成される。Next, as shown in FIG. 1(C), the element substrate 11 is ground and polished (roughing). In this lapping, the side surface of the element substrate 11 forms an obtuse angle with respect to the bonding surface 15 of both substrates, so that the flow of abrasive grains is smoothly performed without being obstructed.
The mirror surface is formed uniformly and precisely over the entire surface of the mirror.
なお、ここでの研削としては例えばダイヤモンド砥石で
削る場合が挙げられ、また、研磨としては、例えばア旦
ン系水溶液とコロイダルミリ力を研磨剤として研磨面に
供給し、研磨布(ポリエステル不織布等)で磨く場合が
挙げられる。Note that the grinding here includes, for example, cutting with a diamond whetstone, and the polishing includes, for example, supplying an aqueous Adan-based solution and colloidal millipower to the polished surface as an abrasive, and using a polishing cloth (polyester nonwoven fabric, etc.). ).
上記した第1実施例は、素子基板11、支持基板12が
それぞれ面取りされたものを用いる例であるが、本発明
の第2実施例では、第1図(d)に示されるそれぞれが
面取りされていない素子基板11aと支持基板123と
を用いる。この第2実施例でも、接合ウェハ14を端面
研削処理により面取りすると第1図(b)の構造が得ら
れ、それを研削および研磨して第1図(c)に示される
接合Solが得られる。The first embodiment described above is an example in which the element substrate 11 and the support substrate 12 are each chamfered, but in the second embodiment of the present invention, each of them is chamfered as shown in FIG. 1(d). The element substrate 11a and the support substrate 123 that are not used are used. In this second embodiment as well, when the bonded wafer 14 is chamfered by the end face grinding process, the structure shown in FIG. 1(b) is obtained, and by grinding and polishing it, the bonded Sol shown in FIG. 1(c) is obtained. .
本発明の第3実施例では、第1図(e)に示すように、
面取りした支持基板12(素子基板11)と面取りして
いない素子基板11a(支持基板12a)とを用いるも
ので、この接合ウェハを端面研削処理により面取りする
と第1図(b)の構造が、また研削および研磨すると第
1図(c)の構造が得られる点は第1実施例の場合と同
様である。In the third embodiment of the present invention, as shown in FIG. 1(e),
It uses a chamfered support substrate 12 (element substrate 11) and a non-chamfered element substrate 11a (support substrate 12a), and when this bonded wafer is chamfered by edge grinding processing, the structure shown in FIG. 1(b) is also obtained. Similar to the first embodiment, the structure shown in FIG. 1(c) is obtained by grinding and polishing.
以上の例では、素子基板と支持基板の双方が表面酸化さ
れたものであったが、支持基板12は素子基板を支持す
るだけであるので、両者の接着面での絶縁膜(SiOx
膜)の膜厚が素子基板に形成される素子のために十分な
絶縁性をもつものであれば、いずれか一方のウェハの表
面酸化を省くことができる。さらには、素子基板、支持
基板も、面取りしたものやしていないものも用いうるか
ら次の組み合わせが可能である。In the above example, both the element substrate and the support substrate were surface oxidized, but since the support substrate 12 only supports the element substrate, an insulating film (SiOx
Surface oxidation of one of the wafers can be omitted if the thickness of the wafer (film) has sufficient insulating properties for the elements formed on the element substrate. Furthermore, since the element substrate and the support substrate may be chamfered or not chamfered, the following combinations are possible.
(木頁、以下余白)
第4実施例の素子基板の表面が酸化されたものである例
は第1図<f)に示され、この場合ウェハが第1図(g
)、、、(h)に示される順に端面研削処理により面取
りされ、研削、研磨される。また、支持基板の表面のみ
が酸化された例は第1図(i)、(j)、(k)に示さ
れる。(Tree pages, blank spaces below) An example in which the surface of the element substrate of the fourth embodiment is oxidized is shown in Fig. 1<f), in which case the wafer is shown in Fig. 1 (g
), , , (h) are chamfered by end face grinding treatment, ground and polished. Further, examples in which only the surface of the support substrate is oxidized are shown in FIGS. 1(i), (j), and (k).
第5実施例は、第1図(N)に示すように、表面が酸化
され、かつ面取りしていない素子基板11a (支持基
板12a)と面取りしていない支持基板12a (素子
基板11a)とを用いるもので、この接合ウェハを端面
研削処理により面取りすると第1図(g)(第1図(j
))の構造が、また研削および研磨すると第1図(h)
(第1図(k))の構造が得られる。In the fifth embodiment, as shown in FIG. 1(N), an element substrate 11a (support substrate 12a) whose surface is oxidized and whose surface is not chamfered and a support substrate 12a (device substrate 11a) whose surface is not chamfered are used. When this bonded wafer is chamfered by edge grinding process, it is shown in Fig. 1(g) (Fig. 1(j)).
)) is also ground and polished as shown in Figure 1 (h).
The structure shown in FIG. 1(k) is obtained.
第6実施例は第1図(m)、(n)に示すように、いず
れか一方のみ面取りされ、かついずれか一方のみ表面酸
化されている場合であり、第1図(m)に示される接合
ウェハを端面研削処理による面取り、研削、研磨すると
第1図(h)の構造が得られ、また第1図(n)に示さ
れる接合ウェハを端面研削処理による面取り、研削、研
磨すると第1図(k)の構造が得られる。The sixth embodiment is a case where only one side is chamfered and only one side is surface oxidized, as shown in FIG. 1(m) and (n). When the bonded wafer is chamfered, ground, and polished by edge grinding, the structure shown in FIG. 1(h) is obtained, and when the bonded wafer shown in FIG. The structure shown in Figure (k) is obtained.
上記第1〜第6実施例では、素子基板と支持基板の少な
くも一方に酸化膜を有し接着面に酸化膜を有する場合で
あったが、素子基板、支持基板共酸化膜を有さないもの
を接着した接合ウェハの場合であってもよい。この場合
、多量の欠陥を有する支持基板とほとんど欠陥を有さな
い素子基板とで構成すれば接着面に酸化膜を有する場合
よりもゲッタリング能力を向上させることができる。以
下に各態様を示す。In the first to sixth embodiments described above, at least one of the element substrate and the support substrate has an oxide film and the adhesive surface has an oxide film, but the element substrate and the support substrate do not have a co-oxide film. This may also be the case with a bonded wafer in which objects are bonded together. In this case, if the support substrate has a large number of defects and the element substrate has almost no defects, the gettering ability can be improved more than when the bonding surface has an oxide film. Each aspect is shown below.
(本頁、以下余白)
第7実施例は、第1図(o)に示されるように、素子基
tJjE 11、支持基板12共面取りされた接合ウェ
ハを第1図(p)、(q)の順に端面研削処理による面
取り、研削、研磨した場合である。(This page, blank spaces below) In the seventh embodiment, as shown in FIG. 1(o), a bonded wafer in which both the element substrate tJjE 11 and the support substrate 12 are chamfered is bonded to a bonded wafer as shown in FIGS. 1(p) and (q). This is the case where chamfering, grinding, and polishing are performed by end face grinding treatment in this order.
第8実施例は第1図(r)に示すように、各々面取りさ
れていない素子基板11aと支持基板12aとを用いる
場合であり、また第9実施例は第1図(S)に示すよう
に、いずれか一方のみ面取りした場合であり、両者共端
面研削処理による面取りすると第1図(p)の構造が得
られ、更に研削、研磨すると第1図(q)の構造が得ら
れる。The eighth embodiment uses an element substrate 11a and a support substrate 12a that are not chamfered, as shown in FIG. In this case, only one of them is chamfered, and when both are chamfered by end face grinding, the structure shown in FIG. 1(p) is obtained, and when further grinding and polishing is performed, the structure shown in FIG. 1(q) is obtained.
なお、第1〜第9実施例では、支持基板と素子基板を接
着し、端面研削処理による面取りを行って不連続な端面
を連続した曲面にした後、素子基板を研削および研磨す
る場合について説明したが、第1図(1)〜(V)に示
すように、接合ウニハエ4の素子基板11を研削および
研磨(この研磨は次の面取り後に行ってもよい)した後
、端面研削処理による面取りを行う場合であってもよい
。この場合、各々表面酸化され、かつ各々面取りされた
接合ウェハを用いる場合であるが、第2〜第9実施例の
各態様の接合ウェハにこの製造方法を適用させることが
できる。本方法により、基板の面取形状は、表裏面で対
称となり割れ欠けの防止により大きな効果が期待できる
。In the first to ninth embodiments, a case will be described in which a supporting substrate and an element substrate are bonded, chamfering is performed by end face grinding processing to make a discontinuous end face into a continuous curved surface, and then the element substrate is ground and polished. However, as shown in FIGS. 1 (1) to (V), after grinding and polishing the element substrate 11 of the bonded sea urchin fly 4 (this polishing may be performed after the next chamfering), chamfering by end face grinding processing is performed. It may also be the case that the In this case, bonded wafers whose surfaces are oxidized and chamfered are used, but this manufacturing method can be applied to the bonded wafers of each aspect of the second to ninth embodiments. With this method, the chamfered shape of the substrate becomes symmetrical on the front and back surfaces, and a greater effect on preventing cracking and chipping can be expected.
また、上記第1図で説明した各実施例は、接合ウェハの
不連続な端面を端面研削処理による面取りを行って連続
した曲面にする場合について説明したが、この端面研削
処理後、更に研磨してミラー面にする場合であってもよ
い。Furthermore, in each of the embodiments described in FIG. 1 above, the discontinuous end face of the bonded wafer is chamfered by end face grinding processing to form a continuous curved surface, but after this end face grinding processing, further polishing is performed. It is also possible to create a mirror surface.
本発明においては、第1図(W)に示すように、素子基
板11と支持基板12が酸化膜13を介して接合してい
る接合ウェハ14において、少な(とも素子基板11の
端面が酸化膜13の端面よりも突出していないものであ
ってもよく、この場合、突出しているものよりもはがれ
難くすることができる。According to the present invention, as shown in FIG. It may be a piece that does not protrude beyond the end face of 13, and in this case, it can be made more difficult to peel off than a piece that protrudes.
以上のように本発明によれば、接合S○■の製造方法に
おいて、2枚のウェハを貼り合わせた接合ウェハの不連
続な端面を面取りして丸めることによって、欠けや割れ
を防止することができ、異物の発生が少なくなり、ゴミ
の発生による欠陥やパターン不良が減少するだけでなく
、接合ウェハを面取りすることによって素子基板の研削
と研磨が高精度に行われる効果がある。As described above, according to the present invention, in the method for manufacturing bonded S○■, chipping and cracking can be prevented by chamfering and rounding the discontinuous end face of a bonded wafer made by bonding two wafers together. This not only reduces the generation of foreign matter and reduces defects and pattern failures due to the generation of dust, but also has the effect that the grinding and polishing of the element substrate can be performed with high precision by chamfering the bonded wafer.
第1図(a)〜(W)は本発明実施例の断面図、第2図
は本発明の詳細な説明する断面図、第3図は面取り工程
を示す図、
第4図はメルト法を示す図で、その(a)は斜視図、そ
の(b)と(C)は断面図、
第5図はSIMOX法を示す断面図、
第6図は接合SOx法を示す図で、その(a)はCZ結
晶の正面図、(b)はCZ結晶の円筒加工後の正面図、
(c)はCZ結晶のオリフラ加工後の正面図、(d)〜
(f)はウェハの斜視図、その(g)〜(i)は接合ウ
ェハの断面図である。
11、11a・・・・・・素子基板
12.12a・・・・・・支持基板
13・・・・・・Sin、膜、
14・・・・・・接合ウェハ、
15・・・・・・接着面、
21・・・・・・チャンク、
22・・・・・・グラインド面、
23・・・・・・アーム、
51・・・・・・CZ結晶、
52・・・・・・筋、
53・・・・・・ウェハ、
53a・・・・・・素子基板、
53b ・・・・・・支持基手反、
54・・・・・・Si0g膜、
55・・・・・・テープ、
(素子を形成すべき基板)、
(素子基板を支持すべき基板)
56・・・・・・接着面。
第
2
図
第
図Figures 1 (a) to (W) are cross-sectional views of embodiments of the present invention, Figure 2 is a cross-sectional view explaining the present invention in detail, Figure 3 is a view showing the chamfering process, and Figure 4 is a view showing the melt method. (a) is a perspective view, (b) and (C) are cross-sectional views, Fig. 5 is a cross-sectional view showing the SIMOX method, and Fig. 6 is a view showing the bonding SOx method. ) is a front view of the CZ crystal, (b) is a front view of the CZ crystal after cylindrical processing,
(c) is a front view of the CZ crystal after orientation flat processing, (d) ~
(f) is a perspective view of the wafer, and (g) to (i) thereof are cross-sectional views of the bonded wafer. 11, 11a...Element substrate 12.12a...Support substrate 13...Sin, film, 14...Bonded wafer, 15... Adhesive surface, 21... Chunk, 22... Grind surface, 23... Arm, 51... CZ crystal, 52... Line, 53...Wafer, 53a...Element substrate, 53b...Support base, 54...Si0g film, 55...Tape, (Substrate on which the element is to be formed), (Substrate on which the element substrate is to be supported) 56... Adhesive surface. Figure 2
Claims (10)
)を接合した後に生じる接合ウェハ(14)の不連続な
端面を端面研削処理によって連続した丸めの端面とする
ことを特徴とする接合ウェハの製造方法。(1) Two or more wafers (11, 12, 11a, 12a
) A method for manufacturing a bonded wafer, characterized in that the discontinuous end surface of the bonded wafer (14) produced after bonding is made into a continuous rounded end surface by an edge grinding process.
で素子を形成すべき基板(11、11a)を薄膜化する
ことを特徴とする請求項1記載の接合ウェハの製造方法
。(2) The method for manufacturing a bonded wafer according to claim 1, characterized in that the bonded wafer (14) is subjected to end face grinding, and then the substrate (11, 11a) on which elements are to be formed is thinned.
することを特徴とする請求項2記載の接合ウェハの製造
方法。(3) The method for manufacturing a bonded wafer according to claim 2, further comprising polishing the bonded wafer (14) after the end face is ground.
膜化を研磨、または研削及び研磨により行うことを特徴
とする請求項2または3記載の接合ウェハの製造方法。(4) The method of manufacturing a bonded wafer according to claim 2 or 3, characterized in that the thinning of the substrate (11, 11a) on which the element is to be formed is performed by polishing, or by grinding and polishing.
(11、11a)を薄膜化し、次いで接合ウェハ(14
)の端面研削を行うことを特徴とする請求項1記載の接
合ウェハの製造方法。(5) The substrates (11, 11a) on which the elements of the bonded wafer (14) are to be formed are thinned, and then the bonded wafer (14) is formed into a thin film.
2. The method of manufacturing a bonded wafer according to claim 1, further comprising performing end face grinding of the bonded wafer.
することを特徴とする請求項5記載の接合ウェハの製造
方法。(6) The method for manufacturing a bonded wafer according to claim 5, further comprising polishing the bonded wafer (14) after the end face is ground.
膜化を研磨、または研削及び研磨により行うことを特徴
とする請求項5または6記載の接合ウェハの製造方法。(7) The method for manufacturing a bonded wafer according to claim 5 or 6, characterized in that the substrate (11, 11a) on which the element is to be formed is thinned by polishing, or by grinding and polishing.
基板を支持すべき基板(12、12a)を接合して得ら
れる接合ウェハ(14)の端面が連続した曲面を有する
ことを特徴とする接合ウェハ。(8) The end face of the bonded wafer (14) obtained by bonding the substrate (11, 11a) on which elements are to be formed and the substrate (12, 12a) that should support the substrate has a continuous curved surface. bonded wafer.
基板を支持すべき基板(12、12a)が絶縁膜(13
)を介して接合していることを特徴とする請求項8記載
の接合ウェハ。(9) The substrate (11, 11a) on which the element is to be formed and the substrate (12, 12a) that should support the substrate are connected to the insulating film (13).
9. The bonded wafer according to claim 8, wherein the bonded wafer is bonded via a.
いることを特徴とする請求項8記載の接合ウェハ。(10) The bonded wafer according to claim 8, wherein the end surface of the bonded wafer (14) is a mirror surface.
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Application Number | Priority Date | Filing Date | Title |
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JP15690289 | 1989-06-21 | ||
JP1-156902 | 1989-06-21 | ||
JP2159301A JP2604488B2 (en) | 1989-06-21 | 1990-06-18 | Bonded wafer and manufacturing method thereof |
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Family
ID=26484528
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001027999A1 (en) * | 1999-10-14 | 2001-04-19 | Shin-Etsu Handotai Co., Ltd. | Bonded wafer producing method and bonded wafer |
WO2002084738A1 (en) * | 2001-04-06 | 2002-10-24 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and its manufacturing method |
JP2005533397A (en) * | 2002-07-17 | 2005-11-04 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method for expanding the area of a useful layer of material that is transferred to a support |
JP2013098435A (en) * | 2011-11-02 | 2013-05-20 | Toyota Motor Corp | Soi wafer and soi wafer manufacturing method |
JP2018078149A (en) * | 2016-11-07 | 2018-05-17 | 株式会社デンソー | Semiconductor wafer and manufacturing method therefor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61256621A (en) * | 1985-05-08 | 1986-11-14 | Toshiba Corp | Production of bound-type semiconductor substrate |
JPS6471655A (en) * | 1987-09-11 | 1989-03-16 | Nippon Denso Co | Semiconductor substrate |
-
1990
- 1990-06-18 JP JP2159301A patent/JP2604488B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61256621A (en) * | 1985-05-08 | 1986-11-14 | Toshiba Corp | Production of bound-type semiconductor substrate |
JPS6471655A (en) * | 1987-09-11 | 1989-03-16 | Nippon Denso Co | Semiconductor substrate |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001027999A1 (en) * | 1999-10-14 | 2001-04-19 | Shin-Etsu Handotai Co., Ltd. | Bonded wafer producing method and bonded wafer |
US6797632B1 (en) | 1999-10-14 | 2004-09-28 | Shin-Etsu Handotai Co., Ltd. | Bonded wafer producing method and bonded wafer |
KR100733112B1 (en) * | 1999-10-14 | 2007-06-27 | 신에쯔 한도타이 가부시키가이샤 | Bonded wafer producing method |
WO2002084738A1 (en) * | 2001-04-06 | 2002-10-24 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and its manufacturing method |
US7560313B2 (en) | 2001-04-06 | 2009-07-14 | Shin-Etsu Handotai Co., Ltd. | SOI wafer and method for producing the same |
JP2005533397A (en) * | 2002-07-17 | 2005-11-04 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method for expanding the area of a useful layer of material that is transferred to a support |
JP2013098435A (en) * | 2011-11-02 | 2013-05-20 | Toyota Motor Corp | Soi wafer and soi wafer manufacturing method |
JP2018078149A (en) * | 2016-11-07 | 2018-05-17 | 株式会社デンソー | Semiconductor wafer and manufacturing method therefor |
Also Published As
Publication number | Publication date |
---|---|
JP2604488B2 (en) | 1997-04-30 |
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